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X9261

Dual Digitally-Controlled (XDCP

) Potentiometers

FEATURES

· DualTwo Separate Potentiometers
· 256 resistor taps/pot0.4% resolution
· SPI Serial Interface for write, read, and transfer

operations of the potentiometer single supply
device

· Wiper Resistance, 100

typical @ V

= 5V

· 4 Nonvolatile Data Registers for Each

Potentiometer

· Nonvolatile Storage of Multiple Wiper Positions
· Power On Recall Loads Saved Wiper Position on

Power Up.

· Standby Current < 5µA Max
· 50K

, 100K

versions of End to End Resistance

· 100 yr. Data Retention
· Endurance: 100,000 Data Changes per Bit per

Register

· 24-Lead SOIC, 24-Lead TSSOP, 16-Lead CSP

(Chip Scale Package)

· Low Power CMOS
· Power Supply V

= 2.7V to 5.5V

DESCRIPTION

The X9261 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four non-
volatile Data Registers that can be directly written to
and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default Data Register (DR0) to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

Single Supply / Low Power / 256-tap / SPI bus

PPLICATION

OTES

AND

EVELOPMENT

YSTEM

A V A I L A B L E

AN99 · AN115 · AN124 ·AN133 · AN134 · AN135

FUNCTIONAL DIAGRAM

Bus

Interface

and Control

SPI

Bus

Address

Data

Status

Write
Read

Transfer

50K

or 100K versions

Inc/Dec

Power On Recall

Wiper Counter

Data Registers

(DR0-DR3)

Interface

Control

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DETAILED FUNCTIONAL DIAGRAM

Wiper

Counter

(WCR)

Resistor

Array
Pot 1

Wiper

Counter

(WCR)

Data

Pot 0

INTERFACE

AND

CONTROL

CIRCUITRY

256-taps

50K

and 100K

SCK

HOLD

Power On

Recall

Power On

Recall

CIRCUIT LEVEL APPLICATIONS

· Vary the gain of a voltage amplifier

· Provide programmable dc reference voltages for

comparators and detectors

· Control the volume in audio circuits

· Trim out the offset voltage error in a voltage amplifier

circuit

· Set the output voltage of a voltage regulator

· Trim the resistance in Wheatstone bridge circuits

· Control the gain, characteristic frequency and

Q-factor in filter circuits

· Set the scale factor and zero point in sensor signal

conditioning circuits

· Vary the frequency and duty cycle of timer ICs

· Vary the dc biasing of a pin diode attenuator in RF

circuits

· Provide a control variable (I, V, or R) in feedback

circuits

SYSTEM LEVEL APPLICATIONS

· Adjust the contrast in LCD displays

· Control the power level of LED transmitters in

communication systems

· Set and regulate the DC biasing point in an RF power

amplifier in wireless systems

· Control the gain in audio and home entertainment

systems

· Provide the variable DC bias for tuners in RF wireless

systems

· Set the operating points in temperature control

systems

· Control the operating point for sensors in industrial

systems

· Trim offset and gain errors in artificial intelligent

systems

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PIN CONFIGURATION

PIN ASSIGNMENTS

Pin

(SOIC/TSSOP)

Pin

CSP

Symbol

Function

Serial Data Output for SPI bus

Device Address for SPI bus.

N/A

No Connect.

N/A

No Connect.

N/A

No Connect.

N/A

No Connect.

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

Device Address for SPI bus.

Hardware Write Protect

Serial Data Input for SPI bus

Device Address for SPI bus.

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

N/A

No Connect

N/A

No Connect

N/A

No Connect

N/A

No Connect

SCK

Serial Clock for SPI bus

HOLD

Device select. Pause the SPI serial bus.

Preliminary Pinout for CSP (Call factory for availability)

CSP

HOLD

SCK

SOIC/TSSOP

X9261

HOLD

SCK

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PIN DESCRIPTIONS

Bus Interface Pins

ERIAL

UTPUT

(SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL

NPUT

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL

LOCK

(SCK)

The SCK input is used to clock data into and out of the
X9261.

OLD

(HOLD)

HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

EVICE

DDRESS

(A1A0)

The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9261.

HIP

ELECT

(CS)

When CS is HIGH, the X9261 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9261, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Potentiometer Pins

, R

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2sets of R

and

such that R

and R

are the terminals of POT 0

and so on.

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 2
potentiometers, there are 2 sets of R

such that R

is the terminals of POT 0 and so on.

Supply Pins

YSTEM

UPPLY

OLTAGE

)

AND

UPPLY

ROUND

)

The V

pin is the system supply voltage. The V

is the system ground.

Other Pins

ONNECT

No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.

ARDWARE

RITE

ROTECT

NPUT

(WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

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PRINCIPLES OF OPERATION

Serial Interface

The X9261 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9261 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R

and R

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).

Power Up and Down Requirements.

There are no restrictions on the power-up or power-
down conditions of V

and the voltages applied to the

potentiometer pins provided that V

is always more

positive than or equal to V

, V

, and V

, i.e., V

, V

. The V

ramp rate specification is always in

effect.

Figure 1. Detailed Potentiometer Block Diagram

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

SERIAL
BUS
INPUT

PARALLEL

BUS
INPUT

COUNTER

REGISTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCK

UP/DN

C
O
U
N
T
E
R

D
E
C
O
D
E

IF WCR = 00[H] THEN R

= R

IF WCR = FF[H] THEN R

= R

WIPER

(WCR)

One of Two Potentiometers

(DR0)

(DR1)

(DR2)

(DR3)

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DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9261 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9261 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR.

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).

Status Register (SR)

This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.

When WIP=1, indicates that high-voltage write cycle

is in progress.

When WIP=0, indicates that no high-voltage write

cycle is in progress.

Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

(MSB)

(LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

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DEVICE DESCRIPTION

Instructions

DENTIFICATION

YTE

( ID

AND

A )

The first byte sent to the X9261 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device id for the X9261; this is fixed as 0101[B] (refer to
Table 3).

The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A3-A0 input pins. The slave address is
externally specified by the user. The X9261 compares
the serial data stream with the address input state; a

successful compare of both address bits is required for
the X9261 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A3-A0 inputs
can be actively driven by CMOS input signals or tied
to V

or V

NSTRUCTION

YTE

( I[3:0] )

The next byte sent to the X9261 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.

Table 3. Identification Byte Format

Table 4. Instruction Byte Format

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Slave Address

(MSB)

(LSB)

Instruction

Pot Selection

Opcode

Selection

(WCR Selection)

Data

Register Selection

Register Selected

DR0

DR1

DR2

DR3

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DEVICE DESCRIPTION

Instructions

Four of the ten instructions are three bytes in length.
These instructions are:

Read Wiper Counter Register read the current

wiper position of the selected potentiometer,

Write Wiper Counter Register change current

wiper position of the selected potentiometer,

Read Data Register read the contents of the

selected Data Register;

Write Data Register write a new value to the

selected Data Register.

Read Status - This command returns the contents of

the WIP bit which indicates if the internal write cycle
is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

WRL

. A transfer

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register. The Read Status Register
instruction is the only unique format (see Figure 5).

Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9261; either between the host and one

of the data registers or directly between the host and
the Wiper Counter Register. These instructions are:

XFR Data Register to Wiper Counter Register

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

Global XFR Data Register to Wiper Counter

Register This transfers the contents of all specified
Data Registers to the associated Wiper Counter
Registers.

Global XFR Wiper Counter Register to Data

Register This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (see
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9261 has responded with
an acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
SCL clock pulse (t

HIGH

) while SI is HIGH, the selected

wiper will move one resistor segment towards the R

terminal. Similarly, for each SCL clock pulse while SI is
LOW, the selected wiper will move one resistor
segment towards the R

terminal. A detailed illustration

of the sequence and timing for this operation are
shown. See Instruction format for more details.

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Figure 2. Two-Byte Instruction Sequence

Figure 3. Three-Byte Instruction Sequence (Write)

Figure 4. Three-Byte Instruction Sequence (Read)

ID3 ID2 ID1 ID0

RB RA

SCK

Device ID

Internal

Instruction

Opcode

Address

Pot/WCR

Address

A1 A0

I3 I2

RB RA

SCL

D7 D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/WCR
Address

WCR[7:0]

Data Register Bit [7:0]

A1 A0

RB RA

SCL

D7 D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/WCR

Address

WCR[7:0]

Don't Care

Data Register Bit [7:0]

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Figure 5. Three-Byte Instruction Sequence (Read Status Register)

Figure 6. Increment/Decrement Instruction Sequence

Figure 7. Increment/Decrement Timing Limits

WIP

Status

Bit

A1 A0

RB RA

SCL

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/WCR
Address

A1 A0

RB RA

SCL

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction
Opcode

Address

Pot/WCR
Address

D
E

SCK

INC/DEC CMD ISSUED

tWRID

VOLTAGE OUT

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Table 5. Instruction Set

Note:

1/0 = data is one or zero

Instruction

Instruction Set

Operation

Read Wiper Counter
Register

1/0

Read the contents of the Wiper Counter
Register pointed to by P0

Write Wiper Counter
Register

1/0

Write new value to the Wiper Counter
Register pointed to by P0

Read Data Register

1/0

Read the contents of the Data Register
pointed to by P0 and RB-RA

Write Data Register

1/0

Write new value to the Data Register
pointed to by P0 and RB-RA

XFR Data Register to
Wiper Counter Register

1/0

Transfer the contents of the Data Register
pointed to by P0 and RB-RA to its
associated Wiper Counter Register

XFR Wiper Counter
Register to Data Register

1/0

Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data Reg-
ister pointed to by RB-RA

Global XFR Data Registers
to Wiper Counter Registers

1/0

Transfer the contents of the Data Registers
pointed to by RB-RA of all four pots to their
respective Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

1/0

Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB-RA of all four pots

Increment/Decrement
Wiper Counter Register

1/0

Enable Increment/decrement of the Control
Latch pointed to by P0

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INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Wiper Position

(Sent by X9261 on SO)

Rising

Edge

0 A1 A0 1

C
R

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

0 A1 A0 1

0 P0

C
R

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Data Byte

(Sent by X9271 on SO)

Rising

Edge

0 A1 A0 1

1 RB RA

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 0 A1 A0 1 1 0 0 RB RA

0 P0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

Addresses

Rising

Edge

0 A1 A0 0

RB RA

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Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Increment/Decrement Wiper Counter Register (WCR)

Read Status Register (SR)

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(2) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

Addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 0 A1 A0 1 0 0 0 RB RA 0 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 0 A1 A0 1 1 1 0 RB RA

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Rising

Edge

0 0 A1 A0 1 1 0 1 RB RA

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Increment/Decrement

(Sent by Master on SDA)

Rising

Edge

0 A1 A0 0

X X

0 P0 I/D I/D

I/D I/D

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Data Byte

(Sent by X9261 on SO)

Rising

Edge

0 A1 A0 0

WIP

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ....................65

°C to +135°C

Storage temperature .........................65

°C to +150°C

Voltage on SCK any address input

with respect to V

.................................. 1V to +7V

V = | (V

VL) | .......................................................... 5.5V

Lead temperature (soldering, 10 seconds).........300

°C

(10 seconds) ................................................. ±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

POTENTIOMETER CHARACTERISTICS

(Over recommended industrial operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R

) / 255, single pot

(4) During power up V

> V

, V

, and V

(5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

100

T version

TOTAL

End to End Resistance

U version

End to End Resistance Tolerance

±20

Power Rating

°C, each pot

Wiper Current

±3

Wiper Resistance

300

±3mA @ V+ = 3V

Wiper Resistance

150

±3mA @ V+ = 5V

TERM

Voltage on any R

or R

= 0V

Noise

-120

dBV

Ref: 1V

Resolution

0.4

Absolute Linearity

(1)

±1

(3)

w(n)(actual)

w(n)(expected)

(5)

Relative Linearity

(2)

±0.6

(3)

w(n + 1)

w(n) + MI

]

(5)

Temperature Coefficient of R

TOTAL

±300

ppm/

°C

Ratiometric Temp. Coefficient

ppm/°C

Potentiometer Capacitances

10/10/25

See Macro model

, R

Leakage

0.1

10.0

µA

Device in stand by.
Vin = V

to V

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

°C

+70

°C

Industrial

°C

+85

°C

Device

Supply Voltage (V

)

(4)

Limits

X9261

±10%

X9261-2.7

2.7V to 5.5V

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D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of V

and the voltages applied to the poten-

tiometer pins provided that V

is always more positive than or equal to V

, V

, and V

, i.e., V

, V

. The

power-up timing spec is always in effect.

A.C. TEST CONDITIONS

Notes: (6) This parameter is not 100% tested

(7) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

-) is stable until the specific instruction can be

issued. These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

supply current

(active)

400

µA

SCK

= 2.5 MHz, SO = Open, V

=6V

Other Inputs = V

CC2

supply current

(nonvolatile write)

SCK

= 2.5MHz, SO = Open, V

=6V

Other Inputs = V

current (standby)

µA

SCK = SI = V

, Addr. = V

CS = V

= 6V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 1

Input LOW voltage

x 0.3

Output LOW voltage

0.4

= 3mA

Output HIGH voltage

- 0.8

= -1mA, V

+3V

Output HIGH voltage

- 0.4

= -0.4mA, V

+3V

Parameter

Min.

Units

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Units

Test Conditions

OUT

(6)

Output capacitance (SO)

OUT

= 0V

(6)

Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK)

= 0V

Symbol

Parameter Min.

Max.

Units

(6)

Power-up rate

0.2

V/ms

PUR

(7)

Power-up to initiation of read operation

nput Pulse Levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

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EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

Symbol

Parameter

Min.

Max.

Units

SCK

SSI/SPI clock frequency

MHz

CYC

SSI/SPI clock cycle rime

500

SSI/SPI clock high rime

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

µs

SI, SCK, HOLD and CS input fall time

µs

DIS

SO output disable time

250

SO output valid time

200

SO output hold time

SO output rise time

100

SO output fall time

100

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

CS deselect time

µs

WPASU

WP, A0, A1 setup time

WPAH

WP, A0, A1 hold time

10pF

TOTAL

25pF

10pF

SPICE Macromodel

1462

100pF

SO pin

2714

1382

100pF

SO pin

1217

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

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HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Typ.

Max.

Units

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max. Units

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

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APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100K

10K

-12V

+12V

TL072

}

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

21 of 25

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Application Circuits (continued)

Attenuator

Filter

Inverting Amplifier

Equivalent L-R Circuit

= G V

-1/2

G +1/2

= 1 + R

fc = 1/(2

RC)

= R

+ s R

+ R

) C

= R

+ s Leq

+ R

) >> R

Function Generator

= R

= 10k

}

= G V

G = - R

}

frequency

, R

, C

amplitude

, R

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

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PACKAGING INFORMATION

Ball Matrix:

HOLD

Vss

SCK

Vcc

Package Dimensions

Symbol

Millimeters

Inches

Min

Nominal

Max

Min

Nominal

Max

Package Width

2.745

2.775

2.805

Package Length

4.523

4.553

4.583

Package Height

0.644

0.677

0.710

Body Thickness

0.444

0.457

0.470

Ball Height

0.200

0.220

0.240

Ball Diameter

0.300

0.320

0.340

Ball Pitch Width

0.65

Ball Pitch Length

0.65

Ball to Edge Spacing Width

0.388

0.413

0.438

Ball to Edge Spacing Length

1.277

1.302

1.327

9261TRR

YWW I

LOT #

16-Bump Chip Scale Package (CSP B16)
Package Outline Drawing

Side View

Top View (Marking Side)

Bottom View (Bumped Side)

Side View

X9261

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

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PACKAGING INFORMATION

0.290 (7.37)
0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

0.014 (0.35)
0.020 (0.50)

Pin 1

Pin 1 Index

0.050 (1.27)

0.598 (15.20)
0.610 (15.49)

0.003 (0.10)
0.012 (0.30)

0.092 (2.35)
0.105 (2.65)

(4X) 7°

24-Lead Plastic Small Outline Gull Wing Package Type S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.420"

0.050" Typical

0.050"

Typical

0.030" Typical

24 Places

FOOTPRINT

0.010 (0.25)

0.020 (0.50)

0.015 (0.40)
0.050 (1.27)

0.009 (0.22)

0.013 (0.33)

0° 8°

X 45°

X9261

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.1.11 2/17/03

Characteristics subject to change without notice.

25 of 25

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ORDERING INFORMATION

Device

Limits

Blank = 5V ±10%
2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = 40°C to +85°C

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B16 = 16-Lead CSP (Contact Factory

for availability)

Potentiometer Organization

Pot

U =

50K

T =

100K

X9261

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9261UB16-2.7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9261UB16-2.7