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Электронный компонент: X9401YS24

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REV 1.8 10/1/03
Characteristics subject to change without notice.
1 of 21
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Low Noise/Low Power/SPI Bus
X9401
Preliminary Information
Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP
TM
)
FEATURES
Quad4 separate pots, 64 taps/pot
Nonvolatile storage of wiper position
Four Nonvolatile Data Registers for Each Pot
16-bytes of EEPROM memory
SPI serial interface
R
Total
= 10k
Wiper resistance = 150
typical
Standby current < 1A (total package)
Operating current < 400A max.
V
CC
= 2.7V to 5V
Packages24-lead TSSOP, SOIC, CSP (Chip
Scale Package)
100 year data retention
DESCRIPTION
The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
Interface
and
Control
Circuitry
CS
SCK
SO
A0
A1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
H1
/R
H1
V
L1
/R
L1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
V
L0
/R
L0
Data
8
V
W0
/R
W0
V
W1
/R
W1
R0 R1
R2 R3
Resistor
Array
V
H2
/R
H2
V
L2
/R
L2
V
W2
/R
W2
R0 R1
R2 R3
Resistor
Array
V
H3
/R
H3
V
L3
/R
L3
V
W3
/R
W3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Pot 3
Pot 2
HOLD
Pot 0
V
CC
V
SS
WP
SI
A
PPLICATION
N
OTES
A V A I L A B L E
AN99 AN115 AN120 AN124 AN133 AN134
X9401 Preliminary Information
Characteristics subject to change without notice.
2 of 21
REV 1.8 10/1/03
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PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
Chip Select (CS)
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it in
the active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial com-
munication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause fea-
ture is not used, HOLD should be held HIGH at all times.
Device Address (A
0
A
1
)
The address inputs are used to set the least significant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input
in order to initiate communication with the X9401. A
maximum of 4 devices may occupy the SPI serial bus.
Potentiometer Pins
V
H
(V
H0
V
H3
), V
L
(V
L0
V
L3
), R
H
(R
H0
R
H3
),
R
L
(R
L0
R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
(V
W0
V
W3
), R
W
(R
W0
R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.
PIN CONFIGURATION
V
CC
V
L0
/R
L0
V
H0
/R
H0
WP
SI
A
1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
NC
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
SO
HOLD
SCK
V
L2
/R
L2
V
H2
/R
H2
SOIC
X9401
V
SS
V
W0
/R
W0
14
13
11
12
CS
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
W2
/R
W2
NC
SI
A
1
V
H2
/R
H2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
CS
V
W0
/R
W0
V
CC
NC
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
TSSOP
X9401
V
W2
/R
W2
14
13
11
12
HOLD
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
A
0
SO
V
H0
/R
H0
NC
SCK
V
L2
/R
L2
V
L0
/R
L0
V
SS
2
3
4
A
B
C
D
E
F
Top ViewBumps Down
V
W0
/R
W0
V
L0
/R
L0
NC
A
0
HOLD
V
L1
/R
L1
V
CC
V
L3
/R
L3
V
W3
/R
W3
SO
SI
V
W1
/R
W1
SCK
V
L2
/R
L2
WP
NC
V
H0
/R
H0
V
H1
/R
H1
V
H3
/R
H3
V
H2
/R
H2
V
SS
V
W2
/R
W2
CS
A
1
1
CSP
X9401
Preliminary Information
Characteristics subject to change without notice.
3 of 21
REV 1.8 10/1/03
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PIN NAMES
DEVICE DESCRIPTION
The X9401 is a highly integrated microcircuit incorpo-
rating four resistor arrays and their associated regis-
ters and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware con-
ventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9401 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is equiv-
alent to a serial-in, parallel-out register/counter with its
outputs decoded to select one of sixty-four switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the Write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register or Global XFR Data Regis-
ter instructions (parallel load); it can be modified one
step at a time by the Increment/Decrement instruction.
Finally, it is loaded with the contents of its data register
zero (R0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9401 is powered-
down. Although the register is automatically loaded
with the value in R
0
upon power-up, this may be differ-
ent from the value present at power-down. The wiper
position must be stored in R
0
to insure restoring the
wiper position after power-up.
Data Registers
Each potentiometer has four 6-bit nonvolatile data reg-
isters. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the data registers can
be used as memory locations for system parameters
or user preference data.
Data Register Detail
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A
0
-A
1
Device Address
V
H0
/R
H0
V
H3
/R
H3
,
V
L0
/R
L0
V
L3
/R
L3
Potentiometers (terminal
equivalent)
V
W0
/R
W0
V
W1
/R
W1
Potentiometers (wiper
equivalent)
WP
Hardware Write Protection
V
CC
System Supply Voltage
V
SS
System Ground
NC
No Connection
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
X9401 Preliminary Information
Characteristics subject to change without notice.
4 of 21
REV 1.8 10/1/03
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Write in Process
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
-A
1
input pins.
The X9401 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A
0
A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 2.
1
0
0
0
0
A1
A0
Device Type
Identifier
Device Address
1
Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
Register 2
Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
V
H
/R
H
V
L
/R
L
V
W
/R
W
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
8
6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
(One of Four Arrays)
X9401
Preliminary Information
Characteristics subject to change without notice.
5 of 21
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Figure 2. Instruction Byte Format
The four high order bits of the instruction byte specify
the operation. The next two bits (R
1
and R
0
) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P
0
) selects which one of the four potentiome-
ters is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
XFR Data Register to Wiper Counter Register--This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register--This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
Global XFR Data Register to Wiper Counter Register --
This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.
Global XFR Wiper Counter Register to Data Register--
This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions exchange
data between the WCR and one of the data registers. A
transfer from a data register to a WCR is essentially a
write to a static RAM, with the static RAM controlling the
wiper position. The response of the wiper to this action
will be delayed by t
WRL
. A transfer from the WCR (cur-
rent wiper position), to a data register is a write to nonvol-
atile memory and takes a minimum of t
WR
to complete.
The transfer can occur between one of the four potenti-
ometers and one of its associated registers; or it may
occur globally, where the transfer occurs between all
potentiometers and one associated register.
Five instructions require a three-byte sequence to com-
plete. These instructions transfer data between the host
and the X9401; either between the host and one of the
data registers or directly between the host and the
Wiper Counter Register. These instructions are:
Read Wiper Counter Register-- read the current
wiper position of the selected pot,
Write Wiper Counter Register--change current wiper
position of the selected pot,
Read Data Register--read the contents of the
selected data register;
Write Data Register--write a new value to the
selected data register.
Read Status--This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 4
and Figure 5.
The final command is Increment/Decrement. It is differ-
ent from the other commands, because it's length is
indeterminate. Once the command is issued, the mas-
ter can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (t
HIGH
)
while SI is HIGH, the selected wiper will move one
resistor segment towards the V
H
/R
H
terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the V
L
/R
L
terminal. A detailed illustration of the sequence and tim-
ing for this operation are shown in Figure 6 and Figure 7.
I1
I2
I3
I0
R1
R0
P1
P0
Pot Select
Register
Select
Instructions
X9401
Preliminary Information
Characteristics subject to change without notice.
6 of 21
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Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence (Write)
Figure 5. Three-Byte Command Sequence (Read)
Figure 6. Increment/Decrement Command Sequence
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1
R0
P1 P0
SCK
SI
CS
0
1
0
1
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
SCL
SI
0
0
D5 D4 D3 D2
D1 D0
CS
0
0
0
1
0
1
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
SCL
SI
CS
0
0
S0
0
0
D5 D4 D3 D2
D1 D0
Don't Care
0
1
0
1
0
0
A1 A0
I3
I2
I1
I0
0
P1
P0
SCK
SI
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
CS
X9401
Preliminary Information
Characteristics subject to change without notice.
7 of 21
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Figure 7. Increment/Decrement Timing Limits
Table 1. Instruction Set
Instruction
Instruction Set
Operation
I
3
I
2
I
1
I
0
R
1
R
0
P
1
P
0
Read Wiper Counter Register
1
0
0
1
0
0
P
1
P
0
Read the contents of the Wiper Counter Register
pointed to by P
1
-P
0
Write Wiper Counter Register
1
0
1
0
0
0
P
1
P
0
Write new value to the Wiper Counter Register
pointed to by P
1
-P
0
Read Data Register
1
0
1
1
R
1
R
0
P
1
P
0
Read the contents of the Data Register pointed to
by P
1
-P
0
and R
1
R
0
Write Data Register
1
1
0
0
R
1
R
0
P
1
P
0
Write new value to the Data Register pointed to by
P
1
-P
0
and R
1
R
0
XFR Data Register to Wiper
Counter Register
1
1
0
1
R
1
R
0
P
1
P
0
Transfer the contents of the Data Register pointed
to by R
1
R
0
to the Wiper Counter Register pointed
to by P
1
-P
0
XFR Wiper Counter Register
to Data Register
1
1
1
0
R
1
R
0
P
1
P
0
Transfer the contents of the Wiper Counter Register
pointed to by P
1
-P
0
to the Register pointed to by
R
1
R
0
Global XFR Data Register to
Wiper Counter Register
0
0
0
1
R
1
R
0
0
0
Transfer the contents of the Data Registers pointed
to by R
1
R
0
of all four pots to their respective Wiper
Counter Register
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R
1
R
0
0
0
Transfer the contents of all Wiper Counter Regis-
ters to their respective data Registers pointed to by
R
1
R
0
of all four pots
Increment/Decrement Wiper
Counter Register
0
0
1
0
0
0
P
1
P
0
Enable Increment/decrement of the Wiper Counter
Register pointed to by P
1
-P
0
Read Status (WIP bit)
0
1
0
1
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
SCK
SI
V
W
/R
W
INC/DEC CMD Issued
t
WRID
Voltage Out
X9401 Preliminary Information
Characteristics subject to change without notice.
8 of 21
REV 1.8 10/1/03
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Instruction Format
Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9401 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
0
1
0
0
P
1
P
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
1
0
0
0
P
1
P
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by X9401 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
1
0
1
1
R
1
R
0
P
1
P
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
Data Byte
(sent by host on SI)
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0 0
A
1
A
0
1 1 0 0
R
1
R
0
P
1
P
0
0 0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
CS
Rising
Edge
0 1 0 1 0 0
A
1
A
0
1 1 0 1
R
1
R
0
P
1
P
0
X9401
Preliminary Information
Characteristics subject to change without notice.
9 of 21
REV 1.8 10/1/03
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Read Status
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0 0
A
1
A
0
1 1 1 0
R
1
R
0
P
1
P
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
increment/decrement
(sent by master on SDA)
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
0
0
1
0
X X
P
1
P
0
I/
D
I/
D
.
.
.
.
I/
D
I/
D
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
0
0
0
1
R
1
R
0
0
0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0 0
A
1
A
0
1 0 0 0
R
1
R
0
0 0
CS
Falling
Edge
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9401 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A
1
A
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
W
I
P
X9401
Preliminary Information
Characteristics subject to change without notice.
10 of 21
REV 1.8 10/1/03
www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias.................... 65
C to +135C
Storage temperature......................... 65
C to +150C
Voltage on SCK, SCL or any address
input with respect to V
SS
........................ 1V to +7V
V = |(V
H
V
L
)| ......................................................5.5V
Lead temperature (soldering, 10 seconds) ........ 300
C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Device
Supply Voltage (V
CC
) Limits
X9401
5V
10%
X9401-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
POWER UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V
CC
and the voltages applied to the poten-
tiometer pins provided that V
CC
is always more positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
, V
W
.
The V
CC
power-up spec is always in effect.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V
H
V
L
)/63, single pot
Symbol
Parameter
Limits
Test Condition
Min.
Typ.
Max.
Unit
R
TOTAL
End to end resistance
20
+20
%
Power rating
50
mW
25
C, each pot
I
W
Wiper current
6
+6
mA
R
W
Wiper resistance
150
500
Wiper Current =
3mA
V
TERM
Voltage on any V
H
or V
L
Pin
V
SS
V
CC
V
V
SS
= 0V
Noise
-120
dBV
Ref: 1kHz
Resolution
1.6
%
Absolute linearity
(1)
1
+1
MI
(3)
V
w(n)(actual)
--V
w(n)(expected)
Relative linearity
(2)
0.2
+0.2
MI
(3)
V
w(n + 1)
--[V
w(n) + MI
]
Temperature coefficient of R
TOTAL
300
ppm/
C
Ratiometric temp. coefficient
20
ppm/C
C
H
/C
L
/C
W
Potentiometer capacitances
10/10/25
pF
See Macro model
I
AL
R
H
, R
L
, R
W
leakage current
0.1
10
A
V
IN
= V
SS
to V
CC
. Device is in
stand-by mode.
X9401
Preliminary Information
Characteristics subject to change without notice.
11 of 21
REV 1.8 10/1/03
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Unit
I
CC1
V
CC
supply current (active)
400
A
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
I
CC2
V
CC
supply current (nonvola-
tile write)
1
mA
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
I
SB
V
CC
current (standby)
1
A
SCK = SI = V
SS
, Addr. = V
SS
,
CS = V
CC
I
LI
Input leakage current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output leakage current
10
A
V
OUT
= V
SS
to V
CC
V
IH
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
IL
Input LOW voltage
0.5
V
CC
x 0.1
V
V
OL
Output LOW voltage
0.4
V
I
OL
= 3mA
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
Symbol
Test
Max.
Unit
Test Condition
C
OUT
(4)
Output capacitance (SO)
8
pF
V
OUT
= 0V
C
IN
(4)
Input capacitance (A0, A1, SI, and SCK)
6
pF
V
IN
= 0V
Symbol
Parameter Min.
Max.
Unit
t
r
V
CC
(6)
V
CC
Power-up rate
0.2
50
V/ms
t
PUR
(5)
Power-up to initiation of read operation
1
ms
t
PUW
(5)
Power-up to initiation of write operation
5
ms
A.C. TEST CONDITIONS
Notes: (4) This parameter is periodically sampled and not 100%
tested
(5) t
PUR
and t
PUW
are the delays required from the time the
(last) power supply (V
CC
-) is stable until the specific
instruction can be issued. These parameters are periodi-
cally sampled and not 100% tested.
(6) This is not a tested or guaranteed parameter and should
be used only as a guideline.
EQUIVALENT A.C. LOAD CIRCUIT
I
nput pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
5V
1533
100pF
SDA
Output
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macro Model
X9401
Preliminary Information
Characteristics subject to change without notice.
12 of 21
REV 1.8 10/1/03
www.xicor.com
AC TIMING
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Symbol
Parameter
Min.
Max.
Unit
f
SCK
SSI/SPI clock frequency
2.0
MHz
t
CYC
SSI/SPI clock cycle rime
500
ns
t
WH
SSI/SPI clock high rime
200
ns
t
WL
SSI/SPI clock low time
200
ns
t
LEAD
Lead time
250
ns
t
LAG
Lag time
250
ns
t
SU
SI, SCK, HOLD and CS input setup time
50
ns
t
H
SI, SCK, HOLD and CS input hold time
50
ns
t
RI
SI, SCK, HOLD and CS input rise time
2
s
t
FI
SI, SCK, HOLD and CS input fall time
2
s
t
DIS
SO output disable time
0
500
ns
t
V
SO output valid time
100
ns
t
HO
SO output hold time
0
ns
t
RO
SO output rise time
50
ns
t
FO
SO output fall time
50
ns
t
HOLD
HOLD time
400
ns
t
HSU
HOLD setup time
100
ns
t
HH
HOLD hold time
100
ns
t
HZ
HOLD low to output in high Z
100
ns
t
LZ
HOLD high to output in low Z
100
ns
T
I
Noise suppression time constant at SI, SCK, HOLD and CS inputs
20
ns
t
CS
CS deselect time
2
s
t
WPASU
WP, A0 and A1 setup time
0
ns
t
WPAH
WP, A0 and A1 hold time
0
ns
Symbol
Parameter
Typ.
Max.
Unit
t
WR
High-voltage write cycle time (store instructions)
5
10
ms
Symbol
Parameter
Min.
Max.
Unit
t
WRPO
Wiper response time after the third (last) power supply is stable
10
s
t
WRL
Wiper response time after instruction issued (all load instructions)
10
s
t
WRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
ns
X9401
Preliminary Information
Characteristics subject to change without notice.
13 of 21
REV 1.8 10/1/03
www.xicor.com
SYMBOL TABLE
TIMING DIAGRAMS
Input Timing
Output Timing
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB
LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
t
WH
...
CS
SCK
SO
SI
ADDR
MSB
LSB
t
DIS
t
HO
t
V
...
X9401
Preliminary Information
Characteristics subject to change without notice.
14 of 21
REV 1.8 10/1/03
www.xicor.com
Hold Timing
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
...
CS
SCK
SO
SI
HOLD
t
HSU
t
HH
t
LZ
t
HZ
t
HOLD
t
RO
t
FO
...
CS
SCK
SI
MSB
LSB
V
W
/R
W
t
WRL
...
SO
High Impedance
...
CS
SCK
SO
SI
ADDR
t
WRID
High Impedance
V
W
/R
W
...
Inc/Dec
Inc/Dec
...
X9401
Preliminary Information
Characteristics subject to change without notice.
15 of 21
REV 1.8 10/1/03
www.xicor.com
Write Protect and Device Address Pins Timing
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
CS
WP
A0
A1
t
WPASU
t
WPAH
(Any Instruction)
V
R
V
W
/R
W
+V
R
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
X9401
Preliminary Information
Characteristics subject to change without notice.
16 of 21
REV 1.8 10/1/03
www.xicor.com
Application Circuits
Noninverting Amplifier
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysteresis
+
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)
V
IN
317
+
V
S
V
O
R
2
R
1
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
V
LL
= {R
1
/(R
1
+R
2
)} V
O
(min)
100K
10K
10K
10K
+5V
TL072
+
V
S
V
O
R
2
R
1
}
}
Attenuator
Filter
+
V
S
V
O
R
3
R
1
V
O
= G V
S
-1/2
G +1/2
G
O
= 1 + R
2
/R
1
fc = 1/(2pRC)
R
2
R
4
All R
S
= 10k
+
V
S
R
2
R
1
R
C
V
O
X9401
Preliminary Information
Characteristics subject to change without notice.
17 of 21
REV 1.8 10/1/03
www.xicor.com
Application Circuits (continued)
Inverting Amplifier
Equivalent L-R Circuit
+
V
S
V
O
R
2
R
1
Z
IN
= R
2
+ s R
2
(R
1
+ R
3
) C
1
= R
2
+ s Leq
(R
1
+ R
3
) >> R
2
+
V
S
Function Generator
}
}
V
O
= G V
S
G = - R
2
/R
1
R
2
C
1
R
1
R
3
Z
IN
+
R
2
+
R
1
}
}
R
A
R
B
frequency
R
1
, R
2
, C
amplitude
R
A
, R
B
C
X9401
Preliminary Information
Characteristics subject to change without notice.
18 of 21
REV 1.8 10/1/03
www.xicor.com
PACKAGING INFORMATION
0.290 (7.37)
0.299 (7.60)
0.393 (10.00)
0.420 (10.65)
0.014 (0.35)
0.020 (0.50)
Pin 1
Pin 1 Index
0.050 (1.27)
0.598 (15.20)
0.610 (15.49)
0.003 (0.10)
0.012 (0.30)
0.092 (2.35)
0.105 (2.65)
(4X) 7
24-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.420"
0.050" Typical
0.050"
Typical
0.030" Typical
24 Places
FOOTPRINT
0.010 (0.25)
0.020 (0.50)
0.015 (0.40)
0.050 (1.27)
0.009 (0.22)
0.013 (0.33)
0 8
X 45
X9401
Preliminary Information
Characteristics subject to change without notice.
19 of 21
REV 1.8 10/1/03
www.xicor.com
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24-Lead Plastic, TSSOP Package Type V
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.026 (.65) BSC
.303 (7.70)
.311 (7.90)
.002 (.06)
.005 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
See Detail "A"
.031 (.80)
.041 (1.05)
.010 (.25)
.020 (.50)
.030 (.75)
Gage Plane
Seating Plane
Detail A (20X)
(4.16) (7.72)
(1.78)
(0.42)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
08
X9401 Preliminary Information
Characteristics subject to change without notice.
20 of 21
REV 1.8 10/1/03
www.xicor.com
PACKAGING INFORMATION\
Ball Matrix:
X9401W/X9401Y
4
3
2
1
A
RL1
A1
CS
RW0
B
RW1
SI
WP
RL0
C
VSS
RH1
RH0
VCC
D
NC
RH2
RH3
NC
E
RW2
HOLD
SO
RL3
F
RL2
SCK
A0
RW3
Package Dimensions
Symbol
Min
Nominal
Max
Millimeters
Package Width
a
2.595
2.625
2.655
Package Length
b
3.814
3.844
3.874
Package Height
c
0.644
0.677
0.710
Body Thickness
d
0.444
0.457
0.470
Ball Height
e
0.200
0.220
0.240
Ball Diameter
f
0.300
0.320
0.340
Ball Pitch Width
j
0.5
Ball Pitch Length
k
0.5
Ball to Edge Spacing Width
l
0.538
0.563
0.588
Ball to Edge Spacing Length
m
0.647
0.672
0.697
9401WRR
YWW I2.7
LO
T #
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
a
A4
A3
A2 A1
f
j
m
l
k
b
d
e
e
c
B4
B3
B2 B1
C4
C3
C2 C1
D4
D3
D2 D1
E4
E3
E2 E1
F4
F3
F2
F1
Side View
X9401
Preliminary Information
Characteristics subject to change without notice.
21 of 21
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.8 10/1/03
www.xicor.com
Xicor, Inc. 2003 Patents Pending
ORDERING INFORMATION
Device
V
CC
Limits
Blank = 5V 10%
2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0C to +70C
I = Industrial = 40C to +85C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24 Lead CSP
Potentiometer Organization
Pot 0
Pot 1
Pot 2
Pot 3
W =
10KW 10KW 10KW 10KW
Y =
2.5K
2.5K 2.5K 2.5K
X9401
P
T
V
Y