REV 1.6 1/30/03

Characteristics subject to change without notice.

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Low Noise/Low Power/2-Wire Bus

X9409

Preliminary Information

Quad Digitally Controlled Potentiometers (XDCP

)

FEATURES

· Four potentiometers per package
· 64 resistor taps
· 2-wire serial interface for write, read, and trans-

fer operations of the potentiometer

· 50

Wiper resistance, typical at 5V.

· Four non-volatile data registers for each

potentiometer

· Non-volatile storage of multiple wiper position
· Power on recall. Loads saved wiper position on

power up.

· Standby current < 1µA typical
· System V

: 2.7V to 5.5V operation

· 10K

, 2.5K

End to end resistance

· 100 yr. data retention
· Endurance: 100,000 data changes per bit per

register

· Low power CMOS
· 24-lead SOIC, 24-lead TSSOP, and

24-lead CSP (Chip Scale Package) Packages

DESCRIPTION

The X9409 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

Interface

and

Control

Circuitry

SCL

SDA

A0
A1
A2
A3

Wiper

Counter

(WCR)

Resistor

Array
Pot 1

Wiper

Counter

(WCR)

Data

Resistor

Array

Resistor

Array

Wiper

Counter

(WCR)

Wiper

Counter

(WCR)

Pot 3

Pot 2

Pot 0

PPLICATION

OTES

A V A I L A B L E

AN99 · AN115 · AN120 · AN124 · AN133 · AN134 · AN135

X9409

 Preliminary Information

Characteristics subject to change without notice.

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PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the
X9409.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

Device Address (A

)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.

Potentiometer Pins

, V

The V

and V

inputs are equivalent to the

terminal connections on either end of a mechanical
potentiometer.

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

PIN NAMES

Symbol

Description

SCL

Serial Clock

SDA

Serial Data

A0-A3

Device Address

Potentiometer Pin
(terminal equivalent)

Potentiometer Pin
(wiper equivalent)

Hardware Write Protection

System Supply Voltage

System Ground (Digital)

No Connection

PIN CONFIGURATION

SDA

SCL

SOIC

X9409

SDA

TSSOP

X9409

SCL

Top ViewBumps Down

A 0

SDA

SCL

CSP

X9409 Preliminary Information

Characteristics subject to change without notice.

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PRINCIPLES OF OPERATION

The X9409 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.

Serial Interface

The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

HIGH

). The X9409 continuously

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.

Array Description

The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9409
this is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9409 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9409 to respond with an acknowledge. The
A

inputs can be actively driven by CMOS input

signals or tied to V

or V

Device Type

Identifier

Device Address

X9409 Preliminary Information

Characteristics subject to change without notice.

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Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical nonvolatile write cycle time.
Once the stop condition is issued to indicate the end of
the nonvolatile write command the X9409 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9409 is
still busy with the write operation no ACK will be
returned. If the X9409 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

Flow 1. ACK Polling Sequence

Instruction Structure

The next byte sent to the X9409 contains the
instruction and register pointer information. The format
is shown in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last bits (P1, P0) select
which one of the four potentiometers is to be affected
by the instruction.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

WRL

. A transfer from the Wiper

Counter Register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9409; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

YES

Proceed

Issue STOP

Proceed

Pot Select

Select

Instructions

X9409 Preliminary Information

Characteristics subject to change without notice.

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Figure 3. Two-Byte Instruction Sequence

S
T
A
R
T

A
C
K

P1 P0

A
C
K

SCL

SDA

S
T
O
P

The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9409 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t

HIGH

)

while SDA is HIGH, the selected wiper will move one

resistor segment towards the V

terminal. Similarly,

for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the V

terminal. A detailed illustration of the

sequence and timing for this operation are shown in
Figures 5 and 6 respectively.

Table 1. Instruction Set

Note:

(7) 1/0 = data is one or zero

Instruction

Instruction Set

Operation

Read Wiper Counter
Register

Read the contents of the Wiper Counter
Register pointed to by P

Write Wiper Counter
Register

Write new value to the Wiper Counter Register
pointed to by P

Read Data Register

Read the contents of the Data Register pointed
to by P

and R

Write Data Register

Write new value to the Data Register pointed to
by P

and R

XFR Data Register to
Wiper Counter Register

Transfer the contents of the Data Register
pointed to by P

and R

to its associated

Wiper Counter Register

XFR Wiper Counter
Register to Data
Register

Transfer the contents of the Wiper Counter
Register pointed to by P

to the Data

Global XFR Data
Registers to Wiper
Counter Registers

Transfer the contents of the Data Registers
pointed to by R

of all four pots to their

respective Wiper Counter Registers

Global XFR Wiper
Counter Registers to
Data Register

Transfer the contents of both Wiper Counter
Registers to their respective Data Registers
pointed to by R

of all four pots

Increment/Decrement
Wiper Counter Register

Enable Increment/decrement of the WCR Latch
pointed to by P

X9409 Preliminary Information

Characteristics subject to change without notice.

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DETAILED OPERATION

All XDCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and 4 Data Registers. A
detailed discussion of the register organization and
array operation follows.

Wiper Counter Register

The X9409 contains four Wiper Counter Registers, one
for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents
of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of the four
associated Data Registers via the XFR Data Register
instruction (parallel load); it can be modified one step at
a time by the Increment/ Decrement instruction. Finally,
it is loaded with the contents of its Data Register zero
(DR0) upon power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9409 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be different
from the value present at power-down.

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile:

Four 6-bit Data Registers for each XDCP. (sixteen 6-bit
registers in total).

{D5~D0}: These bits are for general purpose not vol-

atile data storage or for storage of up to four different
wiper values. The contents of Data Register 0 are
automatically moved to the wiper counter register on
power-up.

Wiper Counter Register, (6-Bit), Volatile:

One 6-bit Wiper Counter Register for each XDCP. (Four
6-bit registers in total.)

{D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register R

The contents of the WCR can be loaded from any of
the other Data Register or directly by command. The
contents of the WCR can be saved in a DR.

(MSB)

(LSB)

WP5

WP4

WP3

WP2

WP1

WP0

(MSB)

(LSB)

X9409 Preliminary Information

Characteristics subject to change without notice.

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Instruction Format

Notes: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.

(2) "A3 ~ A0": stands for the device addresses sent by the master.
(3) "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition.
(4) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(5) "D": stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR) to Data Register (DR)

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR

addresses

S
A
C
K

wiper position

(sent by slave on SDA)

A
C
K

S
T

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR

addresses

S
A
C
K

wiper position

(sent by master on SDA)

S
A
C
K

S
T

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

wiper position

(sent by slave on SDA)

A
C
K

S
T

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

wiper position

(sent by master on SDA)

S
A
C
K

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1

1 1 0 0

0 0

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

S
T

0 1 0 1

1 1 0 1

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1

1 1 1 0

X9409 Preliminary Information

Characteristics subject to change without notice.

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Increment/Decrement Wiper Counter Register (WCR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR

addresses

S
A
C
K

increment/decrement

(sent by master on SDA)

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1

1 0 0 0

0 0

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

120

100

80 100 120

Resistance (K)

Bus Capacitance (pF)

Min.
Resistance

Max.

Resistance

MAX

BUS

MIN

OL MIN

CC MAX

=1.8K

X9409 Preliminary Information

Characteristics subject to change without notice.

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias ....................65°C to +135°C
Storage temperature .........................65°C to +150°C
Voltage on SDA, SCL or any address

input with respect to V

......................... 1V to +7V

V = |V

|........................................................ 5V

Lead temperature (soldering, 10 seconds).........300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

°C

+70

°C

Industrial

°C

+85

°C

Device

Supply Voltage (V

) Limits

X9409

±10%

X9409-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

End to end resistance tolerance

±20

Power rating

25°C, each pot @5V, 2.5K

Wiper current

-3

Wiper resistance

150

± 3mA, V

= 3V to 5V

TERM

Voltage on any V

or V

= 0V

Noise

-120

dBV

Ref: 1kHz

Resolution

(4)

1.6

Absolute linearity

(1)

-1

(3)

w(n)(actual)

--V

w(n)(expected)

Relative linearity

(2)

-0.2

+0.2

(3)

w(n + 1)

--[V

w(n) + MI

]

Temperature coefficient of R

TOTAL

±300

ppm/°C

Ratiometric temp. coefficient

ppm/°C

Potentiometer capacitances

10/10/25

See Macro Model

, R

leakage current

0.1

µA

= V

to V

. Device is

in stand-by mode.

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

--V

)/63, single pot

X9409 Preliminary Information

Characteristics subject to change without notice.

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ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V

, then the potentiometer pins, R

, R

, and R

. The V

ramp rate specification should be met, and any glitches or slope changes in the V

line should be held to <100mV

if possible. If V

powers down, it should be held below 0.1V for more than 1 second before powering up again in

order for proper wiper register recall. Also, V

should not reverse polarity by more than 0.5V. Recall of wiper

position will not be complete until V

reaches its final value.

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

) is stable until the specific instruction can be

issued. These parameters are periodically sampled and not 100% tested.

(6) Sample tested only.

D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current (Active)

100

µA

SCL

= 400kHz, SDA = Open,

Other Inputs = V

CC2

supply current

(Nonvolatile Write)

SCL

= 400kHz, SDA = Open,

Other Inputs = V

current (standby)

µA

SCL = SDA = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.5

Input LOW voltage

0.5

x 0.1

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Test

Max.

Unit

Test Conditions

I/O

(4)

Input/output capacitance (SDA)

I/O

= 0V

(4)

Input capacitance (A0, A1, A2, A3, and SCL)

= 0V

Symbol

Parameter Min.

Max.

Unit

(6)

power-up rate

0.2

V/ms

X9409 Preliminary Information

Characteristics subject to change without notice.

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AC TIMING (over recommended operating condition)

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Min.

Max.

Unit

SCL

Clock frequency

400

kHz

CYC

Clock cycle time

2500

HIGH

Clock high time

600

LOW

Clock low time

1300

SU:STA

Start setup time

600

HD:STA

Start hold time

600

SU:STO

Stop setup time

600

SU:DAT

SDA data input setup time

100

HD:DAT

SDA data input hold time

SCL and SDA rise time

300

SCL and SDA fall time

300

SCL low to SDA data output valid time

900

SDA data output hold time

Noise suppression time constant at SCL and SDA inputs

BUF

Bus free time (prior to any transmission)

1300

SU:WPA

WP, A0, A1, A2 and A3 setup time

HD:WPA

WP, A0, A1, A2 and A3 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

A.C. TEST CONDITIONS

EQUIVALENT A.C. LOAD CIRCUIT

Circuit #3 SPICE Macro Model

nput pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

10pF

TOTAL

25pF

10pF

X9409 Preliminary Information

Characteristics subject to change without notice.

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XDCP TIMING

Note:

(9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

Input Timing

Output Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement
instruction)

µs

SU:STA

HD:STA

SU:STO

SCL

SDA

(START)

(STOP)

SCL

SDA

HIGH

LOW

CYC

HD:DAT

SU:DAT

BUF

SCL

SDA

X9409 Preliminary Information

Characteristics subject to change without notice.

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APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;
Variable voltage divider

Two terminal Variable Resistor;
Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysteresis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100K

10K

TL072

}

X9409 Preliminary Information

Characteristics subject to change without notice.

20 of 21

REV 1.6 1/30/03

www.xicor.com

PACKAGING INFORMATION

Ball Matrix:

X9409W/X9409Y

RL1

RW0

RW1

SDA

RL0

VSS

RH1

RH0

VCC

RH2

RH3

RW2

RL3

RL2

SCL

RW3

Package Dimensions

Symbol

Min

Nominal

Max

Millimeters

Package Width

2.595

2.625

2.655

Package Length

3.814

3.844

3.874

Package Height

0.644

0.677

0.710

Body Thickness

0.444

0.457

0.470

Ball Height

0.200

0.220

0.240

Ball Diameter

0.300

0.320

0.340

Ball Pitch Width

0.5

Ball Pitch Length

0.5

Ball to Edge Spacing Width

0.538

0.563

0.588

Ball to Edge Spacing Length

0.647

0.672

0.697

24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing

Top View (Sample Marking)

Bottom View (Bumped Side)

Side View

A2 A1

B2 B1

C2 C1

D2 D1

E2 E1

Side View

9409WRR

YWW I2.7

T #

X9409 Preliminary Information

Characteristics subject to change without notice.

21 of 21

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.6 1/30/03

www.xicor.com

Ordering Information

Device

Limits

Blank = 5V

±10%

2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

°C to +70°C

I = Industrial = 40

°C to +85°C

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B241 = 24-Lead CSP
Z24 = 24-Lead XBGA Contact Factory for Availability

Potentiometer Organization

Pot 0

Pot 1

Pot 2

Pot 3

W =

10K

10K 10K 10K

Y =

2.5K

2.5K 2.5K 2.5K

X9409

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9409WB241

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9409WB241