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X9460
Dual Audio Control Digitally Controlled Potentiometer (XDCP
TM
)
FEATURES
Dual audio control Two 32 taps Log pots
Zero Amplitude Wiper Switching
2-wire serial interface
4 cascadable slave byte addresses [A1,A0]
Total resistance: 33K
each XDCP (Typical)
Dual Voltage Operation
V+/V- = 2.7 to 5.5V
Temp Range = -40
o
C to +85
o
C
Package Options
14-Lead TSSOP
AUDIO PERFORMANCE
0 to - 62dB volume control
-92dB Mute
--Power up to mute position
SNR -96dB
THD+N: -95dB @1k HZ
Crosstalk rejection: -102dB @ 1k HZ
Channel-to-channel variation: 0.1dB
3dB-cutoff: 100kHz
DESCRIPTION
The X9460 integrates two digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit. The two XDCPs can be used as
stereo gain controls in audio applications. Read/Write
operations can directly access each channel
independently or both channels simultaneously.
Increment/ Decrement can adjust each channel
independently or both channels simultaneously.
The X9460 contains a zero amplitude wiper switching
circuit that delays wiper changes until the next zero
crossing of the audio signal.
The digitally controlled potentiometer is implemented
using 31 polysilicon resistors in a log array. Between
each of the resistors are tap points connected to the
wiper terminal through switches. The XDCPs are
designed to minimize wiper noise to avoid pops and
clicks during audio volume transitions. The position of
the wiper on the array is controlled by the user through
the 2-wire serial bus interface.
Power up reset the wiper to the mute position.
R
H-Right
R
L-Right
BUS
R
H-Left
R
L-Left
R
W-Left
R
W-Right
INTERF
A
CE
CONTROL &
REGISTER
POT
Left
POT
Right
V
SS
I
2
C
bus
V-
data
address
select
inc / dec
Power On
Recall
mute
V
CC
62dB total
Step Size
# of Steps
-1dB
11
-2dB
10
-3dB
5
-4dB
4
Mute
1
V+
PRELIMINARY
Low Noise, Low Cost, High End Features,
Dual Audio Log Potentiometer
SIMPLIFIED
FUNCTIONAL DIAGRAM
New Feature
Zero Amplitude
Wiper Switching
Typical Applications:
Set Top Boxes
DVD Players
Stereo Amplifiers
Portable Audio Products
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X9460
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R
H-Right
R
L-Right
WIPER
COUNTER
REGISTER
(WCR)
INTERFACE
AND
CONTROL
CIRCUITRY
SCL
A0
R
H-Left
R
L-Left
DATA
8
R
W-Left
R
W-Right
WIPER
COUNTER
REGISTER
(WCR)
SDA
A1
V-
V
SS
Power On
Recall
mute
POT Right
POT Left
V
CC
V+
Left Channel Control
Right Channel Control
Simultaneous Left and Right Channel
Control
Gain / Volume Control
Power up in Mute.
Audio
DAC
Audio
Amplifier
Left
Audio
Amplifier
Right
Controller
EEPROM
X9460
2 XDCP
Serial Bus
Audio => R
HL,
R
HR
R
WL
, R
WR
=> Amplifier
DETAILED FUNCTIONAL DIAGRAM
TYPICAL APPLICATION
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X9460
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PIN CONFIGURATION
PIN ASSIGNMENTS
Pin
(TSSOP)
Symbol
Function
1
SDA
Serial Data
2
SCL
Serial Clock
3
V
CC
System Supply Voltage
4
V+
Positive Analog Supply
5
V
SS
System Ground
6
A1
Device Address
7
A0
Device Address
8
R
W-left
Wiper terminal of the Left Potentiometer
9
R
L-left
Negative terminal of the Left Potentiometer
10
R
H-left
Positive terminal of the Left Potentiometer
11
R
W-right
Wiper terminal of the Right Potentiometer
12
R
L-right
Negative terminal of the Right Potentiometer
13
R
H-right
Positive terminal of the Right Potentiometer
14
V-
Negative Analog Supply
TSSOP
V
CC
R
H-left
SDA
V
SS
1
2
3
4
5
6
7
8
14
13
12
11
10
9
V+
A0
R
H-right
R
L-right
R
W-right
SCL
A1
V-
R
L-left
R
W-left
X9460
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X9460
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DETAILED PIN DESCRIPTION:
Host Interface Pins
S
ERIAL
C
LOCK
(SCL)
The SCL input clocks data into and out of the X9460.
S
ERIAL
D
ATA
(SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
D
EVICE
A
DDRESS
(A
1
- A
0
)
The Address inputs are used to set the least significant
2 bits of the 8-bit Slave Byte Address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9460. Up to 4 X9460s may be directly con-
nected to a single I2C serial bus. If left floating, these
pins are internally pulled to ground.
Slave Byte (bits, MSB-LSB) = 0101 0 A
1
A
0
R/W
Potentiometer Pins
R
H-
LEFT
, R
L-
LEFT
, R
H-
RIGHT
, R
L-
RIGHT
The R
H
and R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentio-
meter.
R
W-
LEFT
, R
W-
RIGHT
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Supply Pins
A
NALOG
S
UPPLY
V-
AND
V+
The positive power supply for the DCP analog control
section is connected to V+. The negative power supply
for the DCP analog control section is connected to V-.
Digital Supplies V
CC
, V
SS
The power supplies for the digital control sections.
Power Up and Down Recommendations
There are no restrictions on the power-up condition of
V
CC
, V+ and V- and the voltages applied to the potenti-
ometer pins provided that the Vcc and V+ are more
positive or equal to the voltage at RH, RL , and Rw, ie.
Vcc, V+ > RH, RL, Rw. At all times, the voltages on the
potentiometer pins must be less than V+ and more
than V-.
The following V
CC
ramp rate spec is always in effect.
0.2 V/ms < V
CC
ramp < 50 V/ms
The V
SS
pin is always connected to the system com-
mon or ground. V
H
, V
L
, V
W
are the voltages on the R
H
,
R
L
, and R
W
potentiometer pins.
X9460 PRINCIPLES OF OPERATION
The X9460 is a highly integrated microcircuit incorpo-
rating two resistor arrays with their associated regis-
ters, counters and the serial interface logic providing
direct communication between the host and the DCP
potentiometers. This section provides detailed descrip-
tion as following:
Resistor Array Description
Serial Interface Description
Command Set and Register Information Description
RESISTOR ARRAY DESCRIPTION
The X9460 is comprised of two resistor arrays. Each
array contains 31 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
inputs). Tables 1 and 2 pro-
vide a description of the step size and tap positions.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
five bits of the WCR are decoded to select, and enable,
one of thirty-two switches.
Table 1. Total -62dB range Plus Mute Position
Step Size
# of Steps
-1 dB
11 steps
- 2 dB
10 steps
- 3 dB
5 steps
- 4 dB
4 steps
Mute
1 step
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X9460
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Table 2. Wiper Tap Position vs dB.
SERIAL INTERFACE DESCRIPTION
Serial Interface
The X9460 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
The X9460 is a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop condi-
tions.
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9460 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identifica-
tion and slave address byte, and 2) again after each
successful receipt of the instruction or databyte. See
Figure 1.
Invalid Commands
For any invalid commands or unrecognizable
addresses, the X9460 will NOT acknowledge and
return the X9460 to the idle state.
Tap Position, n
dB
Min/Max dB
for n = 20 to 31
n - 31
-11 / 0
for n = 10 to 19
2n-51
-31 / -13
for n = 5 to 9
3n-61
-46 / -34
for n = 1 to 4
4n-66
-62 / -50
n = 0
-92
-92
Figure 1. Acknowledge Response from Receiver
SCL FROM
MASTER
DATA
OUTPUT
FROM
TRANSMITTER
1
8
9
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
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X9460
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COMMAND SET AND REGISTER DESCRIPTION
DEVICE ADDRESSING
Following a start condition the master must output the
Slave Byte Address of the slave it is accessing. The
most significant four bits of the slave address are the
device type identifier (refer to Figure 2 below). For the
X9460 this is fixed as 0101.
Figure 2. Slave Byte Address
The next three bits of the Slave Byte Address are the
device address. The device address is defined by the
A
1
A
0
inputs. The X9460 compares the serial data
stream with the Slave Byte Address; a successful com-
pare is required for the X9460 to respond with an
acknowledge. The A
1
A
0
inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
. The R/W
bit sets the device for read or write operations.
Command Set
After a Slave Byte Address match, the next byte sent
contains the Command and register pointer informa-
tion. The four most significant bits are the Command.
The next bit is a "X" (don't care) set to zero.
Figure 3. Command Byte Format
The Z
D
bit enables and disables the Zero Amplitude
Wiper Switching circuit. When Z
D
=1, the wiper
switches will turn on when close-to-zero amplitude is
detected across the potentiometer pins. When Z
D
=0,
this circuit is disabled. The last two bits, LT (left POT
enable) and RT (right POT enable), select which of the
two potentiometers is affected by the instruction.
Several instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9460. These instructions are: Read
Wiper Counter Register, Write Wiper Counter Register.
The sequence of operations is shown in Figure 4 and
5. The four-byte command is used for write command
for both right and left pots (Figure 6).
Special Commands
Increment / Decrement Instruction. The Increment/
Decrement command is different from the other com-
mands. Once the command is issued and the X9460
has responded with an acknowledge, the master can
clock the selected wiper up and/or down. For each
SCL clock pulse (t
HIGH
) while SDA is HIGH, the
selected wiper will move one resistor segment towards
the R
H
terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one
resistor segment towards the R
L
terminal. A detailed
illustration of the sequence and timing for this opera-
tion are shown in Figures 7 and 8 respectively.
Wiper Counter Register
The X9460 contains two Wiper Counter Registers. The
Wiper Counter Register output is decoded to select
one of thirty-two switches along its resistor array. The
Write Wiper Counter Register command directly sets
the WCR to a value. The Increment/Decrement
instruction steps the register value up or down one to
multiple times.
The WCR is a volatile register (Table 3) and is reset to
the mute position (tap 0, "zero") at power-up.
Table 3. Wiper Counter Registers, 5-bit - volatile:
The X9460 contains one 5-bit Wiper Counter Register
for each DCP. (Two 5-bit registers in total.)
1
0
0
0
A1
A0
R/W
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
I1
I2
I3
I0
0
Z
D
RT
LT
WIPER COUNTER
SELECT
INSTRUCTIONS
this bit not used, set to 0
WCR4
WCR3
WCR2
WCR1
WCR0
(MSB)
(LSB)
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X9460
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Table 2a. Command Set
Notes: "1/0" = data is one or zero
Figure 4. Three-Byte Command Sequence (Read)
Figure 5. Three-Byte Command Sequence (Write)
Instruction
Instruction Set
Operation
I
3
I
2
I
1
I
0
X
Z
D
RT LT
Read Wiper
LSB of Slave Byte=1, no command required
Slave will return Left then Right Data
Write Left Wiper
Counter
1
0
1
0
0
1/0
0
1
Write new value to the Wiper Counter Register
Write Right Wiper
Counter
1
0
1
0
0
1/0
1
0
Write new value to the Wiper Counter Register
Write Both Wiper
Counters
1
0
1
0
0
1/0
1
1
Write new value to the Wiper Counter Register
Inc/Dec Left Wiper
Counter
0
0
1
0
0
1/0
0
1
Enable Increment/decrement of the Control Latch
Inc/Dec Right Wiper
Counter
0
0
1
0
0
1/0
1
0
Enable Increment/decrement of the Control Latch
Inc/Dec Both Wiper
Counters
0
0
1
0
0
1/0
1
1
Enable Increment/decrement of the Control Latch
S
T
A
R
T
0
1
0
1
0
A1 A0 R/W A
C
K
0
0
0
SCL
SDA
S
T
O
P
A
C
K
0
0
0
LEFT POT
DATA BYTE
RIGHT POT
DATA BYTE
DEVICE TYPE
IDENTIFIER
1
0
0
0
0
0
0
A
C
K
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
0
1
0
1
0
A1 A0
R/W A
C
K
I3
I2
I1 I0
0
ZD RT LT
A
C
K
SCL
SDA
S
T
O
P
A
C
K
0
0
0
INSTRUCTION BYTE
RIGHT or LEFT POT
DATA BYTE
DEVICE TYPE
IDENTIFIER
0
1
0
1
0
0
0
0
0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
PRELIMINARY
X9460
Characteristics subject to change without notice.
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Figure 6. Four-Byte Command Sequence (Write)
Figure 7. Increment/Decrement Command Sequence (Write)
Figure 8. Increment/Decrement Timing Limits
S
T
A
R
T
0 1
0
1 0
A1 A0 R/W A
C
K
I3 I2
I1 I0 0 ZD RT LT A
C
K
SCL
SDA
INSTRUCTION BYTE
DEVICE TYPE
IDENTIFIER
0 0
0
A
C
K
S
T
O
P
A
C
K
0 0 0
LEFT POT
DATA BYTE
RIGHT POT
DATA BYTE
0
1
0
1
0
0
1
1
0 0
0
0 0 0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
T
A
R
T
0
1
0
1
0
A1 A0 R/W A
C
K
I3
I2
I1
I0
ZD
RT LT
A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
DEVICE TYPE
IDENTIFIER
INSTRUCTION BYTE
INC and DEC active
0
0
0
0
1
0
SCL
SDA
RW
INC/DEC
CMD
ISSUED
VOLTAGE OUT
t WRID
Wiper can move within 10secs after the falling edge of SCL
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X9460
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INSTRUCTION FORMATS
Read Wiper Counter Register
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
Left wiper position
(sent by slave on SDA)
M
A
C
K
Right wiper position
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0
1
0
1
0
A
1
A
0
R / W
= 1
0
0
0
L
D
4
L
D
3
L
D
2
L
D
1
L
D
0
0
0
0
R
D
4
R
D
3
R
D
2
R
D
1
R
D
0
Write Wiper Counter Register
Write Both Wiper Counter Registers
Increment/Decrement Wiper Counter Register
Definitions:
(1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.
(2) "A1 ~ A0": stands for the device addresses sent by the master.
(3) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(4) "D": stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
wiper
addresses
S
A
C
K
Left or Right wiper
position
(sent by master on SDA)
S
A
C
K
S
T
O
P
0
1
0
1
0
A
1
A
0
R / W
= 0
1
0
1
0
0
Z
D
R
T
L
T
0
0
0
D
4
D
3
D
2
D
1
D
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
wiper
addresses S
A
C
K
Left wiper position
(sent by master on
SDA)
S
A
C
K
Right wiper position
(sent by master on
SDA)
S
A
C
K
S
T
O
P
0 1 0 1 0
A
1
A
0
R / W
= 0
1 0 1 0 0
Z
D
1 1
0 0 0
L
D
4
L
D
3
L
D
2
L
D
1
L
D
0
0 0 0
R
D
4
R
D
3
R
D
2
R
D
1
R
D
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
wiper
addresses
S
A
C
K
increment/decrement
(sent by master on SDA)
S
T
O
P
0
1
0
1
0
A1 A0
R / W
= 0
0
0
1
0
0 ZD RT LT
I/D
I/D
.
.
.
.
I/D I/D
PRELIMINARY
X9460
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ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................... -65
C to +135C
Storage Temperature.........................65
C to +150C
Voltage on SDA, SCL or any Address Input
with Respect to V
SS
................................1V to +6V
Voltage on V+ (referenced to V
SS
)......................... +6V
Voltage on V- (referenced to V
SS
)........................... -6V
(V+) (V-).............................................................. 12V
Any R
H
.................................................................... V+
Any R
L
...................................................................... V-
Lead Temperature (Soldering, 10 seconds) ...... 300
C
I
W
max (10 secs) ............................................... 3mA
*Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only and the functional
operation of the device at these or any other conditions
above those listed in the operational sections of this
specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
(1)
Notes: (1) V
CC
= | V- |
V
CC
Ramp up timing 0.2 V/ms < Vcc Ramp Rate < 50 V/ms
(2) This parameter is guaranteed by design and characterization
(3) T
A
= 25
o
C, V
CC
= 5.0V; 20 Hz to 20kHz Measurement Bandwidth with 80kHZ filter, input signal 1Vrms, 1kHz Sine Wave.
Temp
Min.
Max.
Industrial
40
C
+85
C
Device
Supply Voltage (V
CC
)
V- Limits
V+ Limits
X9460V142.7
2.7V to 5.5V
-5.5V to -2.7V
+2.7V to +5.5V
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
Dynamic Performance
(2)(3)
Control Range
-62
0
dB
Mute Mode
-92
dB
@1V rms
SNR
Signal Noise Ratios (Unweighted)
-96
dB
@1V rms @ 1kHz, Tap = -6dB
THD + N
Total Harmonic Distortion + Noise
-95
dB
@1V rms @ 1kHz, Tap = -6dB
XTalk
DCP Isolation
-102
dB
@1kHz, tap = -6dB
Digital Feedthrough
(Peak Component)
-105
dB
tap = -6dB
-3db Cutoff Frequency
100
kHz
DC Accuracy
Step Size
-1
-4
dB
Steps of -1, -2, -3, -4 dB
Step Size Error
-0.2
+0.2
dB
For -1dB steps
Step Size Error
-0.4
+0.4
dB
For -2dB steps
Step Size Error
-0.6
+0.6
dB
For -3dB steps
Step Size Error
-0.8
+0.8
dB
For -4dB steps
DCP to DCP Matching
-0.1
0.1
dB
PRELIMINARY
X9460
Characteristics subject to change without notice.
11 of 17
REV 4.0.13 6/25/02
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ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)
(1)
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
(1)
CAPACITANCE
Notes: (4) This parameter is not 100% tested.
ANALOG INPUTS
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
V
TERM
Voltage on R
L
, R
W
, and R
H
pins
V-
V+
V
R
TOTAL
End to End Resistance
-20
+20
%
Typical 33K
Cin
(4)
Input Capacitance R
L
, R
H
, R
W
25
pF
T
A
= 25
o
C
I
W
(2)
Wiper Current
-3
+3
mA
R
W
Wiper Resistance
100
200
Wiper Current = 3mA
V-
Voltage on V- pin
-5.5
-2.7
V
V+
Voltage on V+ pin
+2.7
+5.5
V
Noise
2
Vrms
20 HZ to 20KHZ, Grounded Input
@ -6dB tap
TC
R
(2)
Temperature Coefficient of re-
sistance
-300
PPM/C
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Units
I
CC1
V
CC
Supply Current (Move
Wiper, Write, Read)
200
300
A
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
I
SB
V
CC
Current (Standby)
3
A
SCL = SDA = V
CC
, Addr. = V
SS
I
LI
Input Leakage Current
1
10
A
V
IN
= V
SS
to V
CC
Iai
Analog Input Leakage
0.1
A
V
IN
= V- to V+ with all other
analog inputs floating
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
V
IH
Input HIGH Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
0.5
V
CC
x 0.1
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 3mA
Symbol
Test
Max.
Units
Test Conditions
C
I/O
(4)
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(4)
Input Capacitance (A0, A1, A2 and SCL)
6
pF
V
IN
= 0V
PRELIMINARY
X9460
Characteristics subject to change without notice.
12 of 17
REV 4.0.13 6/25/02
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A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING (Over recommended operating conditions)
DCP TIMING
(2)
I
nput Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing Level
V
CC
x 0.5
5V
1533
100pF
SDA OUTPUT
Symbol
Parameter
Min.
Max.
Units
f
SCL
Clock Frequency
400
kHz
t
CYC
Clock Cycle Time
2500
ns
t
HIGH
Clock High Time
600
ns
t
LOW
Clock Low Time
1300
ns
t
SU:STA
Start Setup Time
600
ns
t
HD:STA
Start Hold Time
600
ns
t
SU:STO
Stop Setup Time
600
ns
t
SU:DAT
SDA Data Input Setup Time
500
ns
t
HD:DAT
SDA Data Input Hold Time
50
ns
t
R
(2)
SCL and SDA Rise Time
300
ns
t
F
(2)
SCL and SDA Fall Time
300
ns
t
AA
(2)
SCL Low to SDA Data Output Valid Time
900
ns
t
DH
(2)
SDA Data Output Hold Time
50
ns
T
I
(2)
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
t
BUF
(2)
Bus Free Time (Prior to Any Transmission)
1300
ns
t
SU:WPA
A0, A1
(2)
0
ns
t
HD:WPA
A0, A1
(2)
0
ns
Symbol
Parameter
Min.
Max.
Units
t
WRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
10
s
t
WRL
Wiper Response Time After Instruction Issued (All Load Instructions)
10
s
t
WRID
Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction)
10
s
PRELIMINARY
X9460
Characteristics subject to change without notice.
13 of 17
REV 4.0.13 6/25/02
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TIMING DIAGRAMS
Figure 9. START and STOP Timing
Figure 10. Input Timing
Figure 11. Output Timing
Figure 12. DCP Timing (for All Load Instructions)
t
SU:STA
t
HD:STA
t
SU:STO
SCL
SDA
t
R
(START)
(STOP)
t
F
t
R
t
F
SCL
SDA
t
HIGH
t
LOW
t
CYC
t
HD:DAT
t
SU:DAT
t
BUF
SCL
SDA
t
DH
t
AA
SCL
SDA
VWx
(STOP)
LSB
t
WRL
PRELIMINARY
X9460
Characteristics subject to change without notice.
14 of 17
REV 4.0.13 6/25/02
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TYPICAL PERFORMANCE CHARACTERISTICS
(V
CC
,V+ = 5.0V,V- = -5.0V, T
A
= + 25 C, unless otherwise noted)
Figure 14. THD + N
Figure 13. Single Tone Frequency Response
FFT Spectrum
-1 8 0
+0
-1 7 0
-1 6 0
-1 5 0
-1 4 0
-1 3 0
-1 2 0
-1 1 0
-1 0 0
-9 0
-8 0
-7 0
-6 0
-5 0
-4 0
-3 0
-2 0
-1 0
d
B
V
H z
(with 1kHz 1Vrms input, tap = -6dB)
20
20k
50
100
200
500
1k
2k
5k
10k
(with 80kHz low-pass filter, tap = -6dB)
THD+N vs Frequency
- 1 2 0
- 6 0
- 1 1 5
- 1 1 0
- 1 0 5
- 1 0 0
- 9 5
- 9 0
- 8 5
- 8 0
- 7 5
- 7 0
- 6 5
d
B
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
PRELIMINARY
X9460
Characteristics subject to change without notice.
15 of 17
REV 4.0.13 6/25/02
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TYPICAL PERFORMANCE CHARACTERISTICS
(V
CC
,V+ = 5.0V,V- = -5.0V, T
A
= + 25 C, unless otherwise noted)
Figure 15. Mute
Mut e Mod e
-140
+0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
V
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
PRELIMINARY
X9460
Characteristics subject to change without notice.
16 of 17
REV 4.0.13 6/25/02
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PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
PRELIMINARY
X9460
Characteristics subject to change without notice.
17 of 17
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
REV 4.0.13 6/25/02
www.xicor.com
ORDERING INFORMATION
X9460 TSSOP 14L Top Mark Instructions
Commercial
Industrial
5.0 volt
X9460KV
EYWW
X9460KV
EYWW I
2.7 volt
X9460KV
EYWW F
X9460KV
EYWW G
Device
V
CC
Limits
Blank = 5V 10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0
C to +70C
I= Industrial = 40
C to +85C
Package
V14 = 14-Lead TSSOP
Potentiometer Organization
Left Pot
Right Pot
K =
33K
20%
33K
20%
X9460
P
T
V
K
PDF 
ZIP