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Data Sheet, v3.0.106
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. All other
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NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
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Introduction
With the Xilinx LogiCORETM PCI Interface, a designer can
build a customized, fully PCI 2.3-compliant core with the
highest possible sustained performance, 528 Mbytes/sec.
Features
Fully PCI 2.3-compliant core, 32-bit, 66/33 MHz
interface
Customizable, programmable, single-chip solution
Predefined implementation for predictable timing
Incorporates Xilinx Smart-IPTM technology
3.3V operation at 0-66 MHz
5.0V operation at 0-33 MHz
Fully verified design tested with Xilinx proprietary
testbench and hardware
Available for configuration and download on the web:
-
Web-based configuration and download tool
-
Web-based user constraint file generator tool
CardBus compliant
Supported initiator functions:
-
Configuration read, configuration write
-
Memory read, memory write, MRM, MRL
-
Interrupt acknowledge, special cycles
-
I/O read, I/O write
Supported target functions:
-
Type 0 configuration space header
-
Up to three base address registers (MEM or I/O
with adjustable block size from 16 bytes to 2
Gbytes)
-
Medium decode speed
-
Parity generation, parity error detection
-
Configuration read, configuration write
-
Memory read, memory write, MRM, MRL
-
Interrupt acknowledge
-
I/O read, I/O write
-
Target abort, target retry, target disconnect
0
LogiCORE PCI32 Interface v3.0
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Data Sheet, v3.0.106
LogiCORE Facts
PCI32 Resource Utilization
(1)
Slice Four Input LUTs
553
Slice Flip-Flops
566
IOB Flip-Flops
97
IOBs
50
TBUFs
288
GCLKs
1
(2)
Provided with Core
Documentation
PCI Design Guide
PCI Implementation Guide
Design File Formats
Verilog/VHDL Simulation Model
NGO Netlist
Constraint Files
User Constraint Files (UCF)
Guide Files (NCD)
Example Design
Verilog/VHDL Example Design
Design Tool Requirements
Xilinx Tools
v5.2i
Service Pack 2
Tested Entry and
Verification Tools
(3)
Synplicity Synplify
Synopsys FPGA Express
Exemplar Leonardo Spectrum
Xilinx XST
(4)
Cadence Verilog XL
Model Technology ModelSim
LogiCORE PCI32 Interface v3.0
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Data Sheet, v3.0.106
Applications
Embedded applications in networking, industrial,
and telecommunication systems
PCI add-in boards such as frame buffers, network
adapters, and data acquisition boards
Hot swap CompactPCI boards
CardBus compliant
Any applications that need a PCI interface
General Description
The LogiCORE PCI Interface is a preimplemented and fully
tested module for Xilinx FPGAs. The pinout for each device
and the relative placement of the internal logic are pre-
defined. Critical paths are controlled by constraint and guide
files to ensure predictable timing. This significantly reduces
the engineering time required to implement the PCI portion
of your design. Resources can instead be focused on your
unique user application logic in the FPGA and on the sys-
tem-level design. As a result, LogiCORE PCI products min-
imize your product development time.
The core meets the setup, hold, and clock-to-timing require-
ments as specified in the PCI-X specification. The interface
is verified through extensive simulation.
Other features that enable efficient implementation of a PCI
system include:
Block SelectRAMTM memory. Blocks of on-chip
ultra-fast RAM with synchronous write and dual-port
RAM capabilities. Used in PCI designs to implement
FIFOs.
SelectRAM memory. Distributed on-chip ultra-fast RAM
with synchronous write option and dual-port RAM
capabilities. Used in PCI designs to implement FIFOs.
Internal three-state bus capability for data multiplexing.
The interface is carefully optimized for best possible perfor-
mance and utilization in Xilinx FPGA devices.
Smart-IP Technology
Drawing on the architectural advantages of Xilinx FPGAs,
Xilinx Smart-IP technology ensures the highest perfor-
mance, predictability, repeatability, and flexibility in PCI
designs. The Smart-IP technology is incorporated in every
LogiCORE PCI interface.
Xilinx Smart-IP technology leverages the Xilinx architectural
advantages, such as look-up tables and segmented routing,
as well as floorplanning information, such as logic mapping
and location constraints. This technology provides the best
physical layout, predictability, and performance. In addition,
these features allow for significantly reduced compile times
over competing architectures.
To guarantee the critical setup, hold, minimum clock-to-out,
and maximum clock-to-out timing, the PCI interface is deliv-
Supported Devices
PCI32/66
Virtex V200FG256-6C
Virtex-E V200EFG256-6C
Virtex-E V400EFG676-6C
3.3V only
3.3V only
3.3V only
PCI32/33
Virtex V300BG432-5C
Virtex V1000FG680-5C
Virtex-E V100EBG352-6C
Virtex-E V300EBG432-6C
Virtex-E V1000EFG680-6C
Virtex-II 2V1000FG456-4C/I/M
Virtex-II ProTM 2VP7FF672-5C
Spartan-II 2S30PQ208-5C
Spartan-II 2S50PQ208-5C
Spartan-II 2S100PQ208-5C
Spartan-II 2S150PQ208-5C
Spartan-II 2S200PQ208-5C
Spartan-IIE 2S50EPQ208-6C
3.3V, 5.0V
3.3V, 5.0V
3.3V only
3.3V only
3.3V only
3.3V only
3.3V only
3.3V, 5.0V
3.3V, 5.0V
3.3V, 5.0V
3.3V, 5.0V
3.3V, 5.0V
3.3V only
Spartan-IIE 2S100EPQ208-6C
Spartan-IIE 2S150EPQ208-6C
Spartan-IIE 2S200EPQ208-6C
Spartan-IIE 2S300EPQ208-6C
Spartan-3 3S1000FG456-4C
3.3V only
3.3V only
3.3V only
3.3V only
3.3V only
Xilinx provides technical support for this LogiCORE product when used
as described in the Design Guide and the Implementation Guide. Xilinx
cannot guarantee timing, functionality, or support of product if
implemented in devices not listed, or if customized beyond that allowed
in the product documentation.
Notes:
1.
The resource utilization depends on configuration of the interface
and the user design. Unused resources are trimmed by the Xilinx
technology mapper. The utilization figures reported in this table are
representative of a maximum configuration.
2.
Designs running at 66 MHz in devices other than VirtexTM-II require
one GCLKIOB and two GCLKs.
3.
See the implementation guide or product release notes for current
supported versions.
4.
XST is command line option only. See Implementation Guide for
details.
5.
Universal card implementations require two bitstreams.
6.
Virtex-E and Spartan-IIE recommended for CardBus.
7.
Commercial devices; 0
o
C < T
j
< 85
o
C.
8.
For additional Part/Package combinations, see the UCF Generator
in the PCI Lounge.
9.
XC2V1000 is supported over Military Temp. range.
LogiCORE PCI32 Interface v3.0
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Data Sheet, v3.0.106
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ered with Smart-IP constraint files that are unique for a
device and package combination. These constraint files
guide the implementation tools so that the critical paths
always are within specification.
Xilinx provides Smart-IP constraint files for many device
and package combinations. Constraint files for unsupported
device and package combinations may be generated using
the web-based constraint file generator.
Functional Description
The LogiCORE PCI Interface is partitioned into five major
blocks and a user application as shown in
Figure 1
.
PCI I/O Interface Block
The I/O interface block handles the physical connection to
the PCI bus including all signaling, input and output syn-
chronization, output three-state controls, and all
request-grant handshaking for bus mastering.
User Application
The LogiCORE PCI Interface provides a simple, gen-
eral-purpose interface for a wide range of applications.
PCI Configuration Space
This block provides the first 64 bytes of Type 0, version 2.3
Configuration Space Header, as shown in
Table 1
, to sup-
port software-driven "Plug-and-Play" initialization and con-
figuration. This includes information for Command, Status,
and three Base Address Registers (BARs).
The capability for extending configuration space has been
built into the user application interface. This capability,
including the ability to implement a capabilities pointer in
configuration space, allows the user to implement functions
such as power management and message signaled inter-
rupts in the user application.
Parity Generator/Checker
This block generates and checks even parity across the AD
bus, the CBE# lines, and the parity signals. It also reports
data parity errors via PERR# and address parity errors via
SERR#.
Initiator State Machine
This block controls the PCI interface initiator functions. The
states implemented are a subset of those defined in Appen-
dix B of the PCI Local Bus Specification. The initiator control
logic uses one-hot encoding for maximum performance.
Target State Machine
This block controls the PCI interface target functions. The
states implemented are a subset of those defined in Appen-
dix B of the PCI Local Bus Specification. The target control
logic uses one-hot encoding for maximum performance.
Interface Configuration
The LogiCORE PCI Interface can easily be configured to fit
unique system requirements by using the Xilinx Web-based
Configuration and Download tool or by changing the HDL
configuration file. The following customization options,
among many others, are supported by the interface and are
described in the product design guide.
Base Address Registers (number, size, and type)
Configuration Space Header ROM
Figure 1: LogiCORE PCI Interface Block Diagram
Parity
Generator/
Checker
P C I C o n f i g u r a t i o n S p a c e
Initiator
State
Machine
Interrupt
Pin and
Line
Register
Latency
Timer
Register
Vendor ID,
Rev ID,
Other User
Data
Target
State
Machine
PCI I/O INTERF
A
C
E
USER APPLICA
TION
A D I O [ 6 3 : 0 ]
A D [ 6 3 : 0 ]
PAR
GNT-
PERR-
SERR-
FRAME-
IRDY-
REQ-
TRDY-
DEVSEL-
STOP-
Base
Address
Register
0
Base
Address
Register
1
Command/
Status
Register
Base
Address
Register
2
REQ64-
ACK64-
PAR64
Table 1: PCI Configuration Space Header
31
16 15
0
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Rev ID
08h
BIST
Header
Type
Latency
Timer
Cache Line
Size
0Ch
Base Address Register 0 (BAR0)
10h
Base Address Register 1 (BAR1)
14h
Base Address Register 2 (BAR2)
18h
Base Address Register 3 (BAR3)
1Ch
Base Address Register 4 (BAR5)
20h
Base Address Register 5 (BAR5)
24h
Cardbus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
2Ch
Expansion ROM Base Address
30h
Reserved
CapPtr
34h
Reserved
38h
Max Lat
Min Gnt
Int Pin
Int Line
3Ch
Reserved
40h-FFh
Notes:
1.
Shaded areas are not implemented and return zero.
LogiCORE PCI32 Interface v3.0
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Data Sheet, v3.0.106
Burst Transfer
The PCI bus derives its performance from its ability to sup-
port burst transfers. The performance of any PCI applica-
tion depends largely on the size of the burst transfer. Buffers
to support PCI burst transfer can efficiently be implemented
using on-chip RAM resources.
Supported PCI Commands
Table 2
illustrates the PCI bus commands supported by the
LogiCORE PCI Interface.
Bandwidth
The LogiCORE PCI Interface supports fully compliant zero
wait-state burst operations for both sourcing and receiving
data. This interface supports a sustained bandwidth of up to
528 MBytes/sec. The design can be configured to take
advantage of the ability of the LogiCORE PCI Interface to
do very long bursts.
The flexible user application interface, combined with sup-
port for many different PCI features, gives users a solution
that lends itself to use in many high-performance applica-
tions. The user is not locked into one DMA engine; hence,
an optimized design that fits a specific application can be
designed.
Recommended Design Experience
The LogiCORE PCI Interface is preimplemented, allowing
engineering focus on the unique user application functions
of a PCI design. Regardless, PCI is a high-performance
design that is challenging to implement in any technology.
Therefore, previous experience with building high-perfor-
mance, pipelined FPGA designs using Xilinx implementa-
tion software, constraint files, and guide files is
recommended. The challenge to implement a complete PCI
design including user application functions varies depend-
ing on configuration and functionality of your application.
Contact your local Xilinx representative for a closer review
and estimation for your specific requirements.
Timing Specifications
The maximum speed at which your user design is capable
of running can be affected by the size and quality of the
design. The following tables show the key timing parame-
ters for the LogiCORE PCI Interface.
Table 3
lists the Timing Parameters in the 66MHz Imple-
mentations and
Table 4
lists Timing Parameters in the
33MHz Implementations.
Table 2: PCI Bus Commands
CBE [3:0]
Command
PCI
Initiator
PCI
Target
0000
Interrupt Acknowledge
Yes
Yes
0001
Special Cycle
Yes
Ignore
0010
I/O Read
Yes
Yes
0011
I/O Write
Yes
Yes
0100
Reserved
Ignore
Ignore
0101
Reserved
Ignore
Ignore
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved
Ignore
Ignore
1001
Reserved
Ignore
Ignore
1010
Configuration Read
Yes
Yes
1011
Configuration Write
Yes
Yes
1100
Memory Read Multiple
Yes
Yes
1101
Dual Address Cycle
No
Ignore
1110
Memory Read Line
Yes
Yes
1111
Memory Write Invalidate
No
Yes
LogiCORE PCI32 Interface v3.0
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Data Sheet, v3.0.106
1-800-255-7778
Ordering Information
This core may be downloaded from the Xilinx
IP Center
for
use with the Xilinx CORE Generator System v4.1 and later.
The Xilinx CORE Generator System tool is bundled with all
Alliance and Foundation Series Software packages, at no
additional charge.
To order the Xilinx PCI Core, please visit the
Xilinx Silicon
Xpresso Cafe
or contact your local Xilinx
sales representa-
tive
.
Part Numbers
DO-DI-PCI32-IP
-Access to the V3.0 PCI32 33 MHz Spartan and 66 MHz
Virtex Families
DX-DI-PCI32-SL
-Upgrade from PCI32 33 MHz Spartan only to V3.0
PCI32 33 MHz Spartan and 66 MHz Virtex Families
DO-DI-PCI32-SP
-Access to the V3.0 PCI32 Spartan Family
Table 3: Timing Parameters, 66MHz Implementations
Symbol
Parameter
Min
Max
T
cyc
CLK Cycle Time
15
1
30
T
high
CLK High Time
6
-
T
low
CLK Low Time
6
-
T
val
CLK to Signal Valid Delay
(bussed signals)
2
2
6
2
T
val
CLK to Signal Valid Delay
(point to point signals)
2
2
6
2
T
on
Float to Active Delay
2
2
-
T
off
Active to Float Delay
-
14
1
T
su
Input Setup Time to CLK
(bussed signals)
3
2,3
-
T
su
Input Setup Time to CLK
(point to point signals)
5
2,3
-
T
h
Input Hold Time from CLK
0
2,3
-
T
rstoff
Reset Active to Output Float
-
40
Notes:
1.
Controlled by timespec constraints, included in product.
2.
Controlled by SelectIO configured for PCI66_3.
3.
Controlled by guide file, included in product.
Table 4: Timing Parameters, 33MHz Implementations
Symbol
Parameter
Min
Max
T
cyc
CLK Cycle Time
30
1
-
T
high
CLK High Time
11
-
T
low
CLK Low Time
11
-
T
val
CLK to Signal Valid Delay
(bussed signals)
2
2
11
2
T
val
CLK to Signal Valid Delay
(point to point signals)
2
2
11
2
T
on
Float to Active Delay
2
2
-
T
off
Active to Float Delay
-
28
1
T
su
Input Setup Time to CLK
(bussed signals)
7
2
-
T
su
Input Setup Time to CLK
(point to point signals)
10
2
-
T
h
Input Hold Time from CLK
0
2
-
T
rstoff
Reset Active to Output Float
-
40
Notes:
1.
Controlled by timespec constraints, included in product.
2.
Controlled by SelectIO configured for PCI33_3 or PCI33_5.
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