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Virtex’II Platform FPGAs: Complete Data Sheet

DS031 October 14, 2003

www.xilinx.com

Product Specification

1-800-255-7778

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

This document includes all four modules of the Virtex-II Platform FPGA data sheet.

Module 1:
Introduction and Overview

DS031-1 (v2.0) August 1, 2003
7 pages

Summary of Features

General Description

Device/Package Combinations and Maximum I/O

Ordering Information

Module 2:
Functional Description

DS031-2 (v3.1) October 14, 2003
40 pages

Detailed Description

Digitally Controlled Impedance (DCI)

Configurable Logic Blocks (CLBs)

Sum of Products

3-State Buffers

18-Kb Block SelectRAMTM Resources

18-Bit x 18-Bit Multipliers

Global Clock Multiplexer Buffers

Digital Clock Manager (DCM)

Active Interconnect Technology

Creating a Design

Configuration

Module 3:
DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003
38 pages

Electrical Characteristics

Performance Characteristics

Switching Characteristics

Pin-to-Pin Output Parameter Guidelines

Pin-to-Pin Input Parameter Guidelines

DCM Timing Parameters

Module 4:
Pinout Information

DS031-4 (v2.0) August 1, 2003
225 pages

Pin Definitions

Pinout Tables
-

CS144 Chip-Scale BGA Package

FG256 Fine-Pitch BGA Package

FG456 Fine-Pitch BGA Package

FG676 Fine-Pitch BGA Package

BG575 Standard BGA Package

BG728 Standard BGA Package

FF896 Flip-Chip Fine-Pitch BGA Package

FF1152 Flip-Chip Fine-Pitch BGA Package

FF1517 Flip-Chip Fine-Pitch BGA Package

BF957Flip-Chip BGA Package

IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy
navigation in this volume.

VirtexTM-II Platform FPGAs:
Complete Data Sheet

DS031 October 14, 2003

Product Specification

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS031-1 (v2.0) August 1, 2003

www.xilinx.com

Module 1 of 4

Product Specification

1-800-255-7778

Summary of Virtex-II Features

Industry First Platform FPGA Solution

IP-Immersion Architecture

Densities from 40K to 8M system gates

420 MHz internal clock speed (Advance Data)

840+ Mb/s I/O (Advance Data)

SelectRAMTM Memory Hierarchy

3 Mb of dual-port RAM in 18 Kbit block SelectRAM
resources

Up to 1.5 Mb of distributed SelectRAM resources

High-Performance Interfaces to External Memory

DRAM interfaces
·

SDR / DDR SDRAM

Network FCRAM

Reduced Latency DRAM

SRAM interfaces
·

SDR / DDR SRAM

QDRTM SRAM

CAM interfaces

Arithmetic Functions

Dedicated 18-bit x 18-bit multiplier blocks

Fast look-ahead carry logic chains

Flexible Logic Resources

Up to 93,184 internal registers / latches with Clock
Enable

Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers

Wide multiplexers and wide-input function support

Horizontal cascade chain and sum-of-products
support

Internal 3-state bussing

High-Performance Clock Management Circuitry

Up to 12 DCM (Digital Clock Manager) modules
·

Precise clock de-skew

Flexible frequency synthesis

High-resolution phase shifting

16 global clock multiplexer buffers

Active Interconnect Technology

Fourth generation segmented routing structure

Predictable, fast routing delay, independent of fanout

SelectIOTM-Ultra Technology

Up to 1,108 user I/Os

19 single-ended and six differential standards

Programmable sink current (2 mA to 24 mA) per I/O

Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards

PCI-X compatible (133 MHz and 66 MHz) at 3.3V

PCI compliant (66 MHz and 33 MHz) at 3.3V

CardBus compliant (33 MHz) at 3.3V

Differential Signaling
·

840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers

Bus LVDS I/O

Lightning Data Transport (LDT) I/O with current
driver buffers

Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O

Built-in DDR input and output registers

Proprietary high-performance SelectLink
Technology
·

High-bandwidth data path

Double Data Rate (DDR) link

Web-based HDL generation methodology

Supported by Xilinx FoundationTM and Alliance
SeriesTM Development Systems

Integrated VHDL and Verilog design flows

Compilation of 10M system gates designs

Internet Team Design (ITD) tool

SRAM-Based In-System Configuration

Fast SelectMAP configuration

Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)

IEEE 1532 support

Partial reconfiguration

Unlimited reprogrammability

Readback capability

0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors

1.5V (V

CCINT

) Core Power Supply, Dedicated 3.3V

CCAUX

Auxiliary and V

CCO

I/O Power Supplies

IEEE 1149.1 Compatible Boundary-Scan Logic
Support

Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Three Standard Fine Pitches (0.80 mm,
1.00 mm, and 1.27 mm)

100% Factory Tested

VirtexTM-II Platform FPGAs:
Introduction and Overview

DS031-1 (v2.0) August 1, 2003

Product Specification

VirtexTM-II Platform FPGAs: Introduction and Overview

DS031-1 (v2.0) August 1, 2003

www.xilinx.com

Module 1 of 4

Product Specification

1-800-255-7778

General Description

The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in

Table 1

, the Virtex-II family comprises 11 members, ranging

from 40K to 8M system gates.

Packaging

Offerings include ball grid array (BGA) packages with
0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-
ditional wire-bond interconnects, flip-chip interconnect is
used in some of the BGA offerings. The use of flip-chip
interconnect offers more I/Os than is possible in wire-bond
versions of the similar packages. Flip-chip construction
offers the combination of high pin count with high thermal
capacity.

Table 2

shows the maximum number of user I/Os available.

The Virtex-II device/package combination table (

Table 6

the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.

Table 1: Virtex-II Field-Programmable Gate Array Family Members

Device

System

Gates

CLB

(1 CLB = 4 slices = Max 128 bits)

Multiplier

Blocks

SelectRAM Blocks

DCMs

Max I/O

Pads

(1)

Array

Row x Col.

Slices

Maximum

Distributed

RAM Kbits

18 Kbit

Blocks

Max RAM

(Kbits)

XC2V40

40K

8 x 8

256

XC2V80

80K

16 x 8

512

144

120

XC2V250

250K

24 x 16

1,536

432

200

XC2V500

500K

32 x 24

3,072

576

264

XC2V1000

40 x 32

5,120

160

720

432

XC2V1500

1.5M

48 x 40

7,680

240

864

528

XC2V2000

56 x 48

10,752

336

1,008

624

XC2V3000

64 x 56

14,336

448

1,728

720

XC2V4000

80 x 72

23,040

720

120

2,160

912

XC2V6000

96 x 88

33,792

1,056

144

2,592

1,104

XC2V8000

112 x 104

46,592

1,456

168

3,024

1,108

Notes:
1.

See details in

Table 2, "Maximum Number of User I/O Pads"

Table 2: Maximum Number of User I/O Pads

Device

Wire-Bond

Flip-Chip

XC2V40

XC2V80

120

XC2V250

200

XC2V500

264

XC2V1000

328

432

XC2V1500

392

528

XC2V2000

624

XC2V3000

516

720

XC2V4000

912

XC2V6000

1,104

XC2V8000

1,108

VirtexTM-II Platform FPGAs: Introduction and Overview

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Module 1 of 4

Product Specification

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Architecture

Virtex-II Array Overview

Virtex-II devices are user-programmable gate arrays with
various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic
designs. As shown in

Figure 1

, the programmable device is

comprised of input/output blocks (IOBs) and internal
configurable logic blocks (CLBs).

Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.

The internal configurable logic includes four major elements
organized in a regular array.

Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.

Block SelectRAM memory modules provide large
18 Kbit storage elements of dual-port RAM.

Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.

DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse- and fine-grained clock phase
shifting.

A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.

All programmable elements, including the routing
resources, are controlled by values stored in static memory

cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.

Virtex-II Features

This section briefly describes Virtex-II features.

Input/Output Blocks (IOBs)

IOBs are programmable and can be categorized as follows:

Input block with an optional single-data-rate or
double-data-rate (DDR) register

Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register

Bidirectional block (any combination of input and output
configurations)

These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.

IOBs support the following single-ended I/O standards:

LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)

PCI-X compatible (133 MHz and 66 MHz) at 3.3V

PCI compliant (66 MHz and 33 MHz) at 3.3V

CardBus compliant (33 MHz) at 3.3V

Figure 1: Virtex-II Architecture Overview

Global Clock Mux

DCM

IOB

CLB

Programmable I/Os

Block SelectRAM

Multiplier

Configurable Logic

DS031_28_100900

VirtexTM-II Platform FPGAs: Introduction and Overview

DS031-1 (v2.0) August 1, 2003

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Module 1 of 4

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GTL and GTLP

HSTL (Class I, II, III, and IV)

SSTL (3.3V and 2.5V, Class I and II)

AGP-2X

The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.

The IOB elements also support the following differential sig-
naling I/O standards:

LVDS

BLVDS (Bus LVDS)

ULVDS

LDT

LVPECL

Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.

Configurable Logic Blocks (CLBs)

CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:

Two function generators (F & G)

Two storage elements

Arithmetic logic gates

Large multiplexers

Wide function capability

Fast carry look-ahead chain

Horizontal cascade chain (OR gate)

The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.

In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.

Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.

Block SelectRAM Memory

The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in

Table 3

A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.

Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.

Global Clocking

The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
schemes.

Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
timing parameters, see

Virtex-II Electrical Characteris-

tics

Virtex-II devices have 16 global clock MUX buffers, with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.

Routing Resources

The IOB, CLB, block SelectRAM, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.

There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column as well as massive secondary and
local routing resources provide fast interconnect. Virtex-II
buffered interconnects are relatively unaffected by net
fanout and the interconnect layout is designed to minimize
crosstalk.

Horizontal and vertical routing resources for each row or
column include:

24 long lines

120 hex lines

40 double lines

16 direct connect lines (total in all four directions)

Table 3: Dual-Port And Single-Port Configurations

16K x 1 bit

2K x 9 bits

8K x 2 bits

1K x 18 bits

4K x 4 bits

512 x 36 bits

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Boundary Scan

Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 -- 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.

Configuration

Virtex-II devices are configured by loading data into internal
configuration memory, using the following five modes:

Slave-serial mode

Master-serial mode

Slave SelectMAP mode

Master SelectMAP mode

Boundary-Scan mode (IEEE 1532)

A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration
information.

Readback and Integrated Logic Analyzer

Configuration data stored in Virtex-II configuration memory
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be read back. This capability is useful for real-time debug-
ging.

The Integrated Logic Analyzer (ILA) core and software pro-
vides a complete solution for accessing and verifying
Virtex-II devices.

Virtex-II Device/Package Combinations
and Maximum I/O

Wire-bond and flip-chip packages are available.

Table 4

and

Table 5

show the maximum possible number of user I/Os in

wire-bond and flip-chip packages, respectively.

Table 6

shows the number of available user I/Os for all device/pack-
age combinations.

CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).

FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).

FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).

BG denotes standard BGA (1.27 mm pitch).

BF denotes flip-chip BGA (1.27 mm pitch).

The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD) and VBATT.

Table 4: Wire-Bond Packages Information

Package

CS144

FG256

FG456

FG676

BG575

BG728

Pitch (mm)

0.80

1.00

1.27

Size (mm)

12 x 12

17 x 17

23 x 23

27 x 27

31 x 31

35 x 35

I/Os

172

324

484

408

516

Table 5: Flip-Chip Packages Information

Package

FF896

FF1152

FF1517

BF957

Pitch (mm)

1.00

1.27

Size (mm)

31 x 31

35 x 35

40 x 40

I/Os

624

824

1,108

684

VirtexTM-II Platform FPGAs: Introduction and Overview

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Module 1 of 4

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Virtex-II Ordering Information

Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information)

Package

Available I/Os

XC2V

250

XC2V

500

XC2V

1000

XC2V

1500

XC2V

2000

XC2V

3000

XC2V

4000

XC2V

6000

XC2V

8000

CS144

FG256

120

172

FG456

200

264

324

FG676

392

456

484

FF896

432

528

624

FF1152

720

824

FF1517

912

1,104

1,108

BG575

328

392

408

BG728

516

BF957

624

684

Notes:
1.

All devices in a particular package are pinout (footprint) compatible. In addition, the FG456 and FG676 packages are compatible, as
are the FF896 and FF1152 packages.

Figure 2: Virtex-II Ordering Information

Example: XC2V1000-5FG456C

Device Type

Temperature Range
C = Commercial (Tj = 0°C to +85°C)
I = Industrial (Tj = 40°C to +100°C)

Number of Pins

Package Type

Speed Grade

(-4, -5, -6)

DS031_35_033001

VirtexTM-II Platform FPGAs: Introduction and Overview

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Revision History

This section records the change history for this module of the data sheet.

Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

VirtexTM-II Platform FPGAs: Introduction and Overview
(Module 1)

VirtexTM-II Platform FPGAs: Detailed Description
(Module 2)

VirtexTM-II Platform FPGAs: DC and Switching
Characteristics (Module 3)

VirtexTM-II Platform FPGAs: Pinout Information
(Module 4)

Date

Version

Revision

11/07/00

1.0

Early access draft.

12/06/00

1.1

Initial release.

01/15/01

1.2

Added values to the tables in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

sections.

01/25/01

1.3

The data sheet was divided into four modules (per the current style standard).

04/02/01

1.5

Skipped v1.4 to sync up modules. Reverted to traditional double-column format.

07/30/01

1.6

Made minor changes to items listed under

Summary of Virtex-II Features

10/02/01

1.7

Minor edits.

07/16/02

1.8

Updated Virtex-II Device/Package Combinations shown in

Table 6

09/26/02

1.9

Updated

Table 2

and

Table 6

to reflect supported Virtex-II Device/Package Combinations.

08/01/03

2.0

All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

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Detailed Description

Input/Output Blocks (IOBs)

Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in

Figure 1

IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.

Note: Differential I/Os must use the same clock.

Supported I/O Standards

Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V

CCINT

= 1.5V),

output driver supply voltage (V

CCO

) is dependent on the I/O

standard (see

Table 1

). An auxiliary supply voltage

CCAUX

= 3.3 V) is required, regardless of the I/O stan-

dard used. For exact supply voltage absolute maximum rat-
ings, see

DC Input and Output Levels

in Module 3.

VirtexTM-II Platform FPGAs:
Detailed Description

DS031-2 (v3.1) October 14, 2003

Product Specification

Figure 1: Virtex-II Input/Output Tile

IOB

PAD4

IOB

PAD3

Differential Pair

IOB

PAD2

IOB

PAD1

Differential Pair

Switch

Matrix

DS031_30_101600

Table 1: Supported Single-Ended I/O Standards

I/O

Standard

Output

CCO

Input
V

CCO

Input

REF

Board

Termination

Voltage (V

)

LVTTL

3.3

N/R

(3)

N/R

LVCMOS33

3.3

N/R

LVCMOS25

2.5

N/R

LVCMOS18

1.8

N/R

LVCMOS15

1.5

N/R

PCI33_3 3.3

3.3

N/R

PCI66_3 3.3

3.3

N/R

PCI-X

3.3

N/R

GTL

Note (1)

0.8

1.2

GTLP

Note (1)

1.0

1.5

HSTL_I

1.5 N/R

0.75

HSTL_II

1.5

N/R

0.75

HSTL_III 1.5

N/R

0.9

1.5

HSTL_IV

1.5 N/R

0.9

1.5

HSTL_I_18

1.8 N/R

0.9

HSTL_II_18

1.8 N/R

0.9

HSTL_III _18

1.8

N/R

1.1

1.8

HSTL_IV_18

1.8 N/R

1.1

1.8

SSTL18_I

(2)

1.8

N/R

0.9

SSTL18_II

1.8

N/R

0.9

SSTL2_I 2.5

N/R

1.25

SSTL2_II

2.5

N/R

1.25

SSTL3_I 3.3

N/R

1.5

SSTL3_II

3.3

N/R

1.5

AGP-2X/AGP

3.3

N/R

1.32

N/R

Notes:
1.

CCO

of GTL or GTLP should not be lower than the

termination voltage or the voltage seen at the I/O pad.

SSTL18_I is not a JEDEC-supported standard.

N/R = no requirement.

VirtexTM-II Platform FPGAs: Detailed Description

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All of the user IOBs have fixed-clamp diodes to VCCO and
to ground. As outputs, these IOBs are not compatible or
compliant with 5V I/O standards. As inputs, these IOBs are
not normally 5V tolerant, but can be used with 5V I/O stan-
dards when external current-limiting resistors are used. For
more details, see the "5V Tolerant I/Os" Tech Topic at

www.xilinx.com

Table 3

lists supported I/O standards with Digitally Con-

trolled Impedance. See

Digitally Controlled Impedance

(DCI), page 8

Table 2: Supported Differential Signal I/O Standards

I/O Standard

Output

CCO

Input
V

CCO

Input

REF

Output

LVPECL_33

3.3

N/R

(1)

N/R

490 mV to 1.22V

LDT_25

2.5

N/R

0.430 - 0.670

LVDS_33

3.3

N/R

0.250 - 0.400

LVDS_25

2.5

N/R

0.250 - 0.400

LVDSEXT_33

3.3

N/R

0.330 - 0.700

LVDSEXT_25

2.5

N/R

0.330 - 0.700

BLVDS_25

2.5

N/R

0.250 - 0.450

ULVDS_25

2.5

N/R

0.430 - 0.670

Notes:
1.

N/R = no requirement.

Table 3: Supported DCI I/O Standards

I/O

Standard

Output

CCO

Input
V

CCO

Input

REF

Termination

Type

LVDCI_33

(1)

3.3

N/R

(4)

Series

LVDCI_DV2_33

(1)

3.3

N/R

Series

LVDCI_25

(1)

2.5

N/R

Series

LVDCI_DV2_25

(1)

2.5

N/R

Series

LVDCI_18

(1)

1.8

N/R

Series

LVDCI_DV2_18

(1)

1.8

N/R

Series

LVDCI_15

(1)

1.5

N/R

Series

LVDCI_DV2_15

(1)

1.5

N/R

Series

GTL_DCI

1.2

0.8

Single

GTLP_DCI

1.5

1.0

Single

HSTL_I_DCI

1.5

0.75

Split

HSTL_II_DCI

1.5

0.75

Split

HSTL_III_DCI

1.5

0.9

Single

HSTL_IV_DCI

1.5

0.9

Single

HSTL_I_DCI_18

1.8

0.9

Split

HSTL_II_DCI_18

1.8

0.9

Split

HSTL_III_DCI_18

1.8

1.1

Single

HSTL_IV_DCI_18

1.8

1.1

Single

SSTL18_I_DCI

(3)

1.8

0.9

Split

SSTL18_II_DCI

1.8

0.9

Split

SSTL2_I_DCI

(2)

2.5

1.25

Split

SSTL2_II_DCI

(2)

2.5

1.25

Split

SSTL3_I_DCI

(2)

3.3

1.5

Split

SSTL3_II_DCI

(2)

3.3

1.5

Split

LVDS_33_DCI

3.3

N/R

Split

LVDS_25_DCI

2.5

N/R

Split

LVDSEXT_33_DCI

3.3

N/R

Split

LVDSEXT_25_DCI

2.5

N/R

Split

Notes:
1.

LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.

These are SSTL compatible.

SSTL18_I is not a JEDEC-supported standard.

N/R = no requirement.

VirtexTM-II Platform FPGAs: Detailed Description

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Module 2 of 4

Product Specification

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Logic Resources

IOB blocks include six storage elements, as shown in

Figure 2

Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.

Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in

Figure 3

. There are two input, output,

and 3-state data signals, each being alternately clocked out.

For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.

All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.

Each register or latch (independent of all other registers or
latches) (see

Figure 4

) can be configured as follows:

No set or reset

Synchronous set

Synchronous reset

Synchronous set and reset

Asynchronous set (preset)

Asynchronous reset (clear)

Asynchronous set and reset (preset and clear)

The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.

Figure 2: Virtex-II IOB Block

Reg

OCK1

Reg

OCK2

Reg

ICK1

Reg

ICK2

DDR mux

Input

PAD

3-State

Reg

OCK1

Reg

OCK2

DDR mux

Output

IOB

DS031_29_100900

Figure 3: Double Data Rate Registers

CLK1

DDR MUX

FDDR

CLK2

(50/50 duty cycle clock)

CLOCK

CLK1

DDR MUX

DCM

FDDR

CLK2

180

° 0°

DS031_26_100900

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Product Specification

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Input/Output Individual Options

Each device pad has optional pull-up and pull-down in all
SelectI/O-Ultra configurations. Each device pad has
optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in

Figure 5

Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 K

, which is the specification for V

CCO

when operating at 3.3V (from 3.0 to 3.6V only). The clamp
diode is always present, even when power is not.

The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on

the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper

Figure 4: Register / Latch Configuration in an IOB Block

FF
LATCH

SR REV

CK1

FF
LATCH

SR REV

FF1

FF2

DDR MUX

CK2

REV

(O/T) CLK1

(OQ or TQ)

(O/T) CE

(O/T) 1

(O/T) CLK2

(O/T) 2

Attribute INIT1

INIT0
SRHIGH
SRLOW

Attribute INIT1

INIT0
SRHIGH
SRLOW

Reset Type

SYNC
ASYNC

DS031_25_110300

Shared

by all

registers

Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards

VCCO

Weak

Keeper

Program

Delay

OBUF

IBUF

Program Current

Clamp
Diode

10-60K

PAD

VCCAUX = 3.3V

DS031_23_011601

VCCINT = 1.5V

VirtexTM-II Platform FPGAs: Detailed Description

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Product Specification

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holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.

LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see

Table 4

). Drive-strength and slew-rate con-

trols for each output driver, minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and
slew-rate controls are not available.

Figure 6

shows the SSTL2, SSTL3, and HSTL configura-

tions. HSTL can sink current up to 48 mA. (HSTL IV)

All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. Virtex-II
uses two memory cells to control the configuration of an I/O
as an input. This is to reduce the probability of an I/O con-
figured as an input from flipping to an output when sub-
jected to a single event upset (SEU) in space applications.

Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set high, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set low, the pull-up resistors are
activated on user I/O pins.

All Virtex-II IOBs support IEEE 1149.1 compatible boundary
scan testing.

Input Path

The Virtex-II IOB input path routes input signals directly to
internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II device, and when
used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V

REF

. The need to supply V

REF

imposes

constraints on which standards can be used in the same
bank. See I/O banking description.

Output Path

The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and / or the
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
or through the DDR output / 3-state registers.

Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied V

CCO

voltage. The need to supply V

CCO

imposes constraints on which standards can be used in the
same bank. See I/O banking description.

I/O Banking

Some of the I/O standards described above require V

CCO

and V

REF

voltages. These voltages are externally supplied

and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.

Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in

Figure 7

and

Figure 8

. Each

bank has multiple V

CCO

pins, all of which must be con-

Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)

SelectI/O-Ultra

Programmable Current (Worst-Case Guaranteed Minimum)

LVTTL

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

LVCMOS33

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

LVCMOS25

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

LVCMOS18

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

n/a

LVCMOS15

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

n/a

Figure 6: SSTL or HSTL SelectI/O-Ultra Standards

VCCO

OBUF

VREF

Clamp
Diode

PAD

VCCAUX = 3.3V
VCCINT = 1.5V

DS031_24_100900

VirtexTM-II Platform FPGAs: Detailed Description

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Module 2 of 4

Product Specification

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nected to the same voltage. This voltage is determined by
the output standards in use.

Some input standards require a user-supplied threshold
voltage (V

REF

), and certain user-I/O pins are automatically

configured as V

REF

inputs. Approximately one in six of the

I/O pins in the bank assume this role.

REF

pins within a bank are interconnected internally, and

consequently only one V

REF

voltage can be used within

each bank. However, for correct operation, all V

REF

pins in

the bank must be connected to the external reference volt-
age source.

The V

CCO

and the V

REF

pins for each bank appear in the

device pinout tables. Within a given package, the number of
V

REF

and V

CCO

pins can vary depending on the size of

device. In larger devices, more I/O pins convert to V

REF

pins. Since these are always a superset of the V

REF

pins

used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.

All V

REF

pins for the largest device anticipated must be con-

nected to the V

REF

voltage and not used for I/O. In smaller

devices, some V

CCO

pins used in larger devices do not con-

nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to V

CCO

to permit migration to a larger device.

Rules for Combining I/O Standards in the Same Bank

The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:

Combining output standards only. Output standards
with the same output V

CCO

requirement can be

combined in the same bank.

Compatible example:

SSTL2_I and LVDS_25_DCI outputs

Incompatible example:

SSTL2_I (output V

CCO

= 2.5V) and

LVCMOS33 (output V

CCO

= 3.3V) outputs

Combining input standards only. Input standards
with the same input V

CCO

and input V

REF

requirements

can be combined in the same bank.

Compatible example:

LVCMOS15 and HSTL_IV inputs

Incompatible example:

LVCMOS15 (input V

CCO

= 1.5V) and

LVCMOS18 (input V

CCO

= 1.8V) inputs

Incompatible example:

HSTL_I_DCI_18 (V

REF

= 0.9V) and

HSTL_IV_DCI_18 (V

REF

= 1.1V) inputs

Combining input standards and output standards.
Input standards and output standards with the same
input V

CCO

and output V

CCO

requirement can be

combined in the same bank.

Compatible example:

LVDS_25 output and HSTL_I input

Incompatible example:

LVDS_25 output (output V

CCO

= 2.5V) and

HSTL_I_DCI_18 input (input V

CCO

= 1.8V)

Combining bi-directional standards with input or
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.

Additional rules for combining DCI I/O standards.

No more than one Single Termination type (input or
output) is allowed in the same bank.

Incompatible example:

HSTL_IV_DCI input and HSTL_III_DCI input

No more than one Split Termination type (input or
output) is allowed in the same bank.

Incompatible example:

HSTL_I_DCI input and HSTL_II_DCI input

The implementation tools will enforce these design rules.

Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond

Packages (CS, FG, & BG)

Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip

Packages (FF & BF)

ug002_c2_014_112900

Bank 0

Bank 1

Bank 5

Bank 4

Bank 7

Bank 6

Bank 2

Bank 3

ds031_66_112900

Bank 1

Bank 0

Bank 4

Bank 5

Bank 2

Bank 3

Bank 7

Bank 6

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Module 2 of 4

Product Specification

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Table 5

summarizes all standards and voltage supplies.

Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards

I/O Standard

CCO

REF

Termination Type

Output

Input

Output

Input

LVDS_33

3.3

N/R

(1)

N/R

LVDSEXT_33

N/R

LVPECL_33

N/R

SSTL3_I

1.5

N/R

SSTL3_II

1.5

N/R

AGP

1.32

N/R

LVTTL

3.3

N/R

LVCMOS33

N/R

LVDCI_33

N/R

Series

N/R

LVDCI_DV2_33

N/R

Series

N/R

PCI33_3

N/R

PCI66_3

N/R

PCIX

N/R

LVDS_33_DCI

N/R

Split

LVDSEXT_33_DCI

N/R

Split

SSTL3_I_DCI

1.5

N/R

Split

SSTL3_II_DCI

1.5

Split

LVDS_25

2.5

N/R

LVDSEXT_25

N/R

LDT_25

N/R

ULVDS_25

N/R

BLVDS_25

N/R

SSTL2_I

1.25

N/R

SSTL2_II

1.25

N/R

LVCMOS25

2.5

N/R

LVDCI_25

N/R

Series

N/R

LVDCI_DV2_25

N/R

Series

N/R

LVDS_25_DCI

N/R

Split

LVDSEXT_25_DCI

N/R

Split

SSTL2_I_DCI

1.25

N/R

Split

SSTL2_II_DCI

1.25

Split

HSTL_III_18

1.8

N/R

1.1

N/R

HSTL_IV_18

1.1

N/R

HSTL_I_18

0.9

N/R

HSTL_II_18

0.9

N/R

SSTL18_I

0.9

N/R

SSTL18_II

0.9

N/R

LVCMOS18

1.8

N/R

LVDCI_18

N/R

Series

N/R

LVDCI_DV2_18

N/R

Series

N/R

HSTL_III_DCI_18

1.1

N/R

Single

HSTL_IV_DCI_18

1.1

Single

HSTL_I_DCI_18

0.9

N/R

Split

HSTL_II_DCI_18

0.9

Split

SSTL18_I_DCI

0.9

N/R

Split

SSTL18_II_DCI

0.9

Split

HSTL_III

1.5

N/R

0.9

N/R

HSTL_IV

0.9

N/R

HSTL_I

0.75

N/R

HSTL_II

0.75

N/R

LVCMOS15

1.5

N/R

LVDCI_15

N/R

Series

N/R

LVDCI_DV2_15

N/R

Series

N/R

GTLP_DCI

Single

HSTL_III_DCI

0.9

N/R

Single

HSTL_IV_DCI

0.9

Single

HSTL_I_DCI

0.75

N/R

Split

HSTL_II_DCI

0.75

Split

GTL_DCI

1.2

0.8

Single

GTLP

N/R

GTL

0.8

N/R

Notes:
1.

N/R = no requirement.

Table 5: Summary of Voltage Supply Requirements for
All Input and Output Standards (Continued)

I/O Standard

CCO

REF

Termination Type

Output

Input

Output

Input

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Digitally Controlled Impedance (DCI)

Today's chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.

Virtex-II XCITE DCI provides controlled impedance drivers
and on-chip termination for single-ended and differential
I/Os. This eliminates the need for external resistors, and
improves signal integrity. The DCI feature can be used on
any IOB by selecting one of the DCI I/O standards.

When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.

DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in

Figure 9

When used with a terminated I/O standard, the value of
resistors are specified by the standard (typically 50

When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (25

to 100 ). For all series and parallel termina-

tions listed in

Table 6

and

Table 7

, the reference resistors

must have the same value for any given bank. One percent
resistors are recommended.

The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.

Controlled Impedance Drivers (Series
Termination)

DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z). Virtex-II input
buffers also support LVDCI and LVDCI_DV2 I/O standards.

Controlled Impedance Drivers (Parallel
Termination)

DCI also provides on-chip termination for SSTL3, SSTL2,
HSTL (Class I, II, III, or IV), and GTL/GTLP receivers or
transmitters on bidirectional lines.

Table 7

lists the on-chip parallel terminations available in Vir-

tex-II devices. V

CCO

must be set according to

Table 3

. Note

that there is a V

CCO

requirement for GTL_DCI and

GTLP_DCI, due to the on-chip termination resistor.

Figure 9: DCI in a Virtex-II Bank

DS031_50_101200

VCCO

GND

DCI

VRN

VRP

1 Bank

REF

(1%)

REF

(1%)

Figure 10: Internal Series Termination

Table 6: SelectI/O-Ultra Controlled Impedance Buffers

CCO

DCI

DCI Half Impedance

3.3 V

LVDCI_33

LVDCI_DV2_33

2.5 V

LVDCI_25

LVDCI_DV2_25

1.8 V

LVDCI_18

LVDCI_DV2_18

1.5 V

LVDCI_15

LVDCI_DV2_15

Table 7: SelectI/O-Ultra Buffers With On-Chip Parallel
Termination

I/O Standard

External

Termination

On-Chip

Termination

SSTL3 Class I

SSTL3_I

SSTL3_I_DCI

(1)

SSTL3 Class II

SSTL3_II

SSTL3_II_DCI

(1)

SSTL2 Class I

SSTL2_I

SSTL2_I_DCI

(1)

SSTL2 Class II

SSTL2_II

SSTL2_II_DCI

(1)

HSTL Class I

HSTL_I

HSTL_I_DCI

HSTL Class II

HSTL_II

HSTL_II_DCI

HSTL Class III

HSTL_III

HSTL_III_DCI

HSTL Class IV

HSTL_IV

HSTL_IV_DCI

GTL

GTL_DCI

GTLP

GTLP_DCI

Notes:
1.

SSTL Compatible

IOB

Virtex-II DCI

DS031_51_110600

CCO

= 3.3 V, 2.5 V, 1.8 V or 1.5 V

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Figure 11

provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O

standards. For a complete list, see the Virtex-II User Guide.

Figure 11: HSTL DCI Usage Examples

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO/2

Virtex-II DCI

VCCO

VCCO/2

Virtex-II DCI

VCCO/2

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

DS031_65a_100201

Conventional

DCI Transmit
Conventional
Receive

Conventional
Transmit
DCI Receive

DCI Transmit
DCI Receive

Bidirectional

Reference
Resistor

Recommended
Z0

(1)

VRN = VRP = R = Z0

HSTL_I

HSTL_II

HSTL_III

HSTL_IV

N/A

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO/2

Virtex-II DCI

VCCO/2

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Note:

1. Z0 is the recommended PCB trace impedance.

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Product Specification

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Figure 12

provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O

standards. For a complete list, see the Virtex-II User Guide.

Figure 12: SSTL DCI Usage Examples

DS031_65b_112502

Conventional

DCI Transmit
Conventional
Receive

Conventional
Transmit
DCI Receive

DCI Transmit
DCI Receive

Bidirectional

Reference
Resistor

Recommended
Z0

(2)

VRN = VRP = R = Z0

SSTL2_I

SSTL2_II

SSTL3_I

SSTL3_II

N/A

Virtex-II DCI

CCO

R/2

VCCO/2

R/2

VCCO/2

R/2

CCO

R/2

VCCO/2

R/2

Virtex-II DCI

VCCO

VCCO/2

R/2

Virtex-II DCI

VCCO

R/2

Virtex-II DCI

VCCO

R/2

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

VCCO/2

Virtex-II DCI

VCCO

VCCO/2

Virtex-II DCI

VCCO/2

Virtex-II DCI

CCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

Virtex-II DCI

VCCO

(1)

Notes:

1. The SSTL-compatible 25

series resistor is accounted for in the DCI buffer, and it is not DCI controlled.

2. Z0 is the recommended PCB trace impedance.

VirtexTM-II Platform FPGAs: Detailed Description

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Figure 13

provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list,

see the Virtex-II User Guide.

Figure 13: LVDS DCI Usage Examples

DS031_65c_022103

Conventional

Conventional
Transmit
DCI Receive

Reference
Resistor

Recommended
Z0

VRN = VRP = R = Z0

LVDS_DCI and LVDSEXT_DCI Receiver

Virtex-II
LVDS DCI

CCO

Virtex-II
LVDS

NOTE: Only LVDS25_DCI is supported (V

CCO

= 2.5V only)

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Configurable Logic Blocks (CLBs)

The Virtex-II configurable logic blocks (CLB) are organized
in an array and are used to build combinatorial and synchro-
nous logic designs. Each CLB element is tied to a switch
matrix to access the general routing matrix, as shown in

Figure 14

. A CLB element comprises 4 similar slices, with

fast local feedback within the CLB. The four slices are split
in two columns of two slices with two independent carry
logic chains and one common shift chain.

Slice Description

Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in

Figure 15

, each 4-input

function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit vari-
able-tap shift register element.

The output from the function generator in each slice drives
both the slice output and the D input of the storage element.

Figure 16

shows a more detailed view of a single slice.

Configurations

Look-Up Table

Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are pro-
vided to each of the two function generators in a slice (F and
G). These function generators are each capable of imple-
menting any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in

Figure 16

In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX are either MUXF6,
MUXF7 or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexers to map
any functions of six, seven, or eight inputs and selected
wide logic functions.

Register/Latch

The storage elements in a Virtex-II slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D input can be directly driven by the X or Y
output via the DX or DY input, or by the slice inputs bypass-
ing the function generators via the BX or BY input. The clock
enable signal (CE) is active High by default. If left uncon-
nected, the clock enable for that storage element defaults to
the active state.

In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic "1" when SR is asserted. SRLOW forces a logic "0".
When SR is used, a second input (BY) forces the storage
element into the opposite state. The reset condition is pre-
dominant over the set condition. (See

Figure 17

The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.

For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II devices also have the ability to
set INIT0 and INIT1 independent of SRHIGH and SRLOW.

The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.

Figure 14: Virtex-II CLB Element

Figure 15: Virtex-II Slice Configuration

Slice

X1Y1

Slice

X1Y0

Slice

X0Y1

Slice

X0Y0

Fast
Connects
to neighbors

Switch

Matrix

DS031_32_101600

SHIFT

CIN

COUT

TBUF X0Y1

COUT

CIN

TBUF X0Y0

MUXF5

MUXFx

SRL16

RAM16

LUT

Arithmetic Logic

LUT

DS031_31_100900

SRL16

RAM16

ORCY

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Figure 16: Virtex-II Slice (Top Half)

SOPIN

WG4

WG3

WG2

WG1

Dual-Port

LUT

FF
LATCH

RAM
ROM

Shift-Reg

MC15

REV

G1
BY

1
0

PROD

CLK

MUXCY

DIG

MUXCY

SOPOUT

DYMUX

GYMUX

YBMUX

ORCY

WSG

WE[2:0]

SHIFTOUT

CYOG

XORG

WE
CLK

WSF

ALTDIG

CLK

SLICEWE[2:0]

MULTAND

Shared between
x & y Registers

SHIFTIN

COUT

CIN

DS031_01_112502

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The set and reset functionality of a register or a latch can be
configured as follows:

No set or reset

Synchronous set

Synchronous reset

Synchronous set and reset

Asynchronous set (preset)

Asynchronous reset (clear)

Asynchronous set and reset (preset and clear)

The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.

Distributed SelectRAM Memory

Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:

Single-Port 16 x 8 bit RAM

Single-Port 32 x 4 bit RAM

Single-Port 64 x 2 bit RAM

Single-Port 128 x 1 bit RAM

Dual-Port 16 x 4 bit RAM

Dual-Port 32 x 2 bit RAM

Dual-Port 64 x 1 bit RAM

Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.

Table 8

shows the number of LUTs (2 per slice) occupied by

each distributed SelectRAM configuration.

For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.

For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).

In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.

Figure 17: Register / Latch Configuration in a Slice

FFY

LATCH

SR REV

FFX

LATCH

SR REV

CLK

Attribute

INIT1
INIT0
SRHIGH
SRLOW

Attribute

INIT1
INIT0
SRHIGH
SRLOW

Reset Type

SYNC
ASYNC

DS031_22_110600

Table 8: Distributed SelectRAM Configurations

RAM

Number of LUTs

16 x 1S

16 x 1D

32 x 1S

32 x 1D

64 x 1S

64 x 1D

128 x 1S

Notes:
1.

S = single-port configuration; D = dual-port configuration

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Figure 18

Figure 19

, and

Figure 20

illustrate various exam-

ple configurations.

Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are available: ROM16x1, ROM32x1, ROM64x1,
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.

Table 9

shows the number

of LUTs occupied by each configuration.

Figure 18: Distributed SelectRAM (RAM16x1S)

Figure 19: Single-Port Distributed SelectRAM

(RAM32x1S)

A[3:0]

WSG

WCLK

RAM 16x1S

RAM

WE
CK

A[4:1]

WG[4:1]

Output

Registered
Output

(optional)

(SR)

(BY)

DS031_02_100900

A[3:0]

WSG

F5MUX

WCLK

RAM 32x1S

D Q

WE0

WSF

RAM

G[4:1]

A[4]

WG[4:1]

RAM

F[4:1]

WF[4:1]

Output

Registered
Output

(optional)

(SR)

(BY)

(BX)

DS031_03_110100

Figure 20: Dual-Port Distributed SelectRAM

(RAM16x1D)

Table 9: ROM Configuration

ROM

Number of LUTs

16 x 1

32 x 1

64 x 1

128 x 1

8 (1 CLB)

256 x 1

16 (2 CLBs)

A[3:0]

WSG

WCLK

RAM 16x1D

WE
CK

RAM

G[4:1]

WG[4:1]

dual_port

RAM

dual_port

(BY)

DPRA[3:0]

SPO

A[3:0]

WSG

WE
CK

G[4:1]

WG[4:1]

DPO

DS031_04_110100

(SR)

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Shift Registers

Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in

Figure 21

. A dynamic read access is performed through the

4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous, how-
ever the storage element or flip-flop is available to
implement a synchronous read. The storage element
should always be used with a constant address. For exam-
ple, when building an 8-bit shift register and configuring the
addresses to point to the 7th bit, the 8th bit can be the
flip-flop. The overall system performance is improved by
using the superior clock-to-out of the flip-flops.

An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See

Figure 22

.) Longer shift registers can be built with dynamic

access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.

Figure 21: Shift Register Configurations

A[3:0]

SHIFTIN

SHIFTOUT

D(BY)

MC15

WSG

CE (SR)

CLK

SRLC16

SHIFT-REG

WE
CK

A[4:1]

Output

Registered
Output

(optional)

DS031_05_110600

Figure 22: Cascadable Shift Register

SRLC16

MC15

SRLC16

SHIFTIN

CASCADABLE OUT

SLICE S0

SLICE S1

SLICE S2

SLICE S3

1 Shift Chain
in CLB

CLB

DS031_06_110200

SRLC16

MC15

SRLC16

SHIFTIN

SHIFTOUT

SRLC16

MC15

SRLC16

SHIFTIN

SHIFTOUT

SRLC16

MC15

SRLC16

SHIFTOUT

OUT

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Multiplexers

Virtex-II function generators and associated multiplexers
can implement the following:

4:1 multiplexer in one slice

8:1 multiplexer in two slices

16:1 multiplexer in one CLB element (4 slices)

32:1 multiplexer in two CLB elements (8 slices)

Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in

Figure 23

Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II User Guide. Any
LUT can implement a 2:1 multiplexer.

Fast Lookahead Carry Logic

Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the

Figure 24

The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also

be used to cascade function generators for implementing
wide logic functions.

Arithmetic Logic

The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in

Figure 16

)

improves the efficiency of multiplier implementation.

Figure 23: MUXF5 and MUXFX multiplexers

Slice S1

Slice S0

Slice S3

Slice S2

CLB

DS031_08_100201

MUXF8 combines
the two MUXF7 outputs
(Two CLBs)

MUXF6 combines the two MUXF5
outputs from slices S2 and S3

MUXF7 combines the two MUXF6
outputs from slices S0 and S2

MUXF6 combines the two MUXF5
outputs from slices S0 and S1

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Figure 24: Fast Carry Logic Path

LUT

O I

MUXCY

LUT

O I

MUXCY

LUT

O I

MUXCY

LUT

O I

MUXCY

CIN

COUT

LUT

O I

MUXCY

LUT

O I

MUXCY

LUT

O I

MUXCY

LUT

O I

MUXCY

CIN

COUT

COUT
to CIN of S2 of the next CLB

COUT
to S0 of the next CLB

(First Carry Chain)

(Second Carry Chain)

SLICE S1

SLICE S0

SLICE S3

SLICE S2

CLB

DS031_07_110200

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Sum of Products

Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in

Figure 25

LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions.

Figure 26

illustrates

LUT and MUXCY resources configured as a 16-input AND
gate.

Figure 25: Horizontal Cascade Chain

MUXCY

Slice 1

ds031_64_110300

ORCY

LUT

MUXCY

Slice 0

LUT

MUXCY

Slice 3

ORCY

LUT

MUXCY

Slice 2

LUT

SOP

CLB

MUXCY

Slice 1

ORCY

LUT

MUXCY

Slice 0

LUT

MUXCY

Slice 3

ORCY

LUT

MUXCY

Slice 2

LUT

CLB

Figure 26: Wide-Input AND Gate (16 Inputs)

MUXCY

AND

MUXCY

"0"

MUXCY

Slice

OUT

Slice

LUT

DS031_41_110600

LUT

VCC

MUXCY

LUT

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3-State Buffers

Introduction

Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip busses. Each 3-state buffer has its
own 3-state control pin and its own input pin.

Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in

Figure 27

TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state busses.

The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.

Locations / Organization

Four horizontal routing resources per CLB are provided for
on-chip 3-state busses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned
as shown in

Figure 28

. The switch matrices corresponding

to SelectRAM memory and multiplier or I/O blocks are
skipped.

Number of 3-State Buffers

Table 10

shows the number of 3-state buffers available in

each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.

CLB/Slice Configurations

Table 11

summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be

implemented in one of the configurations listed.

Table 12

shows the available resources in all CLBs.

Figure 27: Virtex-II 3-State Buffers

Slice

Switch

Matrix

DS031_37_060700

TBUF

Table 10: Virtex-II 3-State Buffers

Device

3-State Buffers

per Row

Total Number

of 3-State Buffers

XC2V40

128

XC2V80

256

XC2V250

768

XC2V500

1,536

XC2V1000

2,560

XC2V1500

3,840

XC2V2000

5,376

XC2V3000

112

7,168

XC2V4000

144

11,520

XC2V6000

176

16,896

XC2V8000

208

23,296

Figure 28: 3-State Buffer Connection to Horizontal Lines

Switch

matrix

CLB-II

Switch

matrix

CLB-II

DS031_09_032700

Programmable

connection

3 - state lines

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18 Kbit Block SelectRAM

Resources

Introduction

Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.

Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).

Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a

rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.

Configuration

The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in

Table 13

Table 11: Logic Resources in One CLB

Slices

LUTs

Flip-Flops

MULT_ANDs

Arithmetic &

Carry-Chains

SOP

Chains

Distributed
SelectRAM

Shift

Registers

TBUF

128 bits

Table 12: Virtex-II Logic Resources Available in All CLBs

Device

CLB Array:

Row x

Column

Number

Slices

Number

LUTs

Max Distributed

SelectRAM or Shift

Register (bits)

Number

Flip-Flops

Number

Carry-Chains

(1)

Number

of SOP

Chains

(1)

XC2V40

8 x 8

256

512

8,192

512

XC2V80

16 x 8

512

1,024

16,384

1,024

XC2V250

24 x 16

1,536

3,072

49,152

3,072

XC2V500

32 x 24

3,072

6,144

98,304

6,144

XC2V1000

40 x 32

5,120

10,240

163,840

10,240

XC2V1500

48 x 40

7,680

15,360

245,760

15,360

XC2V2000

56 x 48

10,752

21,504

344,064

21,504

112

XC2V3000

64 x 56

14,336

28,672

458,752

28,672

112

128

XC2V4000

80 x 72

23,040

46,080

737,280

46,080

144

160

XC2V6000

96 x 88

33,792

67,584

1,081,344

67,584

176

192

XC2V8000

112 x 104

46,592

93,184

1,490,944

93,184

208

224

Notes:
1.

The carry-chains and SOP chains can be split or cascaded.

Table 13: Dual- and Single-Port Configurations

16K x 1 bit

2K x 9 bits

8K x 2 bits

1K x 18 bits

4K x 4 bits

512 x 36 bits

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Single-Port Configuration

As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.

Each block SelectRAM cell is a fully synchronous memory
as illustrated in

Figure 29

. Input data bus and output data

bus widths are identical.

Dual-Port Configuration

As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.

Table 14

illustrates the different configurations available on

ports A & B.

If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the

16 K-bit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbits.

Figure 29: 18 Kbit Block SelectRAM Memory in

Single-Port Mode

DOP

DIP

ADDR

SSR

CLK

18 Kbit Block SelectRAM

DS031_10_071602

Table 14: Dual-Port Mode Configurations

Port A

16K x 1

Port B

16K x 1

8K x 2

4K x 4

2K x 9

1K x 18

512 x 36

Port A

8K x 2

Port B

8K x 2

4K x 4

2K x 9

1K x 18

512 x 36

Port A

4K x 4

Port B

4K x 4

2K x 9

1K x 18

512 x 36

Port A

2K x 9

Port B

2K x 9

1K x 18

512 x 36

Port A

1K x 18

Port B

1K x 18

512 x 36

Port A

512 x 36

Port B

512 x 36

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Each block SelectRAM cell is a fully synchronous memory,
as illustrated in

Figure 30

. The two ports have independent

inputs and outputs and are independently clocked.

Port Aspect Ratios

Table 15

shows the depth and the width aspect ratios for the

18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.

Read/Write Operations

The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.

The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.

A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:

"WRITE_FIRST"

The "WRITE_FIRST" option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in

Figure 31

Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode

DOPA

DOPB

DIPA

ADDRA

WEA

ENA

SSRA

CLKA

DIPB

ADDRB

WEB

ENB

SSRB

CLKB

18 Kbit Block SelectRAM

DS031_11_071602

DOB

DOA

DIA

DIB

Table 15: 18 Kbit Block SelectRAM Port Aspect Ratio

Width

Depth

Address Bus

Data Bus

Parity Bus

16,384

ADDR[13:0]

DATA[0]

N/A

8,192

ADDR[12:0]

DATA[1:0]

N/A

4,096

ADDR[11:0]

DATA[3:0]

N/A

2,048

ADDR[10:0]

DATA[7:0] Parity[0]

1,024

ADDR[9:0]

DATA[15:0] Parity[1:0]

512

ADDR[8:0]

DATA[31:0]

Parity[3:0]

Figure 31: WRITE_FIRST Mode

CLK

Data_in

New

Address

Internal

Memory

Data_out = Data_in

Data_out

DS031_14_102000

New

RAM Contents

New

Old

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"READ_FIRST"

The "READ_FIRST" option is a read-before-write mode.

The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in

Figure 32

"NO_CHANGE"

The "NO_CHANGE" option maintains the content of the output registers, regardless of the write operation. The clock edge
during the write mode has no effect on the content of the data output register DO. When the port is configured as
"NO_CHANGE", only a read operation loads a new value in the output register DO, as shown in

Figure 33

Figure 32: READ_FIRST Mode

CLK

Data_in

New

Old

Address

Internal

Memory

Prior stored data

Data_out

DS031_13_102000

RAM Contents

New

Old

Figure 33: NO_CHANGE Mode

CLK

Data_in

New

Last Read Cycle Content (no change)

Address

Internal

Memory

No change during write

Data_out

DS031_12_102000

RAM Contents

New

Old

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Control Pins and Attributes

Virtex-II SelectRAM memory has two independent ports
with the control signals described in

Table 16

. All control

inputs including the clock have an optional inversion.

Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.

Locations

Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the

number of CLBs in a column divided by four. Column loca-
tions are shown in

Table 17

Table 16: Control Functions

Control Signal

Function

CLK

Read and Write Clock

Enable affects Read, Write, Set, Reset

Write Enable

SSR

Set DO register to SRVAL (attribute)

Table 17: SelectRAM Memory Floor Plan

Device

Columns

SelectRAM Blocks

Per Column

Total

XC2V40

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

120

XC2V6000

144

XC2V8000

168

Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

SelectRAM Blocks

ds031_38_101000

2 CLB column

2 CLB columns

SelectRAM Blocks

2 CLB column

2 CLB columns

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Total Amount of SelectRAM Memory

Table 18

shows the amount of block SelectRAM memory

available for each Virtex-II device. The 18 Kbit SelectRAM
blocks are cascadable to implement deeper or wider single- or
dual-port memory resources.

18-Bit x 18-Bit Multipliers

Introduction

A Virtex-II multiplier block is an 18-bit by 18-bit 2's comple-
ment signed multiplier. Virtex-II devices incorporate many
embedded multiplier blocks. These multipliers can be asso-
ciated with an 18 Kbit block SelectRAM resource or can be
used independently. They are optimized for high-speed
operations and have a lower power consumption compared
to an 18-bit x 18-bit multiplier in slices.

Each SelectRAM memory and multiplier block is tied to four
switch matrices, as shown in

Figure 35

Association With Block SelectRAM Memory

The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the multi-
plier shares inputs with the upper data bits of the
SelectRAM memory.

This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM resource feeding the multi-
plier. The use of SelectRAM memory and the multiplier with
an accumulator in LUTs allows for implementation of a digi-
tal signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.

Configuration

The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits.

Figure 36

shows a multiplier block.

Table 18: Virtex-II SelectRAM Memory Available

Device

Total SelectRAM Memory

Blocks

in Kbits

in Bits

XC2V40

73,728

XC2V80

144

147,456

XC2V250

432

442,368

XC2V500

576

589,824

XC2V1000

720

737,280

XC2V1500

864

884,736

XC2V2000

1,008

1,032,192

XC2V3000

1,728

1,769,472

XC2V4000

120

2,160

2,211,840

XC2V6000

144

2,592

2,654,208

XC2V8000

168

3,024

3,096,576

Figure 35: SelectRAM and Multiplier Blocks

Figure 36: Multiplier Block

Switch

Matrix

Switch

Matrix

18-Kbit block

SelectRAM

18 x 18 Multiplier

Switch

Matrix

Switch

Matrix

DS031_33_101000

MULT 18 x 18

A[17:0]

P[35:0]

B[17:0]

Multiplier Block

DS031_40_100400

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Locations / Organization

Multiplier organization is identical to the 18 Kbit SelectRAM
organization, because each multiplier is associated with an
18 Kbit block SelectRAM resource.

In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to

Configurable Logic Blocks (CLBs)

Table 19: Multiplier Floor Plan

Device

Columns

Multipliers

Per Column

Total

XC2V40

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

120

XC2V6000

144

XC2V8000

168

Figure 37: Multipliers (2-column, 4-column, and 6-column)

DS031_39_101000

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

2 CLB columns

n CLB columns

Multiplier Blocks

2 CLB column

2 CLB columns

Multiplier Blocks

2 CLB column

2 CLB columns

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Global Clock Multiplexer Buffers

Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in

Figure 38

The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.

Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in

Digital

Clock Manager (DCM), page 30

. Each global clock buffer

can also be driven by local interconnects. The DCM has
clock output(s) that can be connected to global clock buffer
inputs, as shown in

Figure 39

Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.

Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide).

Figure 40

shows clock distribution in Virtex-II devices.

Figure 38: Virtex-II Clock Pads

8 clock pads

Virtex-II

Device

DS031_42_101000

Figure 39: Virtex-II Clock Distribution Configurations

Clock

Pad

Clock

Buffer

Clock Distribution

Clock

Pad

Clock

Buffer

Clock Distribution

CLKIN

CLKOUT

DCM

DS031_43_101000

Figure 40: Virtex-II Clock Distribution

DS031_45_120200

8 BUFGMUX

8 max

8 BUFGMUX

16 Clocks

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In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.

To reduce power consumption, any unused clock branches
remain static.

Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).

The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in

Figure 41

The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (

Figure 42

), as well as

a two-input clock multiplexer (

Figure 43

). A functional

description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.

This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.

BUFGCE

If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.

If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.

BUFGMUX

BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the I0 input,
a High on S selects the I1 input. Switching from one clock to
the other is done in such a way that the output High and Low
time is never shorter than the shortest High or Low time of
either input clock. As long as the presently selected clock is
High, any level change of S has no effect .

If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.

The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock; that is, prior to the rising edge of the
BUFGMUX output O. Violating this setup time requirement
can result in an undefined runt pulse output.

All Virtex-II devices have 16 global clock multiplexer buffers.

Figure 44

shows a switchover from CLK0 to CLK1.

The current clock is CLK0.

S is activated High.

If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.

Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.

When CLK1 transitions from High to Low, the output
switches to CLK1.

No glitches or short pulses can appear on the output.

Figure 41: Virtex-II BUFG Function

Figure 42: Virtex-II BUFGCE Function

BUFG

DS031_61_101200

BUFGCE

DS031_62_101200

Figure 43: Virtex-II BUFGMUX Function

Figure 44: Clock Multiplexer Waveform Diagram

BUFGMUX

DS031_63_112900

CLK0

CLK1

OUT

Wait for Low

Switch

DS031_46_112900

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Local Clocking

In addition to global clocks, there are local clock resources
in the Virtex-II devices. There are more than 72 local clocks
in the Virtex-II family. These resources can be used for
many different applications, including but not limited to

memory interfaces. For example, even using only the left
and right I/O banks, Virtex-II FPGAs can support up to 50
local clocks for DDR SDRAM. These interfaces can operate
beyond 200 MHz on Virtex-II devices.

Digital Clock Manager (DCM)

The Virtex-II DCM offers a wide range of powerful clock
management features.

Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.

Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.

Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.

The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.

Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see

Figure 45

). All DCM clock outputs can simul-

taneously drive general routing resources, including routes
to output buffers.

The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.

The DCM has the following general control signals:

RST input pin

resets the entire DCM

LOCKED output pin: asserted High when all enabled
DCM circuits have locked.

STATUS output pins (active High): shown in

Table 20

Clock De-Skew

The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.

To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X. Note
that CLKFB must always be connected, unless only the CLKFX
or CLKFX180 outputs are used and de-skew is not required.

Frequency Synthesis

The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.

The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:

FREQ

CLKFX

= (M/D) * FREQ

CLKIN

Figure 45: Digital Clock Manager

CLKIN

CLKFB

CLK180
CLK270

CLK0

CLK90

CLK2X

CLK2X180

CLKDV

DCM

DS031_67_112900

CLKFX

CLKFX180

LOCKED

STATUS[7:0]

PSDONE

RST

DSSEN

PSINCDEC

PSEN

PSCLK

clock signal

control signal

Table 20: DCM Status Pins

Status Pin

Function

Phase Shift Overflow

CLKIN Stopped

CLKFX Stopped

N/A

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where M and D are two integers. Specifications for M and D
are provided under

DCM Timing Parameters

in Module 3.

By default, M=4 and D=1, which results in a clock output fre-
quency four times faster than the clock input frequency
(CLKIN).

CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).

Note that CLK2X and CLK2X180 are not available in
high-frequency mode.

Phase Shifting

The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.

Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.

In variable mode, the

PHASE_SHIFT

value can also be

dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.

Figure 46

illustrates the effects of fine-phase

shifting. For more information on DCM features, see the
Virtex-II User Guide.

Table 21

lists fine-phase shifting control pins, when used in

variable mode.

Two separate components of the phase shift range must be
understood:

PHASE_SHIFT

attribute range

FINE_SHIFT_RANGE

DCM timing parameter range

The

PHASE_SHIFT

attribute is the numerator in the following

equation:

Phase Shift (ns) = (

PHASE_SHIFT

/256) * PERIOD

CLKIN

The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the

FINE_SHIFT_RANGE

component, which represents

the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-

lute range is guaranteed to be as specified under

DCM Tim-

ing Parameters

in Module 3.

Absolute range (fixed mode) = ±

FINE_SHIFT_RANGE

Absolute range (variable mode) = ±

FINE_SHIFT_RANGE

The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the

PHASE_SHIFT

value never changes after configu-

ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).

Table 21: Fine-Phase Shifting Control Pins

Control Pin

Direction

Function

PSINCDEC

Increment or decrement

PSEN

Enable ± phase shift

PSCLK

Clock for phase shift

PSDONE

out

Active when completed

Figure 46: Fine-Phase Shifting Effects

CLKOUT_PHASE_SHIFT
= FIXED

CLKOUT_PHASE_SHIFT
= VARIABLE

CLKOUT_PHASE_SHIFT
= NONE

CLKIN

CLKFB

(PS/256) x PERIODCLKIN

(PS negative)

(PS/256) x PERIODCLKIN

(PS positive)

(PS/256) x PERIODCLKIN

(PS negative)

(PS/256) x PERIODCLKIN

(PS positive)

DS031_48_101201

CLKFB

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Taking both of these components into consideration, the fol-
lowing are some usage examples:

If PERIOD

CLKIN

= 2 *

FINE_SHIFT_RANGE

, then

PHASE_SHIFT in

fixed mode is limited to

128, and in

variable mode it is limited to

64.

If PERIOD

CLKIN

FINE_SHIFT_RANGE

, then

PHASE_SHIFT in

fixed mode is limited to

255, and in

variable mode it is limited to

128.

If PERIOD

CLKIN

0.5 *

FINE_SHIFT_RANGE

, then

PHASE_SHIFT

is limited to

255 in either mode.

Operating Modes

The frequency ranges of DCM input and output clocks
depend on the operating mode specified, either
low-frequency mode or high-frequency mode, according to

Table 22

. (For actual values, see

Virtex-II Switching Char-

acteristics

in Module 3). The CLK2X, CLK2X180, CLK90,

and CLK270 outputs are not available in high-frequency
mode.

High or low-frequency mode is selected by an attribute.

Locations/Organization

Virtex-II DCMs are placed on the top and bottom of each
block RAM and multiplier column. The number of DCMs
depends on the device size, as shown in

Table 23

Table 22: DCM Frequency Ranges

Output Clock

Low-Frequency Mode

High-Frequency Mode

CLKIN Input

CLK Output

CLKIN Input

CLK Output

CLK0, CLK180

CLKIN_FREQ_DLL_LF

CLKOUT_FREQ_1X_LF

CLKIN_FREQ_DLL_HF

CLKOUT_FREQ_1X_HF

CLK90, CLK270

CLKIN_FREQ_DLL_LF

CLKOUT_FREQ_1X_LF

CLK2X, CLK2X180

CLKIN_FREQ_DLL_LF

CLKOUT_FREQ_2X_LF

CLKDV

CLKIN_FREQ_DLL_LF

CLKOUT_FREQ_DV_LF

CLKIN_FREQ_DLL_HF

CLKOUT_FREQ_DV_HF

CLKFX, CLKFX180

CLKIN_FREQ_FX_LF

CLKOUT_FREQ_FX_LF

CLKIN_FREQ_FX_HF

CLKOUT_FREQ_FX_HF

Table 23: DCM Organization

Device

Columns

DCMs

XC2V40

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

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Active Interconnect Technology

Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores
implementation. Virtex-II Active Interconnect Technology is a fully buffered programmable routing matrix. All routing
resources are segmented to offer the advantages of a hierarchical solution. Virtex-II logic features like CLBs, IOBs, block
RAM, multipliers, and DCMs are all connected to an identical switch matrix for access to global routing resources, as shown
in

Figure 47

Each Virtex-II device can be represented as an array of switch matrixes with logic blocks attached, as illustrated in

Figure 48

Figure 47: Active Interconnect Technology

Figure 48: Routing Resources

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

CLB

18Kb

BRAM

MULT

18 x 18

Switch

Matrix

IOB

Switch

Matrix

DCM

DS031_55_101000

Switch

Matrix

IOB

Switch

Matrix

IOB

Switch

Matrix

IOB

Switch

Matrix

DCM

Switch

Matrix

Switch

Matrix

IOB

Switch

Matrix

CLB

Switch

Matrix

CLB

Switch

Matrix

Switch

Matrix

Switch

Matrix

IOB

Switch

Matrix

CLB

Switch

Matrix

CLB

Switch

Matrix

Switch

Matrix

Switch

Matrix

IOB

Switch

Matrix

CLB

Switch

Matrix

CLB

Switch

Matrix

Switch

Matrix

Switch

Matrix

IOB

Switch

Matrix

CLB

Switch

Matrix

CLB

Switch

Matrix

Switch

Matrix

SelectRAM

Multiplier

DS031_34_110300

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DS031-2 (v3.1) October 14, 2003

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Module 2 of 4

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Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an

incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.

Hierarchical Routing Resources

Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical rout-
ing channels between each switch matrix.

As shown in

Figure 49

, Virtex-II has fully buffered program-

mable interconnections, with a number of resources
counted between any two adjacent switch matrix rows or
columns. Fanout has minimal impact on the performance of
each net.

The long lines are bidirectional wires that distribute
signals across the device. Vertical and horizontal long
lines span the full height and width of the device.

The hex lines route signals to every third or sixth block
away in all four directions. Organized in a staggered
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the endpoints
or at the midpoint (three blocks from the source).

The double lines route signals to every first or second
block away in all four directions. Organized in a
staggered pattern, double lines can be driven only at
their endpoints. Double-line signals can be accessed
either at the endpoints or at the midpoint (one block
from the source).

The direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.

The fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.

Dedicated Routing

In addition to the global and local routing resources, dedi-
cated signals are available.

There are eight global clock nets per quadrant (see

Global Clock Multiplexer Buffers

Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row. (See

3-State Buffers

Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
output signals vertically to the adjacent slice. (See

CLB/Slice Configurations

Figure 49: Hierarchical Routing Resources

24 Horizontal Long Lines
24 Vertical Long Lines

120 Horizontal Hex Lines
120 Vertical Hex Lines

40 Horizontal Double Lines
40 Vertical Double Lines

16 Direct Connections
(total in all four directions)

8 Fast Connects

DS031_60_110200

VirtexTM-II Platform FPGAs: Detailed Description

DS031-2 (v3.1) October 14, 2003

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Product Specification

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One dedicated SOP chain per slice row (two per CLB
row) propagate ORCY output logic signals horizontally
to the adjacent slice. (See

Sum of Products

One dedicated shift-chain per CLB connects the output
of LUTs in shift-register mode to the input of the next
LUT in shift-register mode (vertically) inside the CLB.
(See

Shift Registers, page 16

Creating a Design

Creating Virtex-II designs is easy with Xilinx Integrated Syn-
thesis Environment (ISE) development systems, which sup-
port advanced design capabilities, including ProActive
Timing Closure, integrated logic analysis, and the fastest
place and route runtimes in the industry. ISE solutions
enable designers to get the performance they need, quickly
and easily.

As a result of the ongoing cooperative development efforts
between Xilinx and EDA Alliance partners, designers can
take advantage of the benefits provided by EDA technolo-
gies in the programmable logic design process. Xilinx devel-
opment systems are available in a number of easy to use
configurations, collectively known as the ISE Series.

ISE Alliance

The ISE Alliance solution is designed to plug and play within
an existing design environment. Built using industry standard
data formats and netlists, these stable, flexible products
enable Alliance EDA partners to deliver their best design
automation capabilities to Xilinx customers, along with the
time to market benefits of ProActive Timing Closure.

ISE Foundation

The ISE Foundation solution delivers the benefits of true
HDL-based design in a seamlessly integrated design envi-
ronment. An intuitive project navigator, as well as powerful
HDL design and two HDL synthesis tools, ensure that
high-quality results are achieved quickly and easily. The ISE
Foundation product includes:

State Diagram entry using Xilinx StateCAD

Automatic HDL Testbench generation using Xilinx
HDLBencher

HDL Simulation using ModelSim XE

Design Flow

Virtex-II design flow proceeds as follows:

Design Entry

Synthesis

Implementation

Verification

Most programmable logic designers iterate through these
steps several times in the process of completing a design.

Design Entry

All Xilinx ISE development systems support the mainstream
EDA design entry capabilities, ranging from schematic
design to advanced HDL design methodologies. Given the
high densities of the Virtex-II family, designs are created
most efficiently using HDLs. To further improve their time to
market, many Xilinx customers employ incremental, modu-
lar, and Intellectual Property (IP) design techniques. When
properly used, these techniques further accelerate the logic
design process.

To enable designers to leverage existing investments in
EDA tools, and to ensure high performance design flows,
Xilinx jointly develops tools with leading EDA vendors,
including:

Aldec

Cadence

Exemplar

Mentor Graphics

Model Technology

Synopsys

Synplicity

Complete information on Alliance Series partners and their
associated design flows is available at

www.xilinx.com

the Xilinx Alliance Series web page.

The ISE Foundation product offers schematic entry and
HDL design capabilities as part of an integrated design
solution - enabling one-stop shopping. These capabilities
are powerful, easy to use, and they support the full portfolio
of Xilinx programmable logic devices. HDL design capabil-
ities include a color-coded HDL editor with integrated lan-
guage templates, state diagram entry, and Core generation
capabilities.

Synthesis

The ISE Alliance product is engineered to support
advanced design flows with the industry's best synthesis
tools. Advanced design methodologies include:

Physical Synthesis

Incremental synthesis

RTL floorplanning

Direct physical mapping

The ISE Foundation product seamlessly integrates synthesis
capabilities purchased directly from Exemplar, Synopsys, and
Synplicity. In addition, it includes the capabilities of Xilinx
Synthesis Technology.

A benefit of having two seamlessly integrated synthesis
engines within an ISE design flow is the ability to apply alter-
native sets of optimization techniques on designs, helping to
ensure that designers can meet even the toughest timing
requirements.

VirtexTM-II Platform FPGAs: Detailed Description

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Design Implementation

The ISE Series development systems include Xilinx tim-
ing-driven implementation tools, frequently called "place
and route" or "fitting" software. This robust suite of tools
enables the creation of an intuitive, flexible, tightly inte-
grated design flow that efficiently bridges "logical" and
"physical" design domains. This simplifies the task of defin-
ing a design, including its behavior, timing requirements,
and optional layout (or floorplanning), as well as simplifying
the task of analyzing reports generated during the imple-
mentation process.

The Virtex-II implementation process is comprised of Syn-
thesis, translation, mapping, place and route, and configu-
ration file generation. While the tools can be run individually,
many designers choose to run the entire implementation
process with the click of a button. To assist those who prefer
to script their design flows, Xilinx provides Xflow, an auto-
mated single command line process.

Design Verification

In addition to conventional design verification using static
timing analysis or simulation techniques, Xilinx offers pow-
erful in-circuit debugging techniques using ChipScope ILA
(Integrated Logic Analysis). The reconfigurable nature of
Xilinx FPGAs means that designs can be verified in real
time without the need for extensive sets of software simula-
tion vectors.

For simulation, the system extracts post-layout timing infor-
mation from the design database, and back-annotates this
information into the netlist for use by the simulator. The back
annotation features a variety of patented Xilinx techniques,
resulting in the industry's most powerful simulation flows.
Alternatively, timing-critical portions of a design can be ver-
ified using the Xilinx static timing analyzer or a third party
static timing analysis tool like Synopsys Prime TimeTM, by
exporting timing data in the STAMP data format.

For in-circuit debugging, ChipScope ILA enables designers
to analyze the real-time behavior of a device while operating
at full system speeds. Logic analysis commands and cap-
tured data are transferred between the ChipScope software
and ILA cores within the Virtex-II FPGA, using industry
standard JTAG protocols. These JTAG transactions are
driven over an optional download cable (MultiLINX or
JTAG), connecting the Virtex device in the target system to
a PC or workstation.

ChipScope ILA was designed to look and feel like a logic
analyzer, making it easy to begin debugging a design imme-
diately. Modifications to the desired logic analysis can be
downloaded directly into the system in a matter of minutes.

Other Unique Features of Virtex-II Design Flow

Xilinx design flows feature a number of unique capabilities.
Among these are efficient incremental HDL design flows; a
robust capability that is enabled by Xilinx exclusive hierar-
chical floorplanning capabilities. Another powerful design

capability only available in the Xilinx design flow is "Modular
Design", part of the Xilinx suite of team design tools, which
enables autonomous design, implementation, and verifica-
tion of design modules.

Incremental Synthesis

Xilinx unique hierarchical floorplanning capabilities enable
designers to create a programmable logic design by isolating
design changes within one hierarchical "logic block", and
perform synthesis, verification and implementation pro-
cesses on that specific logic block. By preserving the logic in
unchanged portions of a design, Xilinx incremental design
makes the high-density design process more efficient.

Xilinx hierarchical floorplanning capabilities can be speci-
fied using the high-level floorplanner or a preferred RTL
floorplanner (see the Xilinx web site for a list of supported
EDA partners). When used in conjunction with one of the
EDA partners' floorplanners, higher performance results
can be achieved, as many synthesis tools use this more
predictable detailed physical implementation information to
establish more aggressive and accurate timing estimates
when performing their logic optimizations.

Modular Design

Xilinx innovative modular design capabilities take the incre-
mental design process one step further by enabling the
designer to delegate responsibility for completing the
design, synthesis, verification, and implementation of a hier-
archical "logic block" to an arbitrary number of designers -
assigning a specific region within the target FPGA for exclu-
sive use by each of the team members.

This team design capability enables an autonomous
approach to design modules, changing the hand-off point to
the lead designer or integrator from "my module works in
simulation" to "my module works in the FPGA". This unique
design methodology also leverages the Xilinx hierarchical
floorplanning capabilities and enables the Xilinx (or EDA
partner) floorplanner to manage the efficient implementa-
tion of very high-density FPGAs.

Configuration

Virtex-II devices are configured by loading application spe-
cific configuration data into the internal configuration mem-
ory. Configuration is carried out using a subset of the device
pins, some of which are dedicated, while others can be
re-used as general purpose inputs and outputs once config-
uration is complete.

Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1 and M0 are dedicated pins. An additional pin,
HSWAP_EN is used in conjunction with the mode pins to
select whether user I/O pins have pull-ups during configura-
tion. By default, HSWAP_EN is tied High (internal pull-up)
which shuts off the pull-ups on the user I/O pins during con-
figuration. When HSWAP_EN is tied Low, user I/Os have

VirtexTM-II Platform FPGAs: Detailed Description

DS031-2 (v3.1) October 14, 2003

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Product Specification

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pull-ups during configuration. Other dedicated pins are
CCLK (the configuration clock pin), DONE, PROG_B, and
the boundary-scan pins: TDI, TDO, TMS, and TCK.
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or an input accepting
an externally generated clock. The configuration pins and
boundary scan pins are independent of the V

CCO

. The aux-

iliary power supply (V

CCAUX

) of 3.3V is used for these pins.

All configuration pins are LVTTL 12 mA. (See

Virtex-II DC

Characteristics

in Module 3.)

A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.

Configuration Modes

Virtex-II supports the following five configuration modes:

Slave-serial mode

Master-serial mode

Slave SelectMAP mode

Master SelectMAP mode

Boundary-Scan mode (IEEE 1532/IEEE 1149)

A detailed description of configuration modes is provided in
the Virtex-II User Guide.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.

Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the falling
edge of CCLK.

Slave-serial mode is selected by applying <111> to the
mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.

Master-Serial Mode

In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II FPGA device that drives the configuration clock
on the CCLK pin to a Xilinx Serial PROM which in turn feeds
bit-serial data to the DIN input. The FPGA accepts this data
on each rising CCLK edge. After the FPGA has been

loaded, the data for the next device in a daisy-chain is pre-
sented on the DOUT pin after the falling CCLK edge.

The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration.

Slave SelectMAP Mode

The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II FPGA device with
a BUSY flag controlling the flow of data. An external data
source provides a byte stream, CCLK, an active Low Chip
Select (CS_B) signal and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback opera-
tion.

After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the per-
sist option.

Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, RDWR_B, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
deasserting the CS_B pin of each device in turn and writing
the appropriate data.

Master SelectMAP Mode

This mode is a master version of the SelectMAP mode. The
device is configured byte-wide on a CCLK supplied by the
Virtex-II FPGA device. Timing is similar to the Slave Serial-
MAP mode except that CCLK is supplied by the Virtex-II
FPGA.

Boundary-Scan (JTAG, IEEE 1532) Mode

In boundary-scan mode, dedicated pins are used for config-
uring the Virtex-II device. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). Virtex-II
device configuration using Boundary scan is compliant with
IEEE 1149.1-1993 standard and the new IEEE 1532 stan-
dard for In-System Configurable (ISC) devices. The IEEE
1532 standard is backward compliant with the IEEE
1149.1-1993 TAP and state machine. The IEEE Standard
1532 for In-System Configurable (ISC) devices is intended
to be programmed, reprogrammed, or tested on the board
via a physical and logical protocol.

Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.

VirtexTM-II Platform FPGAs: Detailed Description

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Module 2 of 4

Product Specification

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Table 25

lists the total number of bits required to configure

each device.

Configuration Sequence

The configuration of Virtex-II devices is a three-phase pro-
cess after Power On Reset or POR. POR occurs when
V

CCINT

is greater than 1.2V, V

CCAUX

is greater than 2.5V,

and V

CCO

(bank 4) is greater than 1.5V. Once the POR volt-

ages have been reached, the three-phase process begins.

First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.

Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II FPGA device while the configuration memory is

being cleared. Extending the time that the pin is Low causes
the configuration sequencer to wait. Thus, configuration is
delayed by preventing entry into the phase where data is
loaded.

The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.

The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.

The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.

Readback

In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan mode.

Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Platform FPGA User Guide.

Table 24: Virtex-II Configuration Mode Pin Settings

Configuration Mode

(1)

CCLK Direction

Data Width

Serial D

OUT

(2)

Master Serial

Out

Yes

Slave Serial

Yes

Master SelectMAP

Out

Slave SelectMAP

Boundary Scan

N/A

Notes:
1.

The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pullups are used.

Daisy chaining is possible only in modes where Serial D

OUT

is used. For example, in SelectMAP modes, the first device does NOT

support daisy chaining of downstream devices.

Table 25: Virtex-II Bitstream Lengths

Device

# of Configuration Bits

XC2V40

360,096

XC2V80

635,296

XC2V250

1,697,184

XC2V500

2,761,888

XC2V1000

4,082,592

XC2V1500

5,659,296

XC2V2000

7,492,000

XC2V3000

10,494,368

XC2V4000

15,659,936

XC2V6000

21,849,504

XC2V8000

29,063,072

VirtexTM-II Platform FPGAs: Detailed Description

DS031-2 (v3.1) October 14, 2003

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Module 2 of 4

Product Specification

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Bitstream Encryption

Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.

The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V

BATT

pin, when the

device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.

A detailed description of how to use bitstream encryption is
provided in the Virtex-II Platform FPGA User Guide. For
devices that support this feature, please contact your sales
representative for specific ordering part number.

Partial Reconfiguration

Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration "frame" of the bitstream (device size depen-
dent).

Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.

Revision History

This section records the change history for this module of the data sheet.

Date

Version

Revision

11/07/00

1.0

Early access draft.

12/06/00

1.1

Initial release.

01/15/01

1.2

Added values to the tables in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

sections.

01/25/01

1.3

The data sheet was divided into four modules (per the current style standard). A note was
added to

Table 1

04/02/01

1.5

Under

Input/Output Individual Options

, the range of values for optional pull-up and

pull-down resistors was changed to 10 - 60 K

from 50 - 100 K.

Skipped v1.4 to sync up modules. Reverted to traditional double-column format.

07/30/01

1.6

Added Table 6

Changed definition of multiply and divide integer ranges under

Digital Clock Manager

(DCM)

Made numerous minor edits throughout this module.

10/02/01

1.7

Updated descriptions under

Digitally Controlled Impedance (DCI)

Global Clock

Multiplexer Buffers

Digital Clock Manager (DCM)

, and

Creating a Design

10/12/01

1.8

Made clarifying edits under

Digital Clock Manager (DCM)

11/29/01

1.9

Changed bitstream lengths for each device in

Table 25

07/16/02

2.0

Updated compatible input standards listed in Table 6.

09/26/02

2.1

Changed number of resources available to the XC2V40 device in

Table 12

Clarified Power On Reset information under

Configuration Sequence

12/06/02

2.1.1

Cosmetic edits.

05/07/03

2.1.2

Added qualification note to

Figure 13, page 11

Corrected sentence in section

Input/Output Individual Options, page 4

, to read "The

optional weak-keeper circuit is connected to each user I/O pad."

Corrected typographical errors in

Table 3

for names of HSTL_[x]_DCI_18 standards.

VirtexTM-II Platform FPGAs: Detailed Description

DS031-2 (v3.1) October 14, 2003

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Module 2 of 4

Product Specification

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Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

VirtexTM-II Platform FPGAs: Introduction and Overview
(Module 1)

VirtexTM-II Platform FPGAs: Detailed Description
(Module 2)

VirtexTM-II Platform FPGAs: DC and Switching
Characteristics (Module 3)

VirtexTM-II Platform FPGAs: Pinout Information
(Module 4)

06/19/03

2.2

Removed Compatible Output Standards and Compatible Input Standards tables.

Added new

Table 5

Summary of Voltage Supply Requirements for All Input and

Output Standards

. This table replaces deleted I/O standards tables.

Added section

Rules for Combining I/O Standards in the Same Bank, page 6

08/01/03

3.0

All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

10/14/03

3.1

Added section

Local Clocking, page 30

Table 1, page 1

Added SSTL18_I and SSTL18_II.

Corrected names of 1.8V HSTL_I-IV standards to "HSTL_I-IV_18".

Corrected Input V

REF

for HSTL_III-IV_18 from 1.08V to 1.1V.

Changed "N/A" to "N/R" (no requirement).

Table 2, page 2

Changed "N/A" to "N/R" (no requirement).

Table 3, page 2

Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI,
LVDS_25_DCI, and LVDSEXT_25_DCI.

Corrected Input V

REF

for HSTL_III-IV_18 from 1.08V to 1.1V.

Sections

Slave-Serial Mode

and

Master-Serial Mode, page 37

: Changed "rising" to

"falling" edge with respect to DOUT.

Added verbiage to section

Bitstream Encryption, page 39

: "For devices that support

this feature, please contact your sales representative for specific ordering part
number."

Date

Version

Revision

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS031-3 (v3.1) October 14, 2003

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Product Specification

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Virtex-II Electrical Characteristics

Virtex-II devices are provided in -6, -5, and -4 speed grades,
with -6 having the highest performance.

Virtex-II DC and AC characteristics are specified for both
commercial and industrial grades. Except the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -4 speed
grade industrial device are the same as for a -4 speed grade

commercial device). However, only selected speed grades
and/or devices might be available in the industrial range.

All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parame-
ters included are common to popular designs and typical
applications. Contact Xilinx for design considerations
requiring more detailed information.

All specifications are subject to change without notice.

Virtex-II DC Characteristics

VirtexTM-II Platform FPGAs:
DC

and

Switching

Characteristics

DS031-3 (v3.1) October 14, 2003

Product Specification

Table 1: Absolute Maximum Ratings

Symbol

Description

(1)

Units

CCINT

Internal supply voltage relative to GND

0.5 to 1.65

CCAUX

Auxiliary supply voltage relative to GND

0.5 to 4.0

CCO

Output drivers supply voltage relative to GND

0.5 to 4.0

BATT

Key memory battery backup supply

0.5 to 4.0

REF

Input reference voltage

0.5 to V

CCO

+ 0.5

(3)

Input voltage relative to GND (user and dedicated I/Os)

0.5 to V

CCO

+ 0.5

Voltage applied to 3-state output (user and dedicated I/Os)

0.5 to 4.0

STG

Storage temperature (ambient)

65 to +150

°C

SOL

Maximum soldering temperature

(2)

+220

°C

Maximum junction temperature

(2)

+125

°C

Notes:
1.

Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

For soldering guidelines and thermal considerations, see the

Device Packaging

information on the Xilinx website.

Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the
device is not PCI compliant.

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Table 2: Recommended Operating Conditions

Symbol

Description

Min

Max

Units

CCINT

Internal supply voltage relative to GND, T

= 0

°C to +85°C

Commercial

1.425

1.575

Internal supply voltage relative to GND, T

= 40

°C to +100°C

Industrial

1.425

1.575

CCAUX

Auxiliary supply voltage relative to GND, T

= 0

°C to +85°C

Commercial

3.135

3.465

Auxiliary supply voltage relative to GND, T

= 40

°C to +100°C

Industrial

3.135

3.465

CCO

Supply voltage relative to GND, T

= 0

°C to +85°C

Commercial

1.2

3.6

Supply voltage relative to GND, T

= 40

°C to +100°C

Industrial

1.2

3.6

BATT

Battery voltage relative to GND, T

= 0

°C to +85°C

Commercial

1.0

3.6

Battery voltage relative to GND, T

= 40

°C to +100°C

Industrial

1.0

3.6

Notes:
1.

If battery is not used, do not connect V

BATT

Recommended maximum voltage droop for V

CCAUX

is 10 mV/ms.

The thresholds for Power On Reset are V

CCINT

> 1.2V, V

CCAUX

> 2.5V, and V

CCO

(Bank 4) > 1.5 V.

Limit the noise at the power supply to be within 200 mV peak-to-peak.

For power bypassing guidelines, see XAPP623 at

www.xilinx.com

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Device

Min

Max

Units

DRINT

Data retention V

CCINT

voltage

All

1.2

DRI

Data retention V

CCAUX

voltage

All

2.5

REF

current per bank

All

+10

µA

Input leakage current

All

+10

µA

Input capacitance

All

RPU

Pad pull-up (when selected) @ V

= 0 V, V

CCO

= 3.3 V (sample tested)

All

Note 1

250

µA

RPD

Pad pull-down (when selected) @ V

= 3.6 V (sample tested)

All

Note 1

250

µA

BATT

Battery supply current

All

100

Notes:
1.

Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device operation. The
actual current consumed depends on the power-on ramp
rate of the power supply.

The V

CCINT

, V

CCAUX

, and V

CCO

power supplies shall each

ramp on no faster than 200

µs and no slower than 50 ms.

Ramp on is defined as: 0 V

to minimum supply voltages.

Table 5

shows the minimum current required by Virtex-II

devices for proper power on and configuration.

Power supplies can be turned on in any sequence.

If any V

CCO

bank powers up before V

CCAUX

, then each bank

draws up to 300 mA, worst case, until the V

CCAUX

powers

(1)

. This does not harm the device. If the current is limited

to the minimum value above, or larger, the device powers on
properly after all three supplies have passed through their
power on reset threshold voltages.

Once initialized and configured, use the power calculator to
estimate current drain on these supplies.

Notes:
1.

The 300 mA is transient current (peak); it eventually
disappears even if V

CCAUX

does not power up.

Table 4: Quiescent Supply Current

Symbol

Description

Device

Min

Typical

Max

Units

CCINTQ

Quiescent V

CCINT

supply current

XC2V40
XC2V80

XC2V250
XC2V500

XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000

50
50
65
80

100
125
150
200
225
250
300

TBD

125
150
200
250
350
400
500
650
800

1100

CCOQ

Quiescent V

CCO

supply current

(1,2)

XC2V40
XC2V80

XC2V250
XC2V500

XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000

1
1
1
1
1
2
2
2
2
2
2

TBD

2
2
2
2
4
4
4
4
4
4

CCAUXQ

Quiescent V

CCAUX

supply current

(1,2)

XC2V40
XC2V80

XC2V250
XC2V500

XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000

10
10
10
10
10
15
15
20
20
25
25

TBD

25
25
25
25
50
50
75
75

100
100

Notes:
1.

With no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.

If DCI or differential signaling is used, more accurate values can be obtained by using the Power Estimator or XPOWERTM.

Data are retained even if V

CCO

drops to 0 V.

Values specified for quiescent supply current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial
Grade values by 1.25.

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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General Power Supply Requirements

Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note

XAPP623

for detailed infor-

mation on power distribution system design.

CCAUX

powers critical resources in the FPGA. Thus,

CCAUX

is especially susceptible to power supply noise.

Changes in V

CCAUX

voltage outside of 200 mV peak to peak

should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-

tion are provided in Xilinx Answer Record 13756, available
at

www.support.xilinx.com

CCAUX

can share a power plane with 3.3V V

CCO

, but only if

CCO

does not have excessive noise. Using simultaneously

switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to

XAPP689

"Managing Ground Bounce in Large FPGAs," to determine
the number of simultaneously switching outputs allowed per
bank at the package level.

DC Input and Output Levels

Values for V

and V

are recommended input voltages.

Values for I

and I

are guaranteed over the recom-

mended operating conditions at the V

and V

test

points. Only selected standards are tested. These are cho-

sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V

CCO

with

the respective V

and V

voltage levels shown. Other

standards are sample tested.

Table 5: Minimum Power On Current Required for Virtex-II Devices

Device (mA)

XC2V40, XC2V80,

XC2V250, XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

CCINTMIN

200

250

350

400

500

650

800

1100

CCAUXMIN

100

CCOMIN

100

Notes:
1.

Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.

CCOMIN

values listed here apply to the entire device (all banks).

Table 6: DC Input and Output Levels

Input/Output

Standard

V, Min

V, Max

V, Min

V, Max

V, Min

LVTTL

(1)

0.5

0.8

2.0

3.6

0.4

2.4

LVCMOS33

0.5

0.8

2.0

3.6

0.4

CCO

0.4

LVCMOS25

0.5

0.7

1.7

2.7

0.4

CCO

0.4

LVCMOS18

0.5

35% V

CCO

65% V

CCO

1.95

0.4

CCO

0.4

LVCMOS15

0.5

35% V

CCO

65% V

CCO

1.7

0.4

CCO

0.4

PCI33_3

0.5

30% V

CCO

50% V

CCO

+ 0.5

10% V

CCO

90% V

CCO

Note 2

PCI66_3

0.5

30% V

CCO

50% V

CCO

+ 0.5

10% V

CCO

90% V

CCO

Note 2

PCIX

0.5

Note 2

GTLP

0.5

REF

0.1

REF

+ 0.1

CCO

+ 0.5

0.6

n/a

GTL

0.5

REF

0.05

REF

+ 0.05

CCO

+ 0.5

0.4

n/a

HSTL I

0.5

REF

0.1

REF

+ 0.1

CCO

+ 0.5

0.4

CCO

0.4

HSTL II

0.5

REF

0.1

REF

+ 0.1

CCO

+ 0.5

0.4

CCO

0.4

HSTL III

0.5

REF

0.1

REF

+ 0.1

CCO

+ 0.5

0.4

CCO

0.4

HSTL IV

0.5

REF

0.1

REF

+ 0.1

CCO

+ 0.5

0.4

CCO

0.4

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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LDT Differential Signal DC Specifications (LDT_25)

LVDS DC Specifications (LVDS_33 & LVDS_25)

SSTL3 I

0.5

REF

0.2

REF

+ 0.2

CCO

+ 0.5

REF

0.6

REF

+ 0.6

SSTL3 II

0.5

REF

0.2

REF

+ 0.2

CCO

+ 0.5

REF

0.8

REF

+ 0.8

SSTL2 I

0.5

REF

0.15

REF

+ 0.15

CCO

+ 0.5

REF

0.65

REF

+ 0.65

7.6

SSTL2 II

0.5

REF

0.15

REF

+ 0.15

CCO

+ 0.5

REF

0.80

REF

+ 0.80

15.2

AGP

0.5

REF

0.2

REF

+ 0.2

CCO

+ 0.5

10% V

CCO

90% V

CCO

Note 2

Notes:
1.

and V

for lower drive currents are sample tested. The DONE pin is always LVTTL 12 mA.

Tested according to the relevant specifications.

LVTTL and LVCMOS inputs have approximately 100 mV of hysteresis.

Table 6: DC Input and Output Levels (Continued)

Input/Output

Standard

V, Min

V, Max

V, Min

V, Max

V, Min

Table 7: LDT DC Specifications

DC Parameter

Symbol

Conditions

Min

Typ

Max

Units

Differential Output Voltage

= 100

across Q and Q signals

500

600

700

Change in V

Magnitude

Output Common Mode Voltage

OCM

= 100

across Q and Q signals

560

600

640

Change in V

Magnitude

OCM

Input Differential Voltage

200

600

1000

Change in V

Magnitude

Input Common Mode Voltage

ICM

500

600

700

Change in V

ICM

Magnitude

ICM

Table 8: LVDS DC Specifications

DC Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply Voltage

CCO

3.3 or 2.5

Output High Voltage for Q and Q

= 100

across Q and Q signals

1.575

Output Low Voltage for Q and Q

= 100

across Q and Q signals

0.925

Differential Output Voltage (Q Q),

Q = High (Q Q), Q = High

ODIFF

= 100

across Q and Q signals

250

350

400

Output Common-Mode Voltage

OCM

= 100

across Q and Q signals

1.125

1.2

1.375

Differential Input Voltage (Q Q),

Q = High (Q Q), Q = High

IDIFF

Common-mode input voltage = 1.25 V

100

350

N/A

Input Common-Mode Voltage

ICM

Differential input voltage =

±350 mV

0.2

1.25

CCO

0.5

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Extended LVDS DC Specifications

(LVDSEXT_33 & LVDSEXT_25)

LVPECL DC Specifications

These values are valid when driving a 100

differential

load only, i.e., a 100

resistor between the two receiver

pins. The V

levels are 200 mV below standard LVPECL

levels and are compatible with devices tolerant of lower

common-mode ranges.

Table 10

summarizes the DC output

specifications of LVPECL. For more information on using
LVPECL

see the Virtex-II User Guide.

Table 9: Extended LVDS DC Specifications

DC Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply Voltage

CCO

3.3 or 2.5

Output High voltage for Q and Q

= 100

across Q and Q signals

1.785

Output Low voltage for Q and Q

= 100

across Q and Q signals

0.705

Differential output voltage (Q Q),

Q = High (Q Q), Q = High

ODIFF

= 100

across Q and Q signals

440

820

Output common-mode voltage

OCM

= 100

across Q and Q signals

1.125

1.200

1.375

Differential input voltage (Q Q),

Q = High (Q Q), Q = High

IDIFF

Common-mode input voltage = 1.25 V

100

350

N/A

Input common-mode voltage

ICM

Differential input voltage =

±350 mV

0.2

1.25

CCO

0.5

Table 10: LVPECL DC Specifications

DC Parameter

Min

Max

Min

Max

Min

Max

Units

CCO

3.0

3.3

3.6

1.8

2.11

1.92

2.28

2.13

2.41

0.96

1.27

1.06

1.43

1.30

1.57

1.49

2.72

1.49

2.72

1.49

2.72

0.86

2.125

0.86

2.125

0.86

2.125

Differential Input Voltage

0.3

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Virtex-II

Performance Characteristics

This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as

Virtex-II

Switching Characteristics, page 9

(speed files).

Table 11

provides pin-to-pin values (in nanoseconds)

including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.

Table 12

shows internal (register-to-register) performance. Values are reported in MHz.

Table 11: Pin-to-Pin Performance

Description

Device Used & Speed Grade

Pin-to-Pin (with I/O delays)

Units

Basic Functions

16-bit Address Decoder

XC2V1000 -5

6.3

32-bit Address Decoder

XC2V1000 -5

7.7

64-bit Address Decoder

XC2V1000 -5

9.3

4:1 MUX

XC2V1000 -5

5.7

8:1 MUX

XC2V1000 -5

6.5

16:1 MUX

XC2V1000 -5

6.7

32:1 MUX

XC2V1000 -5

8.7

Combinatorial (pad to LUT to pad)

XC2V1000 -5

5.0

Memory

Block RAM

Pad to setup

1.6

Clock to Pad

9.5

Distributed RAM

Pad to setup

XC2V1000 -5

2.7

Clock to Pad

XC2V1000 -5

5.1 (no clk skew)

Table 12: Register-to-Register Performance

Description

Device Used & Speed

Grade

Register-to-Register

Performance

Units

Basic Functions

16-bit Address Decoder

XC2V1000 -5

398

MHz

32-bit Address Decoder

XC2V1000 -5

291

MHz

64-bit Address Decoder

XC2V1000 -5

274

MHz

4:1 MUX

XC2V1000 -5

563

MHz

8:1 MUX

XC2V1000 -5

454

MHz

16:1 MUX

XC2V1000 -5

414

MHz

32:1 MUX

XC2V1000 -5

323

MHz

XC2V1000 -5

613

MHz

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8-bit Adder

XC2V1000 -5

292

MHz

16-bit Adder

XC2V1000 -5

239

MHz

64-bit Adder

XC2V1000 -5

114

MHz

64-bit Counter

XC2V1000 -5

114

MHz

64-bit Accumulator

XC2V1000 -5

110

MHz

Multiplier 18x18 (with Block RAM inputs)

XC2V1000 -5

MHz

Multiplier 18x18 (with Register inputs)

XC2V1000 -5

105

MHz

Memory

Block RAM

Single-Port 4096 x 4 bits

278

MHz

Single-Port 2048 x 9 bits

277

MHz

Single-Port 1024 x 18 bits

270

MHz

Single-Port 512 x 36 bits

253

MHz

Dual-Port A:4096 x 4 bits & B:1024 x 18 bits

257

MHz

Dual-Port A:1024 x 18 bits & B:1024 x 18 bits

259

MHz

Dual-Port A:2048 x 9 bits & B: 512 x 36 bits

250

MHz

Distributed RAM

Single-Port 32 x 8-bit

XC2V1000 -5

387

MHz

Single-Port 64 x 8-bit

XC2V1000 -5

335

MHz

Single-Port 128 x 8-bit

XC2V1000 -5

266

MHz

Dual-Port 16 x 8

XC2V1000 -5

409

MHz

Dual-Port 32 x 8

XC2V1000 -5

311

MHz

Dual-Port 64 x 8

XC2V1000 -5

294

MHz

Shift Registers

128-bit SRL

N/A

MHz

256-bit SRL

N/A

MHz

FIFOs (Async. in Block RAM)

1024 x 18-bit Read

279

MHz

1024 x 18-bit Write

172

MHz

FIFOs (Sync. in SRL)

128 x 8-bit

N/A

MHz

128 x 16-bit

N/A

MHz

Table 12: Register-to-Register Performance (Continued)

Description

Device Used & Speed

Grade

Register-to-Register

Performance

Units

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Virtex-II Switching Characteristics

Switching characteristics in this document are specified on
a per-speed-grade basis and can be designated as
Advance, Preliminary, or Production. Note that

Virtex-II

Performance Characteristics, page 7

are subject to these

guidelines as well. Each designation is defined as follows:

Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.

Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.

Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.

Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.

Table 13

correlates the current status of each

Virtex-II device with a corresponding speed grade designa-
tion.

All specifications are always representative of worst-case
supply voltage and junction temperature conditions.

Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless other-
wise noted, values apply to all Virtex-II devices.

IOB

Input Switching Characteristics

Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in

IOB Input Switching Characteristics

Standard Adjustments, page 11

Table 13: Virtex-II Device Speed Grade Designations

Device

Speed Grade Designations

Advance

Preliminary

Production

XC2V40

-6, -5, -4

XC2V80

-6, -5, -4

XC2V250

-6, -5, -4

XC2V500

-6, -5, -4

XC2V1000

-6, -5, -4

XC2V1500

-6, -5, -4

XC2V2000

-6, -5, -4

XC2V3000

-6, -5, -4

XC2V4000

-6, -5, -4

XC2V6000

-6, -5, -4

XC2V8000

-5, -4

Table 14: IOB Input Switching Characteristics

Speed Grade

Units

Description

Symbol

Device

-6

-5

-4

Propagation Delays

Pad to I output, no delay

IOPI

All

0.69

0.76

0.88

ns, Max

Pad to I output, with delay

IOPID

XC2V40

1.92

2.11

2.43

ns, Max

XC2V80

1.92

2.11

2.43

ns, Max

XC2V250

1.92

2.11

2.43

ns, Max

XC2V500

1.92

2.11

2.43

ns, Max

XC2V1000

1.92

2.11

2.43

ns, Max

XC2V1500

1.92

2.11

2.43

ns, Max

XC2V2000

1.92

2.11

2.43

ns, Max

XC2V3000

1.97

2.16

2.49

ns, Max

XC2V4000

1.97

2.16

2.49

ns, Max

XC2V6000

2.10

2.31

2.66

ns, Max

XC2V8000

2.31

2.66

ns, Max

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Propagation Delays

Pad to output IQ via transparent
latch, no delay

IOPLI

All

0.83

0.91

1.05

ns, Max

Pad to output IQ via transparent
latch, with delay

IOPLID

XC2V40

3.23

3.55

4.09

ns, Max

XC2V80

3.23

3.55

4.09

ns, Max

XC2V250

3.23

3.55

4.09

ns, Max

XC2V500

3.23

3.55

4.09

ns, Max

XC2V1000

3.23

3.55

4.09

ns, Max

XC2V1500

3.23

3.55

4.09

ns, Max

XC2V2000

3.23

3.55

4.09

ns, Max

XC2V3000

3.32

3.65

4.20

ns, Max

XC2V4000

3.32

3.65

4.20

ns, Max

XC2V6000

3.60

3.95

4.55

ns, Max

XC2V8000

3.95

4.55

ns, Max

Clock CLK to output IQ

IOCKIQ

All

0.67

0.77

ns, Max

Setup and Hold Times With Respect to Clock at IOB Input
Register

Pad, no delay

IOPICK

IOICKP

All

0.84/0.36

0.92/0.39

1.06/0.45

ns, Min

Pad, with delay

IOPICKD

IOICKPD

XC2V40

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V80

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V250

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V500

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V1000

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V1500

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V2000

3.24/2.04

3.57/2.24

4.10/2.58

ns, Min

XC2V3000

3.33/2.10

3.67/2.31

4.22/2.66

ns, Min

XC2V4000

3.33/2.10

3.67/2.31

4.22/2.66

ns, Min

XC2V6000

3.61/2.29

3.97/2.52

4.56/2.90

ns, Min

XC2V8000

3.97/2.52

4.56/2.90

ns, Min

ICE input

IOICECK

IOCKICE

All

0.21/ 0.04

0.24/ 0.04

ns, Min

SR input (IFF, synchronous)

IOSRCKI

All

0.27

0.30

0.34

ns, Min

Set/Reset Delays

SR input to IQ (asynchronous)

IOSRIQ

All

1.11

1.22

1.40

ns, Max

GSR to output IQ

GSRQ

All

5.44

5.98

6.88

ns, Max

Notes:
1.

Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see

Table 18

Table 14: IOB Input Switching Characteristics (Continued)

Speed Grade

Units

Description

Symbol

Device

-6

-5

-4

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Product Specification

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IOB Input Switching Characteristics Standard Adjustments

Table 15: IOB Input Switching Characteristics Standard Adjustments

Speed Grade

Description

Symbol

Standard

-6

-5

-4

Units

Data Input Delay Adjustments

Standard-specific data input delay
adjustments

ILVTTL

LVTTL

0.00

ILVCMOS33

LVCMOS33

0.00

ILVCMOS25

LVCMOS25

0.11

0.12

ILVCMOS18

LVCMOS18

0.42

0.43

0.49

ILVCMOS15

LVCMOS15

0.98

1.00

1.15

ILVDS_25

LVDS_25

0.60

0.69

ILVDS_33

LVDS_33

0.60

0.69

ILVPECL_33

LVPECL

0.60

0.69

IPCI33_3

PCI, 33 MHz, 3.3 V

0.00

IPCI66_3

PCI, 66 MHz, 3.3 V

0.00

IPCIX

PCI

X, 133 MHz, 3.3 V

0.00

IGTL

GTL

0.42

0.48

IGTLP

GTLP

0.42

0.48

IHSTL_I

HSTL I

0.42

0.48

IHSTL_II

HSTL II

0.42

0.48

IHSTL_III

HSTL III

0.42

0.48

IHSTL_IV

HSTL IV

0.42

0.48

IHSTL_I_18

HSTL I_18

0.42

0.48

IHSTL_II_18

HSTL II_18

0.42

0.48

IHSTL_III_18

HSTL III_18

0.42

0.48

IHSTL_IV_18

HSTL IV_18

0.42

0.48

ISSTL2_I

SSTL2 I

0.42

0.48

ISSTL2_II

SSTL2 II

0.42

0.48

ISSTL3_I

SSTL3 I

0.35

0.40

ISSTL3_II

SSTL3 II

0.35

0.40

IAGP

AGP

0.35

0.40

ILVDCI_33

LVDCI_33

0.00

ILVDCI_25

LVDCI_25

0.11

0.12

ILVDCI_18

LVDCI_18

0.42

0.43

0.49

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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ILVDCI_15

LVDCI_15

0.98

1.00

1.14

ILVDCI_DV2_33

LVDCI_DV2_33

0.00

ILVDCI_DV2_25

LVDCI_DV2_25

0.11

0.12

ILVDCI_DV2_18

LVDCI_DV2_18

0.42

0.43

0.49

ILVDCI_DV2_15

LVDCI_DV2_15

0.98

1.00

1.14

IGTL_DCI

GTL_DCI

0.42

0.48

IGTLP_DCI

GTLP_DCI

0.42

0.48

IHSTL_I_DCI

HSTL_I_DCI

0.42

0.48

IHSTL_II_DCI

HSTL_II_DCI

0.42

0.48

IHSTL_III_DCI

HSTL_III_DCI

0.42

0.48

IHSTL_IV_DCI

HSTL_IV_DCI

0.42

0.48

IHSTL_I_DCI_18

HSTL_I_DCI_18

0.42

0.48

IHSTL_II_DCI_18

HSTL_II_DCI_18

0.42

0.48

IHSTL_III_DCI_18

HSTL_III_DCI_18

0.42

0.48

IHSTL_IV_DCI_18

HSTL_IV_DCI_18

0.42

0.48

ISSTL2_I_DCI

SSTL2_I_DCI

0.42

0.48

ISSTL2_II_DCI

SSTL2_II_DCI

0.42

0.48

ISSTL3_I_DCI

SSTL3_I_DCI

0.35

0.40

ISSTL3_II_DCI

SSTL3_II_DCI

0.35

0.40

ILDT_25

LDT_25

0.48

0.49

0.56

IULVDS_25

ULVDS_25

0.48

0.49

0.56

Notes:
1.

Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see

Table 18

Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)

Speed Grade

Description

Symbol

Standard

-6

-5

-4

Units

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Module 3 of 4

Product Specification

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IOB Output Switching Characteristics

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in

IOB Output Switching Characteristics Standard Adjustments, page 14

Table 16: IOB Output Switching Characteristics

Speed Grade

Description

Symbol

-6

-5

-4

Units

Propagation Delays

O input to Pad

IOOP

1.43

1.51

1.74

ns, Max

O input to Pad via transparent latch

IOOLP

1.72

1.83

2.11

ns, Max

3-State Delays

T input to Pad high-impedance

(1)

IOTHZ

0.51

0.56

0.64

ns, Max

T input to valid data on Pad

IOTP

1.38

1.45

1.67

ns, Max

T input to Pad high-impedance via transparent
latch

(1)

IOTLPHZ

0.80

0.88

1.01

ns, Max

T input to valid data on Pad via transparent latch

IOTLPON

1.67

1.77

2.04

ns, Max

GTS to Pad high impedance

(1)

GTS

4.73

5.20

5.98

ns, Max

Sequential Delays

Clock CLK to Pad

IOCKP

1.76

1.87

2.15

ns, Max

Clock CLK to Pad high-impedance
(synchronous)

(1)

IOCKHZ

0.95

1.04

1.20

ns, Max

Clock CLK to valid data on Pad (synchronous)

IOCKON

1.82

1.94

2.22

ns, Max

Setup and Hold Times Before/After Clock CLK

O input

IOOCK

IOCKO

0.31/0.08

0.34/0.09

0.39/0.11

ns, Min

OCE input

IOOCECK

IOCKOCE

0.19/0.06

0.21/0.07

0.24/0.08

ns, Min

SR input (OFF)

IOSRCKO

IOCKOSR

0.27/0.05

0.30/0.06

0.34/0.07

ns, Min

State Setup Times, T input

IOTCK

IOCKT

0.28/0.06

0.31/0.07

0.35/0.08

ns, Min

State Setup Times, TCE input

IOTCECK

IOCKTCE

0.19/0.06

0.21/0.07

0.24/0.08

ns, Min

State Setup Times, SR input (TFF)

IOSRCKT

IOCKTSR

0.27/0.05

0.30/0.06

0.34/0.07

ns, Min

Set/Reset Delays

SR input to Pad (asynchronous)

IOSRP

2.41

2.59

2.98

ns, Max

SR input to Pad high-impedance
(asynchronous)

(1)

IOSRHZ

1.52

1.67

1.92

ns, Max

SR input to valid data on Pad (asynchronous)

IOSRON

2.39

2.56

2.95

ns, Max

GSR to Pad

IOGSRQ

5.44

5.98

6.88

ns, Max

Notes:
1.

The 3-state turn-off delays should not be adjusted.

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Product Specification

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IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.

Table 17: IOB Output Switching Characteristics Standard Adjustments

Speed Grade

Description

Symbol

Standard

-6

-5

-4

Units

Output Delay Adjustments

Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)

OLVTTL_S2

LVTTL, Slow, 2 mA

9.42

9.71

10.68

OLVTTL_S4

4 mA

5.77

5.95

6.55

OLVTTL_S6

6 mA

4.11

4.24

4.66

OLVTTL_S8

8 mA

2.87

2.96

3.26

OLVTTL_S12

12 mA

2.32

2.39

2.63

OLVTTL_S16

16 mA

1.70

1.75

1.93

OLVTTL_S24

24 mA

1.26

1.30

1.43

OLVTTL_F2

LVTTL, Fast, 2 mA

6.52

6.72

7.39

OLVTTL_F4

4 mA

2.80

2.88

3.17

OLVTTL_F6

6 mA

1.57

1.62

1.78

OLVTTL_F8

8 mA

0.46

0.48

0.52

OLVTTL_F12

12 mA

0.00

OLVTTL_F16

16 mA

0.13

0.14

0.15

OLVTTL_F24

24 mA

0.22

0.23

0.26

OLVDS_25

LVDS 0.31

0.32

0.36

OLVDS_33

LVDS 0.25

0.26

0.29

OLVDSEXT_25

LVDS 0.18

0.19

0.21

OLVDSEXT_33

LVDS 0.17

0.18

0.19

OLDT_25

LDT 0.20

0.21

0.23

OBLVDS_25

BLVDS

0.67

0.69

0.76

OULVDS_25

ULVDS

0.20

0.21

0.23

OLVPECL_33

LVPECL

0.29

0.30

0.33

OPCI33_3

PCI, 33 MHz, 3.3 V

1.15

1.19

1.31

OPCI66_3

PCI, 66 MHz, 3.3 V

0.01

OPCIX

PCIX, 133 MHz, 3.3 V

0.01

OGTL

GTL

0.31

0.32

0.36

OGTLP

GTLP

0.17

0.18

0.20

OHSTL_I

HSTL I

0.26

0.27

0.29

OHSTL_II

HSTL II

0.15

0.16

0.17

OHSTL_III

HSTL III

0.17

0.19

OHSTL_IV

HSTL IV

0.40

0.41

0.45

OHSTL_I_18

HSTL I_18

0.03

0.04

OHSTL_II_18

HSTL II_18

0.17

0.18

0.20

OHSTL_III_18

HSTL III_18

0.16

0.18

OHSTL_IV_18

HSTL IV_18

0.39

0.40

0.44

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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OSSTL2_I

SSTL2 I

0.21

0.22

0.24

OSSTL2_II

SSTL2 II

0.15

0.16

0.18

OSSTL3_I

SSTL3 I

0.29

0.30

0.33

OSSTL3_II

SSTL3 II

0.05

OAGP

AGP

0.27

0.28

0.31

OLVCMOS33_S2

LVCMOS33, Slow, 2 mA

7.67

7.91

8.70

OLVCMOS33_S4

4 mA

4.37

4.50

4.95

OLVCMOS33_S6

6 mA

3.34

3.44

3.78

OLVCMOS33_S8

8 mA

2.29

2.36

2.60

OLVCMOS33_S12

12 mA

1.91

1.97

2.16

OLVCMOS33_S16

16 mA

1.24

1.27

1.40

OLVCMOS33_S24

24 mA

1.18

1.22

1.34

OLVCMOS33_F2

LVCMOS33, Fast, 2 mA

5.82

6.00

6.60

OLVCMOS33_F4

4 mA

2.48

2.55

2.81

OLVCMOS33_F6

6 mA

1.28

1.31

1.45

OLVCMOS33_F8

8 mA

0.48

0.49

0.54

OLVCMOS33_F12

12 mA

0.27

0.28

0.31

OLVCMOS33_F16

16 mA

0.14

0.15

OLVCMOS33_F24

24 mA

0.21

0.23

OLVCMOS25_S2

LVCMOS25, Slow, 2 mA

9.11

9.39

10.33

OLVCMOS25_S4

4 mA

5.00

5.16

5.67

OLVCMOS25_S6

6 mA

4.53

4.67

5.13

OLVCMOS25_S8

8 mA

3.86

3.98

4.38

OLVCMOS25_S12

12 mA

2.84

2.93

3.22

OLVCMOS25_S16

16 mA

2.36

2.43

2.67

OLVCMOS25_S24

24 mA

2.00

2.06

2.27

OLVCMOS25_F2

LVCMOS25, Fast, 2 mA

4.06

4.18

4.60

OLVCMOS25_F4

4 mA

1.15

1.18

1.30

OLVCMOS25_F6

6 mA

0.72

0.74

0.81

OLVCMOS25_F8

8 mA

0.33

0.34

0.37

OLVCMOS25_F12

12 mA

0.02

0.03

OLVCMOS25_F16

16 mA

0.18

0.19

0.21

OLVCMOS25_F24

24 mA

0.35

0.36

0.40

OLVCMOS18_S2

LVCMOS18, Slow, 2 mA

15.62

16.10

17.71

OLVCMOS18_S4

4 mA

10.20

10.51

11.57

OLVCMOS18_S6

6 mA

7.52

7.75

8.53

OLVCMOS18_S8

8 mA

6.87

7.08

7.78

OLVCMOS18_S12

12 mA

5.54

5.71

6.28

OLVCMOS18_S16

16 mA

5.31

5.47

6.02

OLVCMOS18_F2

LVCMOS18, Fast, 2 mA

5.55

5.72

6.30

Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)

Speed Grade

Description

Symbol

Standard

-6

-5

-4

Units

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Product Specification

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OLVCMOS18_F4

4 mA

1.89

1.95

2.15

OLVCMOS18_F6

6 mA

0.83

0.85

0.94

OLVCMOS18_F8

8 mA

0.70

0.72

0.80

OLVCMOS18_F12

12 mA

0.26

0.27

0.30

OLVCMOS18_F16

16 mA

0.23

0.26

OLVCMOS15_S2

LVCMOS15, Slow, 2 mA

18.96

19.55

21.50

OLVCMOS15_S4

4 mA

12.77

13.17

14.48

OLVCMOS15_S6

6 mA

12.05

12.42

13.66

OLVCMOS15_S8

8 mA

9.75

10.06

11.06

OLVCMOS15_S12

12 mA

9.04

9.32

10.25

OLVCMOS15_S16

16 mA

8.21

8.46

9.31

OLVCMOS15_F2

LVCMOS15, Fast, 2 mA

5.09

5.25

5.78

OLVCMOS15_F4

4 mA

2.01

2.07

2.27

OLVCMOS15_F6

6 mA

1.46

1.51

1.66

OLVCMOS15_F8

8 mA

0.93

0.96

1.05

OLVCMOS15_F12

12 mA

0.74

0.77

0.84

OLVCMOS15_F16

16 mA

0.67

0.69

0.75

OLVDCI_33

LVDCI_33

0.74

0.77

0.84

OLVDCI_25

LVDCI_25

0.78

0.80

0.88

OLVDCI_18

LVDCI_18

0.84

0.87

0.95

OLVDCI_15

LVDCI_15

1.82

1.88

2.06

OLVDCI_DV2_33

LVDCI_DV2_33

0.12

0.13

OLVDCI_DV2_25

LVDCI_DV2_25

0.03

OLVDCI_DV2_18

LVDCI_DV2_18

0.42

0.43

0.48

OLVDCI_DV2_15

LVDCI_DV2_15

1.20

1.23

1.36

OGTL_DCI

GTL_DCI

0.31

0.32

0.35

OGTLP_DCI

GTLP_DCI

0.15

0.16

0.17

OHSTL_I_DCI

HSTL_I_DCI

0.23

0.26

OHSTL_II_DCI

HSTL_II_DCI

0.06

0.07

OHSTL_III_DCI

HSTL_III_DCI

0.17

0.18

0.20

OHSTL_IV_DCI

HSTL_IV_DCI

0.46

0.47

0.52

OHSTL_I_DCI_18

HSTL_I_DCI_18

0.05

0.06

OHSTL_II_DCI_18

HSTL_II_DCI_18

0.03

OHSTL_III_DCI_18

HSTL_III_DCI_18

0.14

0.16

OHSTL_IV_DCI_18

HSTL_IV_DCI_18

0.41

0.42

0.47

OSSTL2_I_DCI

SSTL2_I_DCI

0.12

0.13

0.14

OSSTL2_II_DCI

SSTL2_II_DCI

0.10

0.11

OSSTL3_I_DCI

SSTL3_I_DCI

0.15

0.16

0.17

OSSTL3_II_DCI

SSTL3_II_DCI

0.08

0.09

Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)

Speed Grade

Description

Symbol

Standard

-6

-5

-4

Units

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Product Specification

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I/O

Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 18

shows the test setup parameters used for measur-

ing Input standard adjustments (see

Table 15, page 11

Output Delay Measurements

Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pf) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See

Virtex-II Platform FPGA User Guide

for details.)

The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in

Figure 1

Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at

http://support.xil-

inx.com/support/sw_ibis.htm

.) Parameters V

REF

, R

REF

, and V

MEAS

fully describe the test conditions for each

I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:

Simulate the output driver of choice into the generalized
test setup, using values from

Table 19

Record the time to V

MEAS

Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.

Record the time to V

MEAS

Compare the results of steps 2 and 4. The increase or
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(

Table 17

) to yield the actual worst-case propagation

delay (clock-to-input) of the PCB trace.

Table 18: Input Delay Measurement Methodology

Standard

(1)

MEAS

(3,4)

REF

(2,4)

LVTTL

3.0

1.4

LVCMOS33

3.3

1.65

LVCMOS25

2.5

1.25

LVCMOS18

1.8

0.9

LVCMOS15

1.5

0.75

PCI33_3

Per PCI Specification

PCI66_3

Per PCI Specification

PCI-X

Per PCI-X Specification

GTL

REF

0.2

REF

+ 0.2

REF

0.80

GTLP

REF

0.2

REF

+ 0.2

REF

1.0

HSTL Class I

REF

0.5

REF

+ 0.5

REF

0.75

HSTL Class II

REF

0.5

REF

+ 0.5

REF

0.75

HSTL Class III

REF

0.5

REF

+ 0.5

REF

0.90

HSTL Class IV

REF

0.5

REF

+ 0.5

REF

0.90

SSTL3
Class I & II

REF

1.00

REF

+ 1.00

REF

1.5

SSTL2
Class I & II

REF

0.75

REF

+ 0.75

REF

1.25

AGP-2X

REF

(0.2

CCO

)

REF

(0.2

CCO

)

REF

Per

AGP

Spec

LVDS25

1.2 0.125

1.2 + 0.125

1.2

LVDS33

1.2 0.125

1.2 + 0.125

1.2

LVDSEXT25

1.2 0.125

1.2 + 0.125

1.2

LVDSEXT33

1.2 0.125

1.2 + 0.125

1.2

ULVDS25

0.6 0.125

0.6 + 0.125

0.6

LDT25

0.6 0.125

0.6 + 0.125

0.6

LVPECL

1.6 0.3

1.6 + 0.3

1.6

Notes:
1.

Input waveform switches between V

and V

Measurements are made at typical, minimum, and maximum V

REF

values. Reported delays reflect worst case of these measurements.
V

REF

values listed are typical. See

Virtex-II Platform FPGA User

Guide

for min/max specifications.

Input voltage level from which measurement starts.

Note that this is an input voltage reference that bears no relation to
the V

REF

/ V

MEAS

parameters found in IBIS models and/or noted in

Figure 1

Figure 1: Generalized Test Setup

REF

MEAS

(voltage level at which
delay measurement is taken)

REF

(probe capacitance)

FPGA Output

ds083-3_06a_092503

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Product Specification

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Table 19: Output Delay Measurement Methodology

Standard

REF

(ohms)

REF

(1)

(pF)

MEAS

(V)

REF

(V)

LVTTL (all)

1.4

LVCMOS33

1.65

LVCMOS25

1.25

LVCMOS18

0.9

LVCMOS15

0.75

PCI33_3 - rising edge

0.94

PCI33_3 - falling edge

2.03

3.3

PCI66_3 - rising edge

0.94

PCI66_3 - falling edge

2.03

3.3

PCI-X - rising edge

0.94

PCI-X - falling edge

2.03

3.3

GTL

0.8

1.2

GTLP

1.0

1.5

HSTL Class I

REF

0.75

HSTL Class II

REF

0.75

HSTL Class III

0.9

1.5

HSTL Class IV

0.9

1.5

HSTL18 Class I

REF

0.9

HSTL18 Class II

REF

0.9

HSTL18 Class III

1.1

1.8

HSTL18 Class IV

1.1

1.8

SSTL3 Class I

REF

1.5

SSTL3 Class II

REF

1.5

SSTL2 Class I

REF

1.25

SSTL2 Class II

REF

1.25

SSTL18 Class I

REF

0.9

SSTL18 Class II

REF

0.9

AGP-2X - rising edge

0.94

AGP-2X - falling edge

2.03

3.3

LVDS25

REF

1.2

LVDSEXT25

REF

1.2

LVDS33

REF

1.2

LVDSEXT33

REF

1.2

BLVDS

1.2

LDT_25

REF

0.6

LVPECL25

1.23

LVDCI33

1.65

LVDCI25

1.25

LVDCI18

0.9

LVDCI15

0.75

HSTL DCI Class I

REF

0.75

HSTL DCI C0lass II

REF

0.75

HSTL DCI Class III

0.9

1.5

HSTL DCI Class IV

0.9

1.5

HSTL18 DCI Class I

REF

0.9

HSTL18 DCI Class II

REF

0.9

HSTL18 DCI Class III

1.1

1.8

HSTL18 DCI Class IV

1.1

1.8

SSTL3 DCI Class I

REF

1.5

SSTL3 DCI Class II

REF

1.5

SSTL2 DCI Class I

REF

1.25

SSTL2 DCI Class II

REF

1.25

SSTL18 DCI Class I

REF

0.9

SSTL18 DCI Class II

REF

0.9

GTL DCI

0.8

1.2

GTLP DCI

1.0

1.5

Notes:
1.

REF

is the capacitance of the probe, nominally 0 pF.

Table 19: Output Delay Measurement Methodology

Standard

REF

(ohms)

REF

(1)

(pF)

MEAS

(V)

REF

(V)

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Module 3 of 4

Product Specification

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Clock Distribution Switching Characteristics

CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used (see

Figure 16

in Module 2). The values listed below

are worst-case. Precise values are provided by the timing analyzer.

Table 20: Clock Distribution Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Global Clock Buffer I input to O output

GIO

0.47

0.52

0.59

ns, Max

Table 21: CLB Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Combinatorial Delays

4-input function: F/G inputs to X/Y outputs

ILO

0.35

0.39

0.44

ns, Max

5-input function: F/G inputs to F5 output

IF5

0.57

0.63

0.72

ns, Max

5-input function: F/G inputs to X output

IF5X

0.76

0.83

0.95

ns, Max

FXINA or FXINB inputs to Y output via MUXFX

IFXY

0.36

0.39

0.45

ns, Max

FXINA input to FX output via MUXFX

INAFX

0.26

0.28

0.32

ns, Max

FXINB input to FX output via MUXFX

INBFX

0.26

0.28

0.32

ns, Max

SOPIN input to SOPOUT output via ORCY

SOPSOP

0.35

0.38

0.44

ns, Max

Incremental delay routing through transparent latch
to XQ/YQ outputs

IFNCTL

0.41

0.45

0.51

ns, Max

Sequential Delays

FF Clock CLK to XQ/YQ outputs

CKO

0.45

0.50

0.57

ns, Max

Latch Clock CLK to XQ/YQ outputs

CKLO

0.54

0.59

0.68

ns, Max

Setup and Hold Times Before/After Clock CLK

BX/BY inputs

DICK

CKDI

0.30/0.07

0.33/0.08

0.37/0.09

ns, Min

DY inputs

DYCK

CKDY

0.30/0.07

0.33/0.08

0.37/0.09

ns, Min

DX inputs

DXCK

CKDX

0.30/0.07

0.33/0.08

0.37/0.09

ns, Min

CE input

CECK

CKCE

0.19/0.06

0.21/0.07

0.24/0.08

ns, Min

SR/BY inputs (synchronous)

SRCK/

SCKR

0.21/0.02

0.23/0.03

0.26/0.03

ns, Min

Clock CLK

Minimum Pulse Width, High

0.61

0.67

0.77

ns, Min

Minimum Pulse Width, Low

0.61

0.67

0.77

ns, Min

Set/Reset

Minimum Pulse Width, SR/BY inputs

RPW

0.61

0.67

0.77

ns, Min

Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)

1.06

1.17

1.34

ns, Max

Toggle Frequency (MHz) (for export control)

TOG

820

750

650

MHz

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Module 3 of 4

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CLB Distributed RAM Switching Characteristics

CLB Shift Register Switching Characteristics

Table 22: CLB Distributed RAM Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Sequential Delays

Clock CLK to X/Y outputs (WE active) in 16 x 1 mode

SHCKO16

1.63

1.79

2.05

ns, Max

Clock CLK to X/Y outputs (WE active) in 32 x 1 mode

SHCKO32

1.97

2.17

2.49

ns, Max

Clock CLK to F5 output

SHCKOF5

1.77

1.94

2.23

ns, Max

Setup and Hold Times Before/After Clock CLK

BX/BY data inputs (DIN)

0.53/0.09

0.58/0.10

0.67/0.11

ns, Min

F/G address inputs

0.40/ 0.00

0.44/ 0.00

0.50/ 0.00

ns, Min

SR input (WS)

WES

WEH

0.42/0.01

0.46/0.01

0.53/0.01

ns, Min

Clock CLK

Minimum Pulse Width, High

WPH

0.57

0.63

0.72

ns, Min

Minimum Pulse Width, Low

WPL

0.57

0.63

0.72

ns, Min

Minimum clock period to meet address write cycle time

1.14

1.25

1.44

ns, Min

Table 23: CLB Shift Register Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Sequential Delays

Clock CLK to X/Y outputs

REG

2.31

2.54

2.92

ns, Max

Clock CLK to X/Y outputs

REG32

2.65

2.92

3.35

ns, Max

Clock CLK to XB output via MC15 LUT output

REGXB

2.23

2.46

2.82

ns, Max

Clock CLK to YB output via MC15 LUT output

REGYB

2.18

2.40

2.75

ns, Max

Clock CLK to Shiftout

CKSH

1.92

2.11

2.43

ns, Max

Clock CLK to F5 output

REGF5

2.45

2.69

3.09

ns, Max

Setup and Hold Times Before/After Clock CLK

BX/BY data inputs (DIN)

SRLDS

SRLDH

0.53/0.07

0.58/0.08

0.67/0.09

ns, Min

SR input (WS)

WSS

WSH

0.19/0.06

0.21/0.07

0.24/0.08

ns, Min

Clock CLK

Minimum Pulse Width, High

SRPH

0.57

0.63

0.72

ns, Min

Minimum Pulse Width, Low

SRPL

0.57

0.63

0.72

ns, Min

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Module 3 of 4

Product Specification

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Multiplier Switching Characteristics

Table 24: Multiplier Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Propagation Delay to Output Pin

Input to Pin 35

MULT_P35

4.66

8.50

10.36

ns, Max

Input to Pin 34

MULT_P34

4.57

8.33

10.15

ns, Max

Input to Pin 33

MULT_P33

4.47

8.16

9.95

ns, Max

Input to Pin 32

MULT_P32

4.37

7.99

9.74

ns, Max

Input to Pin 31

MULT_P31

4.28

7.82

9.53

ns, Max

Input to Pin 30

MULT_P30

4.18

7.65

9.33

ns, Max

Input to Pin 29

MULT_P29

4.08

7.48

9.12

ns, Max

Input to Pin 28

MULT_P28

3.99

7.31

8.91

ns, Max

Input to Pin 27

MULT_P27

3.89

7.14

8.70

ns, Max

Input to Pin 26

MULT_P26

3.79

6.97

8.50

ns, Max

Input to Pin 25

MULT_P25

3.69

6.80

8.29

ns, Max

Input to Pin 24

MULT_P24

3.60

6.63

8.08

ns, Max

Input to Pin 23

MULT_P23

3.50

6.46

7.88

ns, Max

Input to Pin 22

MULT_P22

3.40

6.29

7.67

ns, Max

Input to Pin 21

MULT_P21

3.31

6.12

7.46

ns, Max

Input to Pin 20

MULT_P20

3.21

5.95

7.26

ns, Max

Input to Pin 19

MULT_P19

3.11

5.78

7.05

ns, Max

Input to Pin 18

MULT_P18

3.02

5.61

6.84

ns, Max

Input to Pin 17

MULT_P17

2.92

5.44

6.63

ns, Max

Input to Pin 16

MULT_P16

2.82

5.27

6.43

ns, Max

Input to Pin 15

MULT_P15

2.72

5.10

6.22

ns, Max

Input to Pin 14

MULT_P14

2.63

4.93

6.01

ns, Max

Input to Pin 13

MULT_P13

2.53

4.76

5.81

ns, Max

Input to Pin 12

MULT_P12

2.43

4.59

5.60

ns, Max

Input to Pin 11

MULT_P11

2.34

4.42

5.39

ns, Max

Input to Pin 10

MULT_P10

2.24

4.25

5.19

ns, Max

Input to Pin 9

MULT_P9

2.14

4.08

4.98

ns, Max

Input to Pin 8

MULT_P8

2.05

3.91

4.77

ns, Max

Input to Pin 7

MULT_P7

1.95

3.74

4.56

ns, Max

Input to Pin 6

MULT_P6

1.85

3.57

4.36

ns, Max

Input to Pin 5

MULT_P5

1.75

3.40

4.15

ns, Max

Input to Pin 4

MULT_P4

1.66

3.23

3.94

ns, Max

Input to Pin 3

MULT_P3

1.56

3.06

3.74

ns, Max

Input to Pin 2

MULT_P2

1.46

2.89

3.53

ns, Max

Input to Pin 1

MULT_P1

1.37

2.72

3.32

ns, Max

Input to Pin 0

MULT_P0

1.27

2.55

3.12

ns, Max

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Module 3 of 4

Product Specification

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Table 25: Pipelined Multiplier Switching Characteristics

Description

Symbol

Speed Grade

Units

-6 -5 -4

Setup and Hold Times Before/After Clock

Data Inputs

MULIDCK

MULCKID

3.00/ 0.00

3.45/ 0.00

3.89/ 0.00

ns, Max

Clock Enable

MULIDCK_CE

MULCKID_CE

0.72/ 0.00

0.80/ 0.00

0.86/ 0.00

ns, Max

Reset

MULIDCK_RST

MULCKID_RST

0.72/ 0.00

0.80/ 0.00

0.86/ 0.00

ns, Max

Clock to Output Pin

Clock to Pin 35

MULTCK_P35

3.05

6.91

8.12

ns, Max

Clock to Pin 34

MULTCK_P34

2.95

6.75

7.93

ns, Max

Clock to Pin 33

MULTCK_P33

2.85

6.59

7.74

ns, Max

Clock to Pin 32

MULTCK_P32

2.76

6.43

7.56

ns, Max

Clock to Pin 31

MULTCK_P31

2.66

6.27

7.37

ns, Max

Clock to Pin 30

MULTCK_P30

2.56

6.11

7.19

ns, Max

Clock to Pin 29

MULTCK_P29

2.47

5.95

7.00

ns, Max

Clock to Pin 28

MULTCK_P28

2.37

5.79

6.81

ns, Max

Clock to Pin 27

MULTCK_P27

2.27

5.63

6.63

ns, Max

Clock to Pin 26

MULTCK_P26

2.17

5.47

6.44

ns, Max

Clock to Pin 25

MULTCK_P25

2.08

5.31

6.26

ns, Max

Clock to Pin 24

MULTCK_P24

1.98

5.15

6.07

ns, Max

Clock to Pin 23

MULTCK_P23

1.88

4.99

5.88

ns, Max

Clock to Pin 22

MULTCK_P22

1.79

4.83

5.70

ns, Max

Clock to Pin 21

MULTCK_P21

1.69

4.67

5.51

ns, Max

Clock to Pin 20

MULTCK_P20

1.59

4.51

5.33

ns, Max

Clock to Pin 19

MULTCK_P19

1.50

4.35

5.14

ns, Max

Clock to Pin 18

MULTCK_P18

1.40

4.19

4.95

ns, Max

Clock to Pin 17

MULTCK_P17

1.30

4.03

4.77

ns, Max

Clock to Pin 16

MULTCK_P16

1.20

3.87

4.58

ns, Max

Clock to Pin 15

MULTCK_P15

1.11

3.71

4.40

ns, Max

Clock to Pin 14

MULTCK_P14

1.01

3.55

4.21

ns, Max

Clock to Pin 13

MULTCK_P13

0.91

3.39

4.02

ns, Max

Clock to Pin 12

MULTCK_P12

0.91

3.23

3.84

ns, Max

Clock to Pin 11

MULTCK_P11

0.91

3.07

3.65

ns, Max

Clock to Pin 10

MULTCK_P10

0.91

2.91

3.47

ns, Max

Clock to Pin 9

MULTCK_P9

0.91

2.75

3.28

ns, Max

Clock to Pin 8

MULTCK_P8

0.91

2.59

3.09

ns, Max

Clock to Pin 7

MULTCK_P7

0.91

2.43

2.91

ns, Max

Clock to Pin 6

MULTCK_P6

0.91

2.27

2.72

ns, Max

Clock to Pin 5

MULTCK_P5

0.91

2.11

2.54

ns, Max

Clock to Pin 4

MULTCK_P4

0.91

1.95

2.35

ns, Max

Clock to Pin 3

MULTCK_P3

0.91

1.79

2.16

ns, Max

Clock to Pin 2

MULTCK_P2

0.91

1.63

1.98

ns, Max

Clock to Pin 1

MULTCK_P1

0.91

1.47

1.79

ns, Max

Clock to Pin 0

MULTCK_P0

0.91

1.31

1.61

ns, Max

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

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Module 3 of 4

Product Specification

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Enhanced Multiplier Switching Characteristics

Table 26

and

Table 27

provide timing information for enhanced Virtex-II multiplier blocks, available in stepping revisions of

Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales
representative.

Table 26: Enhanced Multiplier Switching Characteristics

Description

Symbol

Speed Grade

Units

-6 -5 -4

Propagation Delay to Output Pin

Input to Pin 35

MULT1_P35

4.66

5.14

5.91

ns, Max

Input to Pin 34

MULT1_P34

4.57

5.03

5.79

ns, Max

Input to Pin 33

MULT1_P33

4.47

4.93

5.66

ns, Max

Input to Pin 32

MULT1_P32

4.37

4.82

5.54

ns, Max

Input to Pin 31

MULT1_P31

4.28

4.71

5.42

ns, Max

Input to Pin 30

MULT1_P30

4.18

4.61

5.29

ns, Max

Input to Pin 29

MULT1_P29

4.08

4.50

5.17

ns, Max

Input to Pin 28

MULT1_P28

3.99

4.39

5.05

ns, Max

Input to Pin 27

MULT1_P27

3.89

4.28

4.92

ns, Max

Input to Pin 26

MULT1_P26

3.79

4.18

4.80

ns, Max

Input to Pin 25

MULT1_P25

3.69

4.07

4.68

ns, Max

Input to Pin 24

MULT1_P24

3.60

3.96

4.56

ns, Max

Input to Pin 23

MULT1_P23

3.50

3.86

4.43

ns, Max

Input to Pin 22

MULT1_P22

3.40

3.75

4.31

ns, Max

Input to Pin 21

MULT1_P21

3.31

3.64

4.19

ns, Max

Input to Pin 20

MULT1_P20

3.21

3.54

4.06

ns, Max

Input to Pin 19

MULT1_P19

3.11

3.43

3.94

ns, Max

Input to Pin 18

MULT1_P18

3.02

3.32

3.82

ns, Max

Input to Pin 17

MULT1_P17

2.92

3.21

3.69

ns, Max

Input to Pin 16

MULT1_P16

2.82

3.11

3.57

ns, Max

Input to Pin 15

MULT1_P15

2.72

3.00

3.45

ns, Max

Input to Pin 14

MULT1_P14

2.63

2.89

3.33

ns, Max

Input to Pin 13

MULT1_P13

2.53

2.79

3.20

ns, Max

Input to Pin 12

MULT1_P12

2.43

2.68

3.08

ns, Max

Input to Pin 11

MULT1_P11

2.34

2.57

2.96

ns, Max

Input to Pin 10

MULT1_P10

2.24

2.47

2.83

ns, Max

Input to Pin 9

MULT1_P9

2.14

2.36

2.71

ns, Max

Input to Pin 8

MULT1_P8

2.05

2.25

2.59

ns, Max

Input to Pin 7

MULT1_P7

1.95

2.14

2.46

ns, Max

Input to Pin 6

MULT1_P6

1.85

2.04

2.34

ns, Max

Input to Pin 5

MULT1_P5

1.75

1.93

2.22

ns, Max

Input to Pin 4

MULT1_P4

1.66

1.82

2.10

ns, Max

Input to Pin 3

MULT1_P3

1.56

1.72

1.97

ns, Max

Input to Pin 2

MULT1_P2

1.46

1.61

1.85

ns, Max

Input to Pin 1

MULT1_P1

1.37

1.50

1.73

ns, Max

Input to Pin 0

MULT1_P0

1.27

1.40

1.60

ns, Max

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

DS031-3 (v3.1) October 14, 2003

www.xilinx.com

Module 3 of 4

Product Specification

1-800-255-7778

Table 27: Enhanced Pipelined Multiplier Switching Characteristics

Description

Symbol

Speed Grade

Units

-6 -5 -4

Setup and Hold Times Before/After Clock

Data Inputs

MULIDCK

MULCKID

3.00/0.00

3.45/0.00

3.89/0.00

ns, Max

Clock Enable

MULIDCK_CE

MULCKID_CE

0.72/0.00

0.80/0.00

0.86/0.00

ns, Max

Reset

MULIDCK_RST

MULCKID_RST

0.72/0.00

0.80/0.00

0.86/0.00

ns, Max

Clock to Output Pin

Clock to Pin 35

MULTCK1_P35

3.05

3.25

3.74

ns, Max

Clock to Pin 34

MULTCK1_P34

2.95

3.14

3.61

ns, Max

Clock to Pin 33

MULTCK1_P33

2.85

3.04

3.49

ns, Max

Clock to Pin 32

MULTCK1_P32

2.76

2.93

3.37

ns, Max

Clock to Pin 31

MULTCK1_P31

2.66

2.82

3.25

ns, Max

Clock to Pin 30

MULTCK1_P30

2.56

2.72

3.12

ns, Max

Clock to Pin 29

MULTCK1_P29

2.47

2.61

3.00

ns, Max

Clock to Pin 28

MULTCK1_P28

2.37

2.50

2.88

ns, Max

Clock to Pin 27

MULTCK1_P27

2.27

2.40

2.75

ns, Max

Clock to Pin 26

MULTCK1_P26

2.17

2.29

2.63

ns, Max

Clock to Pin 25

MULTCK1_P25

2.08

2.18

2.51

ns, Max

Clock to Pin 24

MULTCK1_P24

1.98

2.07

2.38

ns, Max

Clock to Pin 23

MULTCK1_P23

1.88

1.97

2.26

ns, Max

Clock to Pin 22

MULTCK1_P22

1.79

1.86

2.14

ns, Max

Clock to Pin 21

MULTCK1_P21

1.69

1.75

2.02

ns, Max

Clock to Pin 20

MULTCK1_P20

1.59

1.65

1.89

ns, Max

Clock to Pin 19

MULTCK1_P19

1.50

1.54

1.77

ns, Max

Clock to Pin 18

MULTCK1_P18

1.40

1.43

1.65

ns, Max

Clock to Pin 17

MULTCK1_P17

1.30

1.33

1.52

ns, Max

Clock to Pin 16

MULTCK1_P16

1.20

1.22

1.40

ns, Max

Clock to Pin 15

MULTCK1_P15

1.11

1.28

ns, Max

Clock to Pin 14

MULTCK1_P14

1.01

1.00

1.15

ns, Max

Clock to Pin 13

MULTCK1_P13

0.91

1.00

1.15

ns, Max

Clock to Pin 12

MULTCK1_P12

0.91

1.00

1.15

ns, Max

Clock to Pin 11

MULTCK1_P11

0.91

1.00

1.15

ns, Max

Clock to Pin 10

MULTCK1_P10

0.91

1.00

1.15

ns, Max

Clock to Pin 9

MULTCK1_P9

0.91

1.00

1.15

ns, Max

Clock to Pin 8

MULTCK1_P8

0.91

1.00

1.15

ns, Max

Clock to Pin 7

MULTCK1_P7

0.91

1.00

1.15

ns, Max

Clock to Pin 6

MULTCK1_P6

0.91

1.00

1.15

ns, Max

Clock to Pin 5

MULTCK1_P5

0.91

1.00

1.15

ns, Max

Clock to Pin 4

MULTCK1_P4

0.91

1.00

1.15

ns, Max

Clock to Pin 3

MULTCK1_P3

0.91

1.00

1.15

ns, Max

Clock to Pin 2

MULTCK1_P2

0.91

1.00

1.15

ns, Max

Clock to Pin 1

MULTCK1_P1

0.91

1.00

1.15

ns, Max

Clock to Pin 0

MULTCK1_P0

0.91

1.00

1.15

ns, Max

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Block SelectRAM Switching Characteristics

TBUF Switching Characteristics

JTAG Test Access Port Switching Characteristics

Table 28: Block SelectRAM Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Sequential Delays

Clock CLK to DOUT output

BCKO

2.10

2.31

2.65

ns, Max

Setup and Hold Times Before Clock CLK

ADDR inputs

BACK

BCKA

0.29/ 0.00

0.32/ 0.00

0.36/ 0.00

ns, Min

DIN inputs

BDCK

BCKD

0.29/ 0.00

0.32/ 0.00

0.36/ 0.00

ns, Min

EN input

BECK

BCKE

0.95/0.46

1.04/0.50

1.20/0.58

ns, Min

RST input

BRCK

BCKR

1.31/0.71

1.44/0.78

1.65/0.90

ns, Min

WEN input

BWCK

BCKW

0.57/0.19

0.63/0.21

0.72/0.25

ns, Min

Clock CLK

Minimum Pulse Width, High

BPWH

1.17

1.29

1.48

ns, Min

Minimum Pulse Width, Low

BPWL

1.17

1.29

1.48

ns, Min

Table 29: TBUF Switching Characteristics

Description

Symbol

Speed Grade

Units

-6

-5

-4

Combinatorial Delays

IN input to OUT output

0.45

0.50

0.58

ns, Max

TRI input to OUT output high-impedance

OFF

0.44

0.48

0.55

ns, Max

TRI input to valid data on OUT output

0.44

0.48

0.55

ns, Max

Table 30: JTAG Test Access Port Switching Characteristics

Description

Symbol

Units

TMS and TDI Setup times before TCK

TAPTK

5.5

ns, Min

TMS and TDI Hold times after TCK

TCKTAP

0.0

ns, Min

Output delay from clock TCK to output TDO

TCKTDO

10.0

ns, Max

Maximum TCK clock frequency

TCK

MHz, Max

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Virtex-II Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM

Table 31: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

LVTTL Global Clock Input to Output delay
using Output flip-flop, 12 mA, Fast Slew
Rate, with DCM.

For data output with different standards,
adjust the delays with the values shown in

IOB Output Switching Characteristics
Standard Adjustments, page 14

Global Clock and OFF with DCM

ICKOFDCM

XC2V40

1.10

1.28

1.48

XC2V80

1.10

1.28

1.48

XC2V250

1.10

1.28

1.48

XC2V500

1.10

1.28

1.48

XC2V1000

1.10

1.28

1.48

XC2V1500

1.10

1.28

1.48

XC2V2000

1.10

1.28

1.48

XC2V3000

1.19

1.38

1.59

XC2V4000

1.19

1.38

1.59

XC2V6000

1.64

1.88

2.17

XC2V8000

1.88

2.17

Notes:
1.

Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.

Output timing is measured at 50% V

threshold with test setup shown in

Figure 1

. For other I/O standards, see

Table 19

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Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM

Table 32: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

LVTTL Global Clock Input to Output Delay using
Output flip-flop, 12 mA, Fast Slew Rate, without
DCM.

For data output with different standards, adjust
the delays with the values shown in

IOB Output

Switching Characteristics Standard
Adjustments, page 14

Global Clock and OFF without DCM

ICKOF

XC2V40

3.46

3.58

3.69

XC2V80

3.62

3.58

3.69

XC2V250

3.79

3.88

4.47

XC2V500

3.85

3.88

4.47

XC2V1000

4.02

4.28

4.62

XC2V1500

4.16

4.28

4.62

XC2V2000

4.30

4.43

5.10

XC2V3000

4.49

4.64

5.34

XC2V4000

4.82

4.99

5.74

XC2V6000

5.19

5.38

5.93

XC2V8000

6.09

7.00

Notes:
1.

Output timing is measured at 50% V

threshold with test setup shown in

Figure 1

. For other I/O standards, see

Table 19

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Virtex-II Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.

Global Clock Setup and Hold for LVTTL Standard, With DCM

Table 33: Global Clock Setup and Hold for LVTTL Standard, With DCM

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.

For data input with different
standards, adjust the setup time
delay by the values shown in

IOB

Input Switching
Characteristics Standard
Adjustments, page 11

No Delay

Global Clock and IFF with DCM

PSDCM

PHDCM

XC2V40

1.60/0.90

1.84/0.76

XC2V80

1.60/0.90

1.84/0.76

XC2V250

1.60/0.90

1.84/0.76

XC2V500

1.60/0.90

1.84/0.76

XC2V1000

1.60/0.90

1.84/0.76

XC2V1500

1.60/0.90

1.84/0.76

XC2V2000

1.70/0.90

1.96/0.76

XC2V3000

1.70/0.90

1.96/0.76

XC2V4000

1.70/0.90

1.96/0.76

XC2V6000

1.70/0.90

1.96/0.76

XC2V8000

1.70/0.90

1.96/0.76

Notes:
1.

IFF = Input Flip-Flop or Latch

Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.

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Global Clock Setup and Hold for LVTTL Standard, Without DCM

Table 34: Global Clock Setup and Hold for LVTTL Standard, Without DCM

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.

(2)

For data input with different
standards, adjust the setup time
delay by the values shown in

IOB

Input Switching Characteristics
Standard Adjustments,
page 11

Full Delay

Global Clock and IFF

(1)

without

DCM

PSFD

PHFD

XC2V40

1.92/ 0.00

2.21/ 0.00

XC2V80

2.10/ 0.00

2.21/ 0.00

XC2V250

1.92/ 0.00

2.21/ 0.00

XC2V500

1.92/ 0.00

2.21/ 0.00

XC2V1000

1.92/ 0.00

2.21/ 0.00

XC2V1500

1.92/ 0.00

2.21/ 0.00

XC2V2000

1.92/ 0.00

2.21/ 0.00

XC2V3000

1.92/ 0.00

2.21/ 0.00

XC2V4000

2.00/ 0.00

2.30/ 0.00

XC2V6000

1.92/ 0.50

2.21/ 0.50

XC2V8000

2.38/ 0.00

2.60/ 0.00

Notes:
1.

IFF = Input Flip-Flop or Latch

These values are parametrically measured.

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DCM Timing Parameters

All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values

across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.

Operating Frequency Ranges

Table 35: Operating Frequency Ranges

Description

Symbol

Constraint

Speed Grade

Unit

-6

-5

-4

Output Clocks (Low Frequency Mode)

CLK0, CLK90, CLK180, CLK270

CLKOUT_FREQ_1X_LF_Min

24.00

MHz

CLKOUT_FREQ_1X_LF_Max

230.00

210.00

180.00

MHz

CLK2X, CLK2X180

CLKOUT_FREQ_2X_LF_Min

48.00

MHz

CLKOUT_FREQ_2X_LF_Max

450.00

420.00

360.00

MHz

CLKDV

CLKOUT_FREQ_DV_LF_Min

1.50

MHz

CLKOUT_FREQ_DV_LF_Max

150.00

140.00

120.00

MHz

CLKFX, CLKFX180

CLKOUT_FREQ_FX_LF_Min

24.00

MHz

CLKOUT_FREQ_FX_LF_Max

260.00

240.00

210.00

MHz

Input Clocks (Low Frequency Mode)

CLKIN (using DLL outputs)

(1,3)

CLKIN_FREQ_DLL_LF_Min

24.00

MHz

CLKIN_FREQ_DLL_LF_Max

230.00

210.00

180.00

MHz

CLKIN (using CLKFX outputs)

(2,3)

CLKIN_FREQ_FX_LF_Min

1.00

MHz

CLKIN_FREQ_FX_LF_Max

260.00

240.00

210.00

MHz

PSCLK

PSCLK_FREQ_LF_Min

0.01

MHz

PSCLK_FREQ_LF_Max

450.00

420.00

360.00

MHz

Output Clocks (High Frequency Mode)

CLK0, CLK180

CLKOUT_FREQ_1X_HF_Min

48.00

MHz

CLKOUT_FREQ_1X_HF_Max

450.00

420.00

360.00

MHz

CLKDV

CLKOUT_FREQ_DV_HF_Min

3.00

MHz

CLKOUT_FREQ_DV_HF_Max

300.00

280.00

240.00

MHz

CLKFX, CLKFX180

CLKOUT_FREQ_FX_HF_Min

210.00

MHz

CLKOUT_FREQ_FX_HF_Max

350.00

320.00

270.00

MHz

Input Clocks (High Frequency Mode)

CLKIN (using DLL outputs)

(1,3)

CLKIN_FREQ_DLL_HF_Min

48.00

MHz

CLKIN_FREQ_DLL_HF_Max

450.00

420.00

360.00

MHz

CLKIN (using CLKFX outputs)

(2,3)

CLKIN_FRQ_FX_HF_Min

50.00

MHz

CLKIN_FRQ_FX_HF_Max

350.00

320.00

270.00

MHz

PSCLK

PSCLK_FREQ_HF_Min

0.01

MHz

PSCLK_FREQ_HF_Max

450.00

420.00

360.00

MHz

Notes:
1.

"DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

If both DLL and CLKFX outputs are used, follow the more restrictive specification.

If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.

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Input Clock Tolerances

Table 36: Input Clock Tolerances

Description

Symbol

Constraints

CLKIN

Speed Grade

Units

-6

-5

-4

Min

Max

Min

Max

Min

Max

Input Clock Low/High Pulse Width

PSCLK

PSCLK_PULSE

< 1MHz

25.00

PSCLK and CLKIN

(3)

PSCLK_PULSE and
CLKIN_PULSE

1 10 MHz

25.00

10 25 MHz

10.00

25 50 MHz

5.00

50 100 MHz

3.00

100 150 MHz

2.40

150 200 MHz

2.00

200 250 MHz

1.80

250 300 MHz

1.50

300 350 MHz

1.30

350 400 MHz

1.15

> 400 MHz

1.05

Input Clock Cycle-Cycle Jitter (Low Frequency Mode)

CLKIN (using DLL outputs)

(1)

CLKIN_CYC_JITT_DLL_LF

±300

CLKIN (using CLKFX outputs)

(2)

CLKIN_CYC_JITT_FX_LF

±300

Input Clock Cycle-Cycle Jitter (High Frequency Mode)

CLKIN (using DLL outputs)

(1)

CLKIN_CYC_JITT_DLL_HF

±150

CLKIN (using CLKFX outputs)

(2)

CLKIN_CYC_JITT_FX_HF

±150

Input Clock Period Jitter (Low Frequency Mode)

CLKIN (using DLL outputs)

(1)

CLKIN_PER_JITT_DLL_LF

±1

CLKIN (using CLKFX outputs)

(2)

CLKIN_PER_JITT_FX_LF

±1

Input Clock Period Jitter (High Frequency Mode)

CLKIN (using DLL outputs)

(1)

CLKIN_PER_JITT_DLL_HF

±1

CLKIN (using CLKFX outputs)

(2)

CLKIN_PER_JITT_FX_HF

±1

Feedback Clock Path Delay Variation

CLKFB off-chip feedback

CLKFB_DELAY_VAR_EXT

±1

Notes:
1.

""DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

If both DLL and CLKFX outputs are used, follow the more restrictive specification.

If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within ±5% (45/55 to 55/45).

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Output Clock Jitter

Output Clock Phase Alignment

Table 37: Output Clock Jitter

Description

Symbol

Constraints

Speed Grade

Units

-6

-5

-4

Clock Synthesis Period Jitter

CLK0

CLKOUT_PER_JITT_0

±100

CLK90

CLKOUT_PER_JITT_90

±150

CLK180

CLKOUT_PER_JITT_180

±150

CLK270

CLKOUT_PER_JITT_270

±150

CLK2X, CLK2X180

CLKOUT_PER_JITT_2X

±200

CLKDV (integer division)

CLKOUT_PER_JITT_DV1

±150

CLKDV (non-integer division)

CLKOUT_PER_JITT_DV2

±300

CLKFX, CLKFX180

CLKOUT_PER_JITT_FX

Note 1

Notes:
1.

Values for this parameter are available at

www.xilinx.com

Table 38: Output Clock Phase Alignment

Description

Symbol

Constraints

Speed Grade

Units

-6

-5

-4

Phase Offset Between CLKIN and CLKFB

CLKIN/CLKFB

CLKIN_CLKFB_PHASE

±50

Phase Offset Between Any DCM Outputs

All CLK outputs

CLKOUT_PHASE

±140

Duty Cycle Precision

DLL outputs

(1)

CLKOUT_DUTY_CYCLE_DLL

(2)

±150

CLKFX outputs

CLKOUT_DUTY_CYCLE_FX

±100

Notes:
1.

"DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.

Specification also applies to PSCLK.

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Miscellaneous Timing Parameters

Frequency Synthesis

Parameter Cross Reference

Table 39: Miscellaneous Timing Parameters

Description

Symbol

Constraints

CLKIN

Speed Grade

Units

-6

-5

-4

Time Required to Achieve LOCK

Using DLL outputs

(1)

LOCK_DLL

LOCK_DLL_60

> 60MHz

20.0

µs

LOCK_DLL_50_60

50 - 60 MHz

25.0

µs

LOCK_DLL_40_50

40 - 50 MHz

50.0

µs

LOCK_DLL_30_40

30 - 40 MHz

90.0

µs

LOCK_DLL_24_30

24 - 30 MHz

120.0

µs

Using CLKFX outputs

LOCK_FX_MIN

10.0

LOCK_FX_MAX

10.0

Additional lock time with
fine-phase shifting

LOCK_DLL_FINE_SHIFT

50.0

µs

Fine-Phase Shifting

Absolute shifting range

FINE_SHIFT_RANGE

10.0

Delay Lines

Tap delay resolution

DCM_TAP_MIN

30.0

DCM_TAP_MAX

60.0

Notes:
1.

"DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

Specification also applies to PSCLK.

Table 40: Frequency Synthesis

Attribute

Min

Max

CLKFX_MULTIPLY

CLKFX_DIVIDE

Table 41: Parameter Cross Reference

Libraries Guide

Data Sheet

DLL_CLKOUT_{MIN|MAX}_LF

CLKOUT_FREQ_{1X|2X|DV}_LF

DFS_CLKOUT_{MIN|MAX}_LF

CLKOUT_FREQ_FX_LF

DLL_CLKIN_{MIN|MAX}_LF

CLKIN_FREQ_DLL_LF

DFS_CLKIN_{MIN|MAX}_LF

CLKIN_FREQ_FX_LF

DLL_CLKOUT_{MIN|MAX}_HF

CLKOUT_FREQ_{1X|DV}_HF

DFS_CLKOUT_{MIN|MAX}_HF

CLKOUT_FREQ_FX_HF

DLL_CLKIN_{MIN|MAX}_HF

CLKIN_FREQ_DLL_HF

DFS_CLKIN_{MIN|MAX}_HF

CLKIN_FREQ_FX_HF

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Source-Synchronous Switching Characteristics

The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II source-synchronous
transmitter and receiver data-valid windows.

Table 42: Duty Cycle Distortion and Clock-Tree Skew

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

Duty Cycle Distortion

(1)

DCD_CLK0

All

140

DCD_CLK180

All

Clock Tree Skew

(2)

CKSKEW

XC2V40

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

100

110

XC2V3000

100

110

XC2V4000

400

450

XC2V6000

500

550

XC2V8000

600

650

Notes:
1.

These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused
by asymmetrical rise/fall times.
T

DCD_CLK0

applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.

DCD_CLK180

applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element

in the I/O.

This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.

Table 43: Package Skew

Description

Symbol

Device/Package

Value

Units

Package Skew

(1)

PKGSKEW

XC2V1000 / FF896

130

XC2V3000 / FF1152

115

XC2V3000 / BF957

130

XC2V4000 / FF1152

130

XC2V4000 / FF1517

200

XC2V4000 / BF957

140

XC2V6000 / FF1152

XC2V6000 / FF1517

105

XC2V6000 / BF957

105

Notes:
1.

These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).

Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.

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Table 44: Sample Window

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

Sampling Error at Receiver Pins

(1)

SAMP

XC2V40

500

550

XC2V80

500

550

XC2V250

500

550

XC2V500

500

550

XC2V1000

500

550

XC2V1500

500

550

XC2V2000

500

550

XC2V3000

500

550

XC2V4000

500

550

XC2V6000

500

550

XC2V8000

500

550

Notes:
1.

This parameter indicates the total sampling error of Virtex-II

DDR input registers across voltage, temperature, and process. The

characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T

DCD_CLK180

- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.

Table 45: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration

Description

Symbol

Device

Speed Grade

Units

-6

-5

-4

Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.

For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in

IOB Input Switching

Characteristics Standard Adjustments, page 11

No Delay

Global Clock and IFF with DCM

PSDCM

PHDCM

XC2V40

0.2/0.5

XC2V80

0.2/0.5

XC2V250

0.2/0.5

XC2V500

0.2/0.5

XC2V1000

0.2/0.5

XC2V1500

0.2/0.5

XC2V2000

0.2/0.5

XC2V3000

0.2/0.5

0.2/0.6

XC2V4000

0.2/0.5

0.2/0.6

XC2V6000

0.2/0.5

0.2/0.6

XC2V8000

0.2/0.6

0.2/0.7

Notes:
1.

IFF = Input Flip-Flop

The timing values were measured using the fine-phase adjustment feature of the DCM.

The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Source Synchronous Timing Budgets

This section describes how to use the parameters provided in the

Source-Synchronous Switching Characteristics

section to develop system-specific timing budgets. The following analysis provides information necessary for determining
Virtex-II contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol
Interference or PCB skew.

Virtex-II Transmitter Data-Valid Window (T

)

is the minimum aggregate valid data period for a

source-synchronous data bus at the pins of the device and
is calculated as follows:

= Data Period - [Jitter

(1)

+ Duty Cycle Distortion

(2)

TCKSKEW

(3)

+ TPKGSKEW

(4)

]

Notes:
1.

Jitter values and accumulation methodology to be provided in
a future release of this document. The absolute period jitter
values found in the

DCM Timing Parameters

section of the

particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.

This value depends on the clocking methodology used. See
Note1 for

Table 42

This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.

These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.

Virtex-II Receiver Data-Valid Window (R

)

is the required minimum aggregate valid data period for

a source-synchronous data bus at the pins of the device
and is calculated as follows:

= [TSAMP

(1)

+ TCKSKEW

(2)

+ TPKGSKEW

(3)

]

Notes:
1.

This parameter indicates the total sampling error of Virtex-II

DDR input registers across voltage, temperature, and
process. The characterization methodology uses the DCM to
capture the DDR input registers' edges of operation. These
measurements include:
-

CLK0 and CLK180 DCM jitter in a quiet system

Worst-case duty-cycle distortion

DCM accuracy (phase offset)

DCM phase shift resolution.

These measurements do not include package or clock tree
skew.

This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.

These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.

Revision History

This section records the change history for this module of the data sheet.

Date

Version

Revision

11/07/00

1.0

Early access draft.

12/06/00

1.1

Initial release.

01/15/01

1.2

Added values to the tables in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

sections.

01/25/01

1.3

The data sheet was divided into four modules (per the current style standard).

Updated values in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

tables.

Table 18, "Delay Measurement Methodology"

04/23/01

1.5

Updated values in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

tables.

Added T

REG32

symbol to

Table 23

Skipped v1.4 to sync with other modules. Reverted to traditional double-column
format.

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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07/30/01

1.6

Updated values in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

tables.

Added values to the

Virtex-II Pin-to-Pin Output Parameter Guidelines

and

Virtex-II

Pin-to-Pin Input Parameter Guidelines

tables.

Added

Frequency Synthesis

table.

10/02/01

1.7

Updated values in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

tables.

Updated the speed grade designations used in data sheets, and added

Table 13

which shows the current speed grade designation for each device.

10/05/01

1.8

Corrected the speed grade designation for the XC2V1000 device in

Table 13

10/12/01

1.9

Updated values in the

Virtex-II Performance Characteristics

and

Virtex-II

Switching Characteristics

tables.

11/28/01

2.0

Updated values in

Table 3

Table 4

Table 5

Virtex-II Performance Characteristics

and

Virtex-II Switching Characteristics

tables.

01/03/02

2.1

Updated values in

Virtex-II Performance Characteristics

and

Virtex-II Switching

Characteristics

tables, based on values extracted from speedsfile version 1.96.

Changed the speed grade designation for the XC2V6000 device in

Table 13

07/16/02

2.2

Updated values in

Table 4

, "

Quiescent Supply Current

Updated values in

Virtex-II Performance Characteristics

and

Virtex-II Switching

Characteristics

tables, based on values extracted from speedsfile version 1.111.

Added

Enhanced Multiplier Switching Characteristics

section.

Added footnote to

Table 34

, "

Global Clock Setup and Hold for LVTTL Standard,

Without DCM

Added

Source-Synchronous Switching Characteristics

section.

09/26/02

2.3

Removed mention of MIL-M-38510/605 specification.

Added footnotes to

Table 2

and

Table 6

12/06/02

2.4

Revised SSTL2 values in

Table 6

to match the latest JEDEC specification.

Added footnote regarding V

PCI compliance to

Table 1

Added footnote regarding

CLKOUT_DUTY_CYCLE_DLL

Table 38

05/07/03

2.5

Updated values in

Virtex-II Performance Characteristics

and

Virtex-II Switching

Characteristics

tables, based on values extracted from speedsfile version 1.114.

Table 4

Quiescent Supply Current

, and

Table 5

Minimum Power On Current

Required for Virtex-II Devices

: Added parameters for XC2V8000 device.

Table 16

IOB Output Switching Characteristics

: Changed parameter designator

IOTON

to T

IOTP

Table 26

Enhanced Multiplier Switching Characteristics

: Corrected all parameter

designators from T

MULT_P[nn]

to T

MULT1_P[nn]

in order to correspond with designators

used in speedsfile.

Table 27

Enhanced Pipelined Multiplier Switching Characteristics

: Corrected all

parameter designators from T

MULTCK_P[nn]

to T

MULTCK1_P[nn]

in order to correspond

with designators used in speedsfile.

Removed old Table 19, Standard Capacitive Loads.

Added Figure 1, page 17, showing test configuration for measuring I/O standard
adjustments.

06/19/03

2.5.1

Removed footnotes in

Table 31

and

Table 33

that stated DCM jitter was included in the

measurements.

Date

Version

Revision

VirtexTM-II Platform FPGAs: DC and Switching Characteristics

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Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

VirtexTM-II Platform FPGAs: Introduction and Overview
(Module 1)

VirtexTM-II Platform FPGAs: Detailed Description
(Module 2)

VirtexTM-II Platform FPGAs: DC and Switching
Characteristics (Module 3)

VirtexTM-II Platform FPGAs: Pinout Information
(Module 4)

08/01/03

3.0

Table 13

: All Virtex-II devices and speed grades now Production.

Updated values in

Virtex-II Performance Characteristics

and

Virtex-II Switching

Characteristics

tables, based on values extracted from speedsfile version 1.116.

Table 31

and

Table 32

: Revised test setup footnote to refer to

Figure 1

. Previously

specified a capacitive load parameter.

Figure 1: Added note to figure regarding termination resistors.

10/14/03

3.1

Table 1

: Changed T

description from "Operating junction temperature" to "Maximum

junction temperature".

In section

General Power Supply Requirements

, replaced reference to Answer

Record 11713 with reference to

XAPP689

regarding handling of simultaneously

switching outputs (SSO).

In section

I/O Standard Adjustment Measurement Methodology

Table 18

renamed

Input Delay Measurement Methodology

. Added footnotes.

Added new

Table 19

Output Delay Measurement Methodology

Replaced

Figure 1

Generalized Test Setup

, with new drawing.

Revised and extended text describing output delay measurement procedure.

Table 42

Table 44

, and

Table 45

: All Source-Synchronous parameters for all devices

now available in these tables.

XC2V8000 is no longer offered in the -6 speed grade. The following tables containing
parameters or other references to this device/grade combination were corrected
accordingly:

Table 13

Table 14

Table 31

Table 32

Table 33

Table 34

Table 42

Table 44

, and

Table 45

Table 36

: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing

Footnote (2) to new Footnote (3).

Date

Version

Revision

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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This document provides

Virtex-II Device/Package Combi-

nations and Maximum I/Os Available

and

Virtex-II Pin

Definitions

, followed by pinout tables for the following pack-

ages:

CS144 Chip-Scale BGA Package

FG256 Fine-Pitch BGA Package

FG456 Fine-Pitch BGA Package

FG676 Fine-Pitch BGA Package

BG575 Standard BGA Package

BG728 Standard BGA Package

FF896 Flip-Chip Fine-Pitch BGA Package

FF1152 Flip-Chip Fine-Pitch BGA Package

FF1517 Flip-Chip Fine-Pitch BGA Package

BF957 Flip-Chip BGA Package

For device pinout diagrams and layout guidelines, refer to
the

Virtex-II Platform FPGA User Guide

. ASCII package

pinout files are also available for download from the Xilinx
website (

www.xilinx.com

Virtex-II Device/Package Combinations
and Maximum I/Os Available

Wire-bond and flip-chip packages are available.

Table 1

and

Table 2

show the maximum number of user I/Os possible in

wire-bond and flip-chip packages, respectively.

Table 3

shows the number of user I/Os available for all

device/package combinations.

CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).

FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).

FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).

BG denotes standard BGA (1.27 mm pitch).

BF denotes flip-chip BGA (1.27 mm pitch).

The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).

225

VirtexTM-II Platform FPGAs:
Pinout Information

DS031-4 (v2.0) August 1, 2003

Product Specification

Table 1: Wire-Bond Packages Information

Package

CS144

FG256

FG456

FG676

BG575

BG728

Pitch (mm)

0.80

1.00

1.27

Size (mm)

12 x 12

17 x 17

23 x 23

27 x 27

31 x 31

35 x 35

I/Os

172

324

484

408

516

Table 2: Flip-Chip Packages Information

Package

FF896

FF1152

FF1517

BF957

Pitch (mm)

1.00

1.27

Size (mm)

31 x 31

35 x 35

40 x 40

I/Os

624

824

1,108

684

VirtexTM-II Platform FPGAs: Pinout Information

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Virtex-II

Pin Definitions

This section describes the pinouts for Virtex-II devices in the
following packages:

CS144: wire-bond chip-scale ball grid array (BGA) of
0.80 mm pitch

FG256, FG456, and FG676: wire-bond fine-pitch BGA
of 1.00 mm pitch

FF896, FF1152, FF1517: flip-chip fine-pitch BGA of
1.00 mm pitch

BG575 and BG728: wire-bond BGA of 1.27 mm pitch

BF957: flip-chip BGA of 1.27 mm pitch

All of the devices supported in a particular package are
pinout compatible and are listed in the same table (one
table per package). In addition, the FG456 and FG676
packages are compatible, as are the FF896 and FF1152
packages. Pins that are not available for the smallest
devices are listed in right-hand columns.

Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards (see the Virtex-II Data Sheet).
Global pins, including JTAG, configuration, and
power/ground pins, are listed at the end of each table.

Table 4

provides definitions for all pin types.

The FG256 pinouts (

Table 6

) is included as an example. All

Virtex-II pinout tables are available on the distribution
CD-ROM, or on the web (at

http://www.xilinx.com

Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os

Package

Available I/Os

XC2V

250

XC2V

500

XC2V

1000

XC2V

1500

XC2V

2000

XC2V

3000

XC2V

4000

XC2V

6000

XC2V

8000

CS144

FG256

120

172

FG456

200

264

324

FG676

392

456

484

FF896

432

528

624

FF1152

720

824

FF1517

912

1,104

1,108

BG575

328

392

408

BG728

516

BF957

624

684

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

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Pin Definitions

Table 4

provides a description of each pin type listed in Virtex-II pinout tables.

Table 4: Virtex-II Pin Definitions

Pin Name

Direction

Description

User I/O Pins

IO_LXXY_#

Input/Output

All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled "IO_LXXY_#", where:

IO indicates a user I/O pin.

LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.

# indicates the bank number (0 through 7)

Dual-Function Pins

IO_LXXY_#/ZZZ

The dual-function pins are labelled "IO_LXXY_#/ZZZ", where ZZZ can be one of the
following pins:

Per Bank - VRP, VRN, or VREF

Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN D7, RDWR_B, or CS_B

With /ZZZ:

D0/DIN, D1, D2,
D3, D4, D5, D6,
D7

Input/Output

In SelectMAP mode, D0 through D7 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.

In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O
after configuration.

CS_B

Input

In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.

RDWR_B

Input

In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.

BUSY/DOUT

Output

In SelectMAP mode, BUSY controls the rate at which configuration data is loaded.
The pin becomes a user I/O after configuration, unless the SelectMAP port is
retained.

In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.

INIT_B

Bidirectional
(open-drain)

When Low, this pin indicates that the configuration memory is being cleared. When held
Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. The pin becomes a user I/O after
configuration.

GCLKx (S/P)

Input/Output

These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.

VRP

Input

This pin is for the DCI voltage reference resistor of P transistor (per bank).

VRN

Input

This pin is for the DCI voltage reference resistor of N transistor (per bank).

ALT_VRP

Input

This is the alternative pin for the DCI voltage reference resistor of P transistor.

ALT_VRN

Input

This is the alternative pin for the DCI voltage reference resistor of N transistor.

REF

Input

These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).

Dedicated Pins

(1)

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CCLK

Input/Output

Configuration clock. Output in Master mode or Input in Slave mode.

PROG_B

Input

Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.

DONE

Input/Output

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.

M2, M1, M0

Input

Configuration mode selection.

HSWAP_EN

Input

Enable I/O pullups during configuration.

TCK

Input

Boundary Scan Clock.

TDI

Input

Boundary Scan Data Input.

TDO

Output

Boundary Scan Data Output.

TMS

Input

Boundary Scan Mode Select.

PWRDWN_B

Input

(unsupported)

Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.

Other Pins

DXN, DXP

N/A

Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).

BATT

Input

Decryptor key memory backup supply. (Do not connect if battery is not used.)

RSVD

N/A

Reserved pin - do not connect.

CCO

Input

Power-supply pins for the output drivers (per bank).

CCAUX

Input

Power-supply pins for auxiliary circuits.

CCINT

Input

Power-supply pins for the internal core logic.

GND

Input

Ground.

Notes:
1.

All dedicated pins (JTAG and configuration) are powered by V

CCAUX

(independent of the bank V

CCO

voltage).

Table 4: Virtex-II Pin Definitions (Continued)

Pin Name

Direction

Description

VirtexTM-II Platform FPGAs: Pinout Information

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CS144 Chip-Scale BGA Package

As shown in

Table 5

, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144 package. Pins in the

XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the No
Connect column. Following this table are the

CS144 Chip-Scale BGA Package Specifications (0.80mm pitch)

Table 5: CS144 -- XC2V40, XC2V80, and XC2V250

Bank

Pin Description

Pin Number

No Connect in the XC2V40

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L94N_0/VREF_0

IO_L94P_0

IO_L95N_0/GCLK7P

IO_L95P_0/GCLK6S

IO_L96N_0/GCLK5P

IO_L96P_0/GCLK4S

IO_L96N_1/GCLK3P

IO_L96P_1/GCLK2S

IO_L95N_1/GCLK1P

IO_L95P_1/GCLK0S

IO_L94N_1

IO_L94P_1/VREF_1

IO_L03N_1/VRP_1

IO_L03P_1/VRN_1

IO_L02N_1

A10

IO_L02P_1

B10

IO_L01N_1

C10

IO_L01P_1

D10

IO_L01N_2

C13

IO_L01P_2

D11

IO_L02N_2/VRP_2

D12

IO_L02P_2/VRN_2

D13

IO_L03N_2

E10

IO_L03P_2/VREF_2

E11

IO_L93N_2

E13

IO_L93P_2/VREF_2

F11

IO_L94N_2

F12

IO_L94P_2

G10

VirtexTM-II Platform FPGAs: Pinout Information

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IO_L96N_2

G11

IO_L96P_2

G13

IO_L96N_3

G12

IO_L96P_3

H12

IO_L94N_3

H11

IO_L94P_3

J13

IO_L03N_3/VREF_3

J10

IO_L03P_3

K13

IO_L02N_3/VRP_3

K12

IO_L02P_3/VRN_3

K11

IO_L01N_3

K10

IO_L01P_3

L13

IO_L01N_4/BUSY/DOUT

(1)

M11

IO_L01P_4/INIT_B

N11

IO_L02N_4/D0/DIN

(1)

L10

IO_L02P_4/D1

M10

IO_L03N_4/D2/ALT_VRP_4

N10

IO_L03P_4/D3/ALT_VRN_4

IO_L94N_4/VREF_4

IO_L94P_4

IO_L95N_4/GCLK3S

IO_L95P_4/GCLK2P

IO_L96N_4/GCLK1S

IO_L96P_4/GCLK0P

IO_L96N_5/GCLK7S

IO_L96P_5/GCLK6P

IO_L95N_5/GCLK5S

IO_L95P_5/GCLK4P

IO_L94N_5

IO_L94P_5/VREF_5

IO_L03N_5/D4/ALT_VRP_5

IO_L03P_5/D5/ALT_VRN_5

IO_L02N_5/D6

IO_L02P_5/D7

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

Table 5: CS144 -- XC2V40, XC2V80, and XC2V250

Bank

Pin Description

Pin Number

No Connect in the XC2V40

VirtexTM-II Platform FPGAs: Pinout Information

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IO_L01P_6

IO_L01N_6

IO_L02P_6/VRN_6

IO_L02N_6/VRP_6

IO_L03P_6

IO_L03N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

VCCO_1

A11

VCCO_1

VCCO_2

F10

VCCO_2

C12

VCCO_3

L12

VCCO_3

J12

VCCO_4

L11

VCCO_5

VCCO_6

VCCO_7

Table 5: CS144 -- XC2V40, XC2V80, and XC2V250

Bank

Pin Description

Pin Number

No Connect in the XC2V40

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

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CCLK

M13

PROG_B

DONE

N12

TCK

B12

TDI

TDO

C11

TMS

A13

PWRDWN_B

M12

HSWAP_EN

RSVD

VBATT

A12

RSVD

B11

VCCAUX

N13

VCCAUX

B13

VCCINT

H13

VCCINT

GND

J11

GND

H10

GND

F13

GND

E12

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 5: CS144 -- XC2V40, XC2V80, and XC2V250

Bank

Pin Description

Pin Number

No Connect in the XC2V40

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

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CS144 Chip-Scale BGA Package Specifications (0.80mm pitch)

Figure 1: CS144 Chip-Scale BGA Package Specifications

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Module 4 of 4

Product Specification

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FG256 Fine-Pitch BGA Package

As shown in

Table 6

, XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG256

fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No Connect columns
show pin differences for the XC2V40 and XC2V80 devices. Following this table are the

FG256 Fine-Pitch BGA Package

Specifications (1.00mm pitch)

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L04N_0/VREF_0

IO_L04P_0

IO_L05N_0

IO_L05P_0

IO_L92N_0

IO_L92P_0

IO_L93N_0

IO_L93P_0

IO_L94N_0/VREF_0

IO_L94P_0

IO_L95N_0/GCLK7P

IO_L95P_0/GCLK6S

IO_L96N_0/GCLK5P

IO_L96P_0/GCLK4S

IO_L96N_1/GCLK3P

IO_L96P_1/GCLK2S

IO_L95N_1/GCLK1P

IO_L95P_1/GCLK0S

IO_L94N_1

A10

IO_L94P_1/VREF_1

B10

IO_L93N_1

C10

IO_L93P_1

D10

IO_L92N_1

E10

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Module 4 of 4

Product Specification

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IO_L92P_1

E11

IO_L05N_1

A11

IO_L05P_1

B11

IO_L04N_1

C11

IO_L04P_1/VREF_1

D11

IO_L03N_1/VRP_1

A12

IO_L03P_1/VRN_1

B12

IO_L02N_1

C12

IO_L02P_1

D12

IO_L01N_1

B13

IO_L01P_1

C13

IO_L01N_2

C16

IO_L01P_2

D16

IO_L02N_2/VRP_2

D14

IO_L02P_2/VRN_2

D15

IO_L03N_2

E13

IO_L03P_2/VREF_2

E14

IO_L04N_2

E15

IO_L04P_2

E16

IO_L06N_2

F13

IO_L06P_2

F14

IO_L43N_2

F15

IO_L43P_2

F16

IO_L45N_2

F12

IO_L45P_2/VREF_2

G12

IO_L91N_2

G13

IO_L91P_2

G14

IO_L93N_2

G15

IO_L93P_2/VREF_2

G16

IO_L94N_2

H13

IO_L94P_2

H14

IO_L96N_2

H15

IO_L96P_2

H16

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L96N_3

J16

IO_L96P_3

J15

IO_L94N_3

J14

IO_L94P_3

J13

IO_L93N_3/VREF_3

K16

IO_L93P_3

K15

IO_L91N_3

K14

IO_L91P_3

K13

IO_L45N_3/VREF_3

K12

IO_L45P_3

L12

IO_L43N_3

L16

IO_L43P_3

L15

IO_L06N_3

L14

IO_L06P_3

L13

IO_L04N_3

M16

IO_L04P_3

M15

IO_L03N_3/VREF_3

M14

IO_L03P_3

M13

IO_L02N_3/VRP_3

N15

IO_L02P_3/VRN_3

N14

IO_L01N_3

N16

IO_L01P_3

P16

IO_L01N_4/BUSY/DOUT

(1)

T14

IO_L01P_4/INIT_B

T13

IO_L02N_4/D0/DIN

(1)

P13

IO_L02P_4/D1

R13

IO_L03N_4/D2/ALT_VRP_4

N12

IO_L03P_4/D3/ALT_VRN_4

P12

IO_L04N_4/VREF_4

R12

IO_L04P_4

T12

IO_L05N_4/VRP_4

N11

IO_L05P_4/VRN_4

P11

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L91N_4/VREF_4

R11

IO_L91P_4

T11

IO_L92N_4

M11

IO_L92P_4

M10

IO_L93N_4

N10

IO_L93P_4

P10

IO_L94N_4/VREF_4

R10

IO_L94P_4

T10

IO_L95N_4/GCLK3S

IO_L95P_4/GCLK2P

IO_L96N_4/GCLK1S

IO_L96P_4/GCLK0P

IO_L96N_5/GCLK7S

IO_L96P_5/GCLK6P

IO_L95N_5/GCLK5S

IO_L95P_5/GCLK4P

IO_L94N_5

IO_L94P_5/VREF_5

IO_L93N_5

IO_L93P_5

IO_L92N_5

IO_L92P_5

IO_L91N_5

IO_L91P_5/VREF_5

IO_L05N_5/VRP_5

IO_L05P_5/VRN_5

IO_L04N_5

IO_L04P_5/VREF_5

IO_L03N_5/D4/ALT_VRP_5

IO_L03P_5/D5/ALT_VRN_5

IO_L02N_5/D6

IO_L02P_5/D7

IO_L01N_5/RDWR_B

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L01P_5/CS_B

IO_L01P_6

IO_L01N_6

IO_L02P_6/VRN_6

IO_L02N_6/VRP_6

IO_L03P_6

IO_L03N_6/VREF_6

IO_L04P_6

IO_L04N_6

IO_L06P_6

IO_L06N_6

IO_L43P_6

IO_L43N_6

IO_L45P_6

IO_L45N_6/VREF_6

IO_L91P_6

IO_L91N_6

IO_L93P_6

IO_L93N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L91P_7

IO_L91N_7

IO_L45P_7/VREF_7

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L45N_7

IO_L43P_7

IO_L43N_7

IO_L06P_7

IO_L06N_7

IO_L04P_7

IO_L04N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

VCCO_1

F10

VCCO_1

VCCO_2

H12

VCCO_2

H11

VCCO_2

G11

VCCO_3

K11

VCCO_3

J12

VCCO_3

J11

VCCO_4

L10

VCCO_4

VCCO_5

VCCO_6

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_6

VCCO_7

CCLK

P15

PROG_B

DONE

R14

HSWAP_EN

TCK

A15

TDI

TDO

C15

TMS

B14

PWRDWN_B

T15

RSVD

VBATT

A14

RSVD

A13

VCCAUX

R16

VCCAUX

B16

VCCAUX

VCCINT

N13

VCCINT

M12

VCCINT

E12

VCCINT

D13

VCCINT

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

GND

T16

GND

R15

GND

P14

GND

L11

GND

K10

GND

J10

GND

H10

GND

G10

GND

F11

GND

C14

GND

B15

GND

A16

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 6: FG256 BGA -- XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V40

No Connect in XC2V80

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

FG256 Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 2: FG256 Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

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FG456 Fine-Pitch BGA Package

As shown in

Table 7

, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG456 fine-pitch BGA

package. Pins in the XC2V250, XC2V500, and XC2V1000 devices are the same, except for the pin differences in the
XC2V250 and XC2V500 devices shown in the No Connect columns. Following this table are the

FG456 Fine-Pitch BGA

Package Specifications (1.00mm pitch)

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L04N_0/VREF_0

IO_L04P_0

IO_L05N_0

IO_L05P_0

IO_L06N_0

IO_L06P_0

IO_L21N_0

IO_L21P_0/VREF_0

IO_L22N_0

IO_L22P_0

IO_L24N_0

IO_L24P_0

IO_L49N_0

IO_L49P_0

IO_L51N_0

IO_L51P_0/VREF_0

IO_L52N_0

IO_L52P_0

IO_L54N_0

IO_L54P_0

IO_L91N_0/VREF_0

E10

IO_L91P_0

F10

IO_L92N_0

D10

IO_L92P_0

C10

VirtexTM-II Platform FPGAs: Pinout Information

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Product Specification

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IO_L93N_0

B10

IO_L93P_0

A10

IO_L94N_0/VREF_0

E11

IO_L94P_0

F11

IO_L95N_0/GCLK7P

D11

IO_L95P_0/GCLK6S

C11

IO_L96N_0/GCLK5P

B11

IO_L96P_0/GCLK4S

A11

IO_L96N_1/GCLK3P

F12

IO_L96P_1/GCLK2S

F13

IO_L95N_1/GCLK1P

E12

IO_L95P_1/GCLK0S

D12

IO_L94N_1

C12

IO_L94P_1/VREF_1

B12

IO_L93N_1

A13

IO_L93P_1

B13

IO_L92N_1

C13

IO_L92P_1

D13

IO_L91N_1

E13

IO_L91P_1/VREF_1

E14

IO_L54N_1

A14

IO_L54P_1

B14

IO_L52N_1

C14

IO_L52P_1

D14

IO_L51N_1/VREF_1

A15

IO_L51P_1

B15

IO_L49N_1

C15

IO_L49P_1

D15

IO_L24N_1

F14

IO_L24P_1

E15

IO_L22N_1

A16

IO_L22P_1

B16

IO_L21N_1/VREF_1

C16

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L21P_1

D16

IO_L06N_1

E16

IO_L06P_1

E17

IO_L05N_1

A17

IO_L05P_1

B17

IO_L04N_1

C17

IO_L04P_1/VREF_1

D17

IO_L03N_1/VRP_1

A18

IO_L03P_1/VRN_1

B18

IO_L02N_1

C18

IO_L02P_1

D18

IO_L01N_1

A19

IO_L01P_1

B19

IO_L01N_2

C21

IO_L01P_2

C22

IO_L02N_2/VRP_2

E18

IO_L02P_2/VRN_2

F18

IO_L03N_2

D21

IO_L03P_2/VREF_2

D22

IO_L04N_2

E19

IO_L04P_2

E20

IO_L06N_2

E21

IO_L06P_2

E22

IO_L19N_2

F19

IO_L19P_2

F20

IO_L21N_2

F21

IO_L21P_2/VREF_2

F22

IO_L22N_2

G18

IO_L22P_2

H18

IO_L24N_2

G19

IO_L24P_2

G20

IO_L43N_2

G21

IO_L43P_2

G22

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L45N_2

H19

IO_L45P_2/VREF_2

H20

IO_L46N_2

H21

IO_L46P_2

H22

IO_L48N_2

J17

IO_L48P_2

J18

IO_L49N_2

J19

IO_L49P_2

J20

IO_L51N_2

J21

IO_L51P_2/VREF_2

J22

IO_L52N_2

K17

IO_L52P_2

K18

IO_L54N_2

K19

IO_L54P_2

K20

IO_L91N_2

K21

IO_L91P_2

K22

IO_L93N_2

L17

IO_L93P_2/VREF_2

L18

IO_L94N_2

L19

IO_L94P_2

L20

IO_L96N_2

L21

IO_L96P_2

L22

IO_L96N_3

M21

IO_L96P_3

M20

IO_L94N_3

M19

IO_L94P_3

M18

IO_L93N_3/VREF_3

M17

IO_L93P_3

N17

IO_L91N_3

N22

IO_L91P_3

N21

IO_L54N_3

N20

IO_L54P_3

N19

IO_L52N_3

N18

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52P_3

P18

IO_L51N_3/VREF_3

P22

IO_L51P_3

P21

IO_L49N_3

P20

IO_L49P_3

P19

IO_L48N_3

R22

IO_L48P_3

R21

IO_L46N_3

R20

IO_L46P_3

R19

IO_L45N_3/VREF_3

R18

IO_L45P_3

P17

IO_L43N_3

T22

IO_L43P_3

T21

IO_L24N_3

T20

IO_L24P_3

T19

IO_L22N_3

U22

IO_L22P_3

U21

IO_L21N_3/VREF_3

U20

IO_L21P_3

U19

IO_L19N_3

T18

IO_L19P_3

U18

IO_L06N_3

V22

IO_L06P_3

V21

IO_L04N_3

V20

IO_L04P_3

V19

IO_L03N_3/VREF_3

W22

IO_L03P_3

W21

IO_L02N_3/VRP_3

Y22

IO_L02P_3/VRN_3

Y21

IO_L01N_3

W20

IO_L01P_3

AA20

IO_L01N_4/BUSY/DOUT

(1)

AB19

IO_L01P_4/INIT_B

AA19

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L02N_4/D0/DIN

(1)

V18

IO_L02P_4/D1

V17

IO_L03N_4/D2/ALT_VRP_4

W18

IO_L03P_4/D3/ALT_VRN_4

Y18

IO_L04N_4/VREF_4

AA18

IO_L04P_4

AB18

IO_L05N_4/VRP_4

W17

IO_L05P_4/VRN_4

Y17

IO_L06N_4

AA17

IO_L06P_4

AB17

IO_L19N_4

V16

IO_L19P_4

V15

IO_L21N_4

W16

IO_L21P_4/VREF_4

Y16

IO_L22N_4

AA16

IO_L22P_4

AB16

IO_L24N_4

W15

IO_L24P_4

Y15

IO_L49N_4

AA15

IO_L49P_4

AB15

IO_L51N_4

U14

IO_L51P_4/VREF_4

V14

IO_L52N_4

W14

IO_L52P_4

Y14

IO_L54N_4

AA14

IO_L54P_4

AB14

IO_L91N_4/VREF_4

U13

IO_L91P_4

V13

IO_L92N_4

W13

IO_L92P_4

Y13

IO_L93N_4

AA13

IO_L93P_4

AB13

IO_L94N_4/VREF_4

U12

IO_L94P_4

V12

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L95N_4/GCLK3S

W12

IO_L95P_4/GCLK2P

Y12

IO_L96N_4/GCLK1S

AA12

IO_L96P_4/GCLK0P

AB12

IO_L96N_5/GCLK7S

AA11

IO_L96P_5/GCLK6P

Y11

IO_L95N_5/GCLK5S

W11

IO_L95P_5/GCLK4P

V11

IO_L94N_5

U11

IO_L94P_5/VREF_5

U10

IO_L93N_5

AB10

IO_L93P_5

AA10

IO_L92N_5

Y10

IO_L92P_5

W10

IO_L91N_5

V10

IO_L91P_5/VREF_5

IO_L54N_5

AB9

IO_L54P_5

AA9

IO_L52N_5

IO_L52P_5

IO_L51N_5/VREF_5

AB8

IO_L51P_5

AA8

IO_L49N_5

IO_L49P_5

IO_L24N_5

IO_L24P_5

IO_L22N_5

AB7

IO_L22P_5

AA7

IO_L21N_5/VREF_5

IO_L21P_5

IO_L19N_5

AB6

IO_L19P_5

AA6

IO_L06N_5

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L06P_5

IO_L05N_5/VRP_5

IO_L05P_5/VRN_5

IO_L04N_5

AB5

IO_L04P_5/VREF_5

AA5

IO_L03N_5/D4/ALT_VRP_5

IO_L03P_5/D5/ALT_VRN_5

IO_L02N_5/D6

AB4

IO_L02P_5/D7

AA4

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

AA3

IO_L01P_6

IO_L01N_6

IO_L02P_6/VRN_6

IO_L02N_6/VRP_6

IO_L03P_6

IO_L03N_6/VREF_6

IO_L04P_6

IO_L04N_6

IO_L06P_6

IO_L06N_6

IO_L19P_6

IO_L19N_6

IO_L21P_6

IO_L21N_6/VREF_6

IO_L22P_6

IO_L22N_6

IO_L24P_6

IO_L24N_6

IO_L43P_6

IO_L43N_6

IO_L45P_6

IO_L45N_6/VREF_6

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L46P_6

IO_L46N_6

IO_L48P_6

IO_L48N_6

IO_L49P_6

IO_L49N_6

IO_L51P_6

IO_L51N_6/VREF_6

IO_L52P_6

IO_L52N_6

IO_L54P_6

IO_L54N_6

IO_L91P_6

IO_L91N_6

IO_L93P_6

IO_L93N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L91P_7

IO_L91N_7

IO_L54P_7

IO_L54N_7

IO_L52P_7

IO_L52N_7

IO_L51P_7/VREF_7

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L51N_7

IO_L49P_7

IO_L49N_7

IO_L48P_7

IO_L48N_7

IO_L46P_7

IO_L46N_7

IO_L45P_7/VREF_7

IO_L45N_7

IO_L43P_7

IO_L43N_7

IO_L24P_7

IO_L24N_7

IO_L22P_7

IO_L22N_7

IO_L21P_7/VREF_7

IO_L21N_7

IO_L19P_7

IO_L19N_7

IO_L06P_7

IO_L06N_7

IO_L04P_7

IO_L04N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

G11

VCCO_0

G10

VCCO_0

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_0

VCCO_1

G14

VCCO_1

G13

VCCO_1

G12

VCCO_1

F16

VCCO_1

F15

VCCO_2

L16

VCCO_2

K16

VCCO_2

J16

VCCO_2

H17

VCCO_2

G17

VCCO_3

T17

VCCO_3

R17

VCCO_3

P16

VCCO_3

N16

VCCO_3

M16

VCCO_4

U16

VCCO_4

U15

VCCO_4

T14

VCCO_4

T13

VCCO_4

T12

VCCO_5

T11

VCCO_5

T10

VCCO_5

VCCO_6

VCCO_7

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_7

CCLK

Y19

PROG_B

DONE

AB20

AB2

AB3

HSWAP_EN

TCK

C19

TDI

TDO

D20

TMS

B20

PWRDWN_B

AB21

DXN

DXP

VBATT

A21

RSVD

A20

VCCAUX

AB11

VCCAUX

AA22

VCCAUX

AA1

VCCAUX

M22

VCCAUX

B22

VCCAUX

A12

VCCINT

U17

VCCINT

T16

VCCINT

T15

VCCINT

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCINT

R16

VCCINT

H16

VCCINT

G16

VCCINT

G15

VCCINT

F17

VCCINT

GND

AB22

GND

AB1

GND

AA21

GND

AA2

GND

Y20

GND

W19

GND

P14

GND

P13

GND

P12

GND

P11

GND

P10

GND

N14

GND

N13

GND

N12

GND

N11

GND

N10

GND

M14

GND

M13

GND

M12

GND

M11

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

M10

GND

L14

GND

L13

GND

L12

GND

L11

GND

L10

GND

K14

GND

K13

GND

K12

GND

K11

GND

K10

GND

J14

GND

J13

GND

J12

GND

J11

GND

J10

GND

D19

GND

C20

GND

B21

GND

A22

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 7: FG456 BGA -- XC2V250, XC2V500, and XC2V1000

Bank

Pin Description

Pin Number

No Connect in XC2V250

No Connect in XC2V500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

FG456 Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 3: FG456 Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

FG676 Fine-Pitch BGA Package

As shown in

Table 8

, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676 fine-pitch BGA

package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the
XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the

FG676 Fine-Pitch BGA

Package Specifications (1.00mm pitch)

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L04N_0/VREF_0

IO_L04P_0

IO_L05N_0

IO_L05P_0

IO_L06N_0

IO_L06P_0

IO_L19N_0

IO_L19P_0

IO_L21N_0

IO_L21P_0/VREF_0

IO_L22N_0

IO_L22P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0/VREF_0

IO_L49N_0

IO_L49P_0

IO_L51N_0

IO_L51P_0/VREF_0

IO_L52N_0

IO_L52P_0

IO_L54N_0

IO_L54P_0

IO_L67N_0

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L67P_0

C10

IO_L69N_0

F10

IO_L69P_0/VREF_0

G10

IO_L70N_0

E10

IO_L70P_0

D10

IO_L72N_0

A10

IO_L72P_0

A11

IO_L73N_0

F11

IO_L73P_0

E11

IO_L75N_0

G11

IO_L75P_0/VREF_0

H11

IO_L76N_0

D11

IO_L76P_0

C11

IO_L78N_0

B11

IO_L78P_0

B12

IO_L91N_0/VREF_0

G12

IO_L91P_0

H12

IO_L92N_0

F12

IO_L92P_0

E12

IO_L93N_0

D12

IO_L93P_0

C12

IO_L94N_0/VREF_0

G13

IO_L94P_0

H13

IO_L95N_0/GCLK7P

F13

IO_L95P_0/GCLK6S

E13

IO_L96N_0/GCLK5P

D13

IO_L96P_0/GCLK4S

C13

IO_L96N_1/GCLK3P

H14

IO_L96P_1/GCLK2S

H15

IO_L95N_1/GCLK1P

G14

IO_L95P_1/GCLK0S

F14

IO_L94N_1

E14

IO_L94P_1/VREF_1

D14

IO_L93N_1

A12

IO_L93P_1

A13

IO_L92N_1

A14

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L92P_1

A15

IO_L91N_1

B15

IO_L91P_1/VREF_1

C15

IO_L78N_1

D15

IO_L78P_1

E15

IO_L76N_1

F15

IO_L76P_1

G15

IO_L75N_1/VREF_1

G16

IO_L75P_1

F16

IO_L73N_1

A16

IO_L73P_1

A17

IO_L72N_1

B16

IO_L72P_1

C16

IO_L70N_1

D16

IO_L70P_1

E16

IO_L69N_1/VREF_1

C17

IO_L69P_1

D17

IO_L67N_1

H16

IO_L67P_1

G17

IO_L54N_1

E17

IO_L54P_1

F17

IO_L52N_1

A18

IO_L52P_1

A19

IO_L51N_1/VREF_1

E18

IO_L51P_1

D18

IO_L49N_1

B18

IO_L49P_1

C18

IO_L27N_1/VREF_1

F19

IO_L27P_1

F18

IO_L25N_1

G18

IO_L25P_1

G19

IO_L24N_1

B19

IO_L24P_1

C19

IO_L22N_1

D19

IO_L22P_1

E19

IO_L21N_1/VREF_1

A20

IO_L21P_1

A21

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L19N_1

E20

IO_L19P_1

F20

IO_L06N_1

B21

IO_L06P_1

B22

IO_L05N_1

A22

IO_L05P_1

A23

IO_L04N_1

C21

IO_L04P_1/VREF_1

D21

IO_L03N_1/VRP_1

C20

IO_L03P_1/VRN_1

D20

IO_L02N_1

A24

IO_L02P_1

A25

IO_L01N_1

B23

IO_L01P_1

B24

IO_L01N_2

B26

IO_L01P_2

C26

IO_L02N_2/VRP_2

G20

IO_L02P_2/VRN_2

H20

IO_L03N_2

C25

IO_L03P_2/VREF_2

D25

IO_L04N_2

E23

IO_L04P_2

E24

IO_L06N_2

G21

IO_L06P_2

G22

IO_L19N_2

D26

IO_L19P_2

E26

IO_L21N_2

F23

IO_L21P_2/VREF_2

F24

IO_L22N_2

E25

IO_L22P_2

F25

IO_L24N_2

H22

IO_L24P_2

H21

IO_L25N_2

G23

IO_L25P_2

G24

IO_L43N_2

F26

IO_L43P_2

G26

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L45N_2

H23

IO_L45P_2/VREF_2

H24

IO_L46N_2

J21

IO_L46P_2

J20

IO_L48N_2

H25

IO_L48P_2

H26

IO_L49N_2

J22

IO_L49P_2

J23

IO_L51N_2

K21

IO_L51P_2/VREF_2

K22

IO_L52N_2

K20

IO_L52P_2

L20

IO_L54N_2

J24

IO_L54P_2

J25

IO_L67N_2

K23

IO_L67P_2

K24

IO_L69N_2

J26

IO_L69P_2/VREF_2

K26

IO_L70N_2

L22

IO_L70P_2

L21

IO_L72N_2

L25

IO_L72P_2

L26

IO_L73N_2

L19

IO_L73P_2

M19

IO_L75N_2

L23

IO_L75P_2/VREF_2

L24

IO_L76N_2

M22

IO_L76P_2

M21

IO_L78N_2

M23

IO_L78P_2

M24

IO_L91N_2

M25

IO_L91P_2

M26

IO_L93N_2

M20

IO_L93P_2/VREF_2

N20

IO_L94N_2

N22

IO_L94P_2

N21

IO_L96N_2

N24

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L96P_2

N23

IO_L96N_3

N26

IO_L96P_3

P26

IO_L94N_3

P23

IO_L94P_3

P22

IO_L93N_3/VREF_3

P19

IO_L93P_3

N19

IO_L91N_3

P21

IO_L91P_3

P20

IO_L78N_3

R26

IO_L78P_3

R25

IO_L76N_3

R20

IO_L76P_3

R19

IO_L75N_3/VREF_3

R24

IO_L75P_3

R23

IO_L73N_3

R22

IO_L73P_3

R21

IO_L72N_3

T26

IO_L72P_3

T25

IO_L70N_3

T20

IO_L70P_3

T19

IO_L69N_3/VREF_3

T24

IO_L69P_3

T23

IO_L67N_3

T22

IO_L67P_3

T21

IO_L54N_3

U26

IO_L54P_3

V26

IO_L52N_3

U24

IO_L52P_3

U23

IO_L51N_3/VREF_3

U22

IO_L51P_3

U21

IO_L49N_3

V25

IO_L49P_3

V24

IO_L48N_3

V23

IO_L48P_3

V22

IO_L46N_3

W26

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L46P_3

Y26

IO_L45N_3/VREF_3

U20

IO_L45P_3

V20

IO_L43N_3

W25

IO_L43P_3

W24

IO_L25N_3

V21

IO_L25P_3

W21

IO_L24N_3

AA26

IO_L24P_3

AA25

IO_L22N_3

Y24

IO_L22P_3

Y23

IO_L21N_3/VREF_3

W22

IO_L21P_3

W23

IO_L19N_3

AB26

IO_L19P_3

AB25

IO_L06N_3

AC26

IO_L06P_3

AC25

IO_L04N_3

AD26

IO_L04P_3

AD25

IO_L03N_3/VREF_3

AA24

IO_L03P_3

AA23

IO_L02N_3/VRP_3

AB24

IO_L02P_3/VRN_3

AB23

IO_L01N_3

Y22

IO_L01P_3

AA22

IO_L01N_4/BUSY/DOUT

(1)

AD21

IO_L01P_4/INIT_B

AC21

IO_L02N_4/D0/DIN

(1)

Y20

IO_L02P_4/D1

Y19

IO_L03N_4/D2/ALT_VRP_4

AA20

IO_L03P_4/D3/ALT_VRN_4

AB20

IO_L04N_4/VREF_4

AC22

IO_L04P_4

AE21

IO_L05N_4/VRP_4

AE26

IO_L05P_4/VRN_4

AF25

IO_L06N_4

W20

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L06P_4

Y21

IO_L19N_4

AE24

IO_L19P_4

AF24

IO_L21N_4

AE23

IO_L21P_4/VREF_4

AF23

IO_L22N_4

AE22

IO_L22P_4

AF22

IO_L24N_4

AF21

IO_L24P_4

AF20

IO_L25N_4

AA19

IO_L25P_4

AB19

IO_L27N_4

AD20

IO_L27P_4/VREF_4

AC20

IO_L28N_4

AC19

IO_L28P_4

AD19

IO_L49N_4

AE19

IO_L49P_4

AF19

IO_L51N_4

AA18

IO_L51P_4/VREF_4

AB18

IO_L52N_4

Y18

IO_L52P_4

Y17

IO_L54N_4

AC18

IO_L54P_4

AD18

IO_L67N_4

AE18

IO_L67P_4

AF18

IO_L69N_4

AA17

IO_L69P_4/VREF_4

AB17

IO_L70N_4

AC17

IO_L70P_4

AD17

IO_L72N_4

AF17

IO_L72P_4

AF16

IO_L73N_4

AB16

IO_L73P_4

AC16

IO_L75N_4

AA16

IO_L75P_4/VREF_4

Y16

IO_L76N_4

AD16

IO_L76P_4

AE16

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L78N_4

Y15

IO_L78P_4

AA15

IO_L91N_4/VREF_4

W15

IO_L91P_4

W16

IO_L92N_4

AB15

IO_L92P_4

AC15

IO_L93N_4

AD15

IO_L93P_4

AE15

IO_L94N_4/VREF_4

W14

IO_L94P_4

Y14

IO_L95N_4/GCLK3S

AA14

IO_L95P_4/GCLK2P

AB14

IO_L96N_4/GCLK1S

AC14

IO_L96P_4/GCLK0P

AD14

IO_L96N_5/GCLK7S

AC13

IO_L96P_5/GCLK6P

AB13

IO_L95N_5/GCLK5S

AA13

IO_L95P_5/GCLK4P

Y13

IO_L94N_5

W13

IO_L94P_5/VREF_5

W12

IO_L93N_5

AF15

IO_L93P_5

AF14

IO_L92N_5

AF13

IO_L92P_5

AF12

IO_L91N_5

AE12

IO_L91P_5/VREF_5

AD12

IO_L78N_5

AC12

IO_L78P_5

AB12

IO_L76N_5

AA12

IO_L76P_5

Y12

IO_L75N_5/VREF_5

AF11

IO_L75P_5

AF10

IO_L73N_5

AE11

IO_L73P_5

AD11

IO_L72N_5

AC11

IO_L72P_5

AB11

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L70N_5

W11

IO_L70P_5

Y10

IO_L69N_5/VREF_5

Y11

IO_L69P_5

AA11

IO_L67N_5

AF9

IO_L67P_5

AF8

IO_L54N_5

AE9

IO_L54P_5

AD9

IO_L52N_5

AB10

IO_L52P_5

AA10

IO_L51N_5/VREF_5

AD10

IO_L51P_5

AC10

IO_L49N_5

AE8

IO_L49P_5

AF7

IO_L28N_5

AD8

IO_L28P_5

AC8

IO_L27N_5/VREF_5

AB9

IO_L27P_5

AC9

IO_L25N_5

AA9

IO_L25P_5

IO_L24N_5

AF6

IO_L24P_5

AE6

IO_L22N_5

AB8

IO_L22P_5

AA8

IO_L21N_5/VREF_5

AC7

IO_L21P_5

AD7

IO_L19N_5

AF5

IO_L19P_5

AE5

IO_L06N_5

AF4

IO_L06P_5

AE4

IO_L05N_5/VRP_5

AF3

IO_L05P_5/VRN_5

AE3

IO_L04N_5

IO_L04P_5/VREF_5

IO_L03N_5/D4/ALT_VRP_5

AB7

IO_L03P_5/D5/ALT_VRN_5

AA7

IO_L02N_5/D6

AD6

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L02P_5/D7

AC6

IO_L01N_5/RDWR_B

AB6

IO_L01P_5/CS_B

AC5

IO_L01P_6

AF2

IO_L01N_6

AE1

IO_L02P_6/VRN_6

AB4

IO_L02N_6/VRP_6

AB3

IO_L03P_6

AD2

IO_L03N_6/VREF_6

AD1

IO_L04P_6

AC2

IO_L04N_6

AC1

IO_L06P_6

AB2

IO_L06N_6

AB1

IO_L19P_6

AA4

IO_L19N_6

AA3

IO_L21P_6

IO_L21N_6/VREF_6

IO_L22P_6

IO_L22N_6

IO_L24P_6

AA2

IO_L24N_6

AA1

IO_L25P_6

IO_L25N_6

IO_L43P_6

IO_L43N_6

IO_L45P_6

IO_L45N_6/VREF_6

IO_L46P_6

IO_L46N_6

IO_L48P_6

IO_L48N_6

IO_L49P_6

IO_L49N_6

IO_L51P_6

IO_L51N_6/VREF_6

IO_L52P_6

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52N_6

IO_L54P_6

IO_L54N_6

IO_L67P_6

IO_L67N_6

IO_L69P_6

IO_L69N_6/VREF_6

IO_L70P_6

IO_L70N_6

IO_L72P_6

IO_L72N_6

IO_L73P_6

IO_L73N_6

IO_L75P_6

IO_L75N_6/VREF_6

IO_L76P_6

IO_L76N_6

IO_L78P_6

IO_L78N_6

IO_L91P_6

IO_L91N_6

IO_L93P_6

IO_L93N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L91P_7

IO_L91N_7

IO_L78P_7

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L78N_7

IO_L76P_7

IO_L76N_7

IO_L75P_7/VREF_7

IO_L75N_7

IO_L73P_7

IO_L73N_7

IO_L72P_7

IO_L72N_7

IO_L70P_7

IO_L70N_7

IO_L69P_7/VREF_7

IO_L69N_7

IO_L67P_7

IO_L67N_7

IO_L54P_7

IO_L54N_7

IO_L52P_7

IO_L52N_7

IO_L51P_7/VREF_7

IO_L51N_7

IO_L49P_7

IO_L49N_7

IO_L48P_7

IO_L48N_7

IO_L46P_7

IO_L46N_7

IO_L45P_7/VREF_7

IO_L45N_7

IO_L43P_7

IO_L43N_7

IO_L25P_7

IO_L25N_7

IO_L24P_7

IO_L24N_7

IO_L22P_7

IO_L22N_7

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L21P_7/VREF_7

IO_L21N_7

IO_L19P_7

IO_L19N_7

IO_L06P_7

IO_L06N_7

IO_L04P_7

IO_L04N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

J13

VCCO_0

J12

VCCO_0

J11

VCCO_0

H10

VCCO_0

B10

VCCO_0

VCCO_1

B17

VCCO_1

J16

VCCO_1

J15

VCCO_1

J14

VCCO_1

H18

VCCO_1

H17

VCCO_1

B20

VCCO_2

N18

VCCO_2

M18

VCCO_2

L18

VCCO_2

K25

VCCO_2

K19

VCCO_2

J19

VCCO_2

G25

VCCO_3

Y25

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_3

V19

VCCO_3

U25

VCCO_3

U19

VCCO_3

T18

VCCO_3

R18

VCCO_3

P18

VCCO_4

AE20

VCCO_4

AE17

VCCO_4

W18

VCCO_4

W17

VCCO_4

V16

VCCO_4

V15

VCCO_4

V14

VCCO_5

AE10

VCCO_5

AE7

VCCO_5

W10

VCCO_5

V13

VCCO_5

V12

VCCO_5

V11

VCCO_6

VCCO_7

CCLK

AB21

PROG_B

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

DONE

AD22

AD4

AA5

AD5

HSWAP_EN

TCK

E21

TDI

TDO

F22

TMS

D22

PWRDWN_B

AD23

DXN

DXP

VBATT

C23

RSVD

C22

VCCAUX

AD13

VCCAUX

AC24

VCCAUX

AC3

VCCAUX

P24

VCCAUX

D24

VCCAUX

C14

VCCINT

W19

VCCINT

V18

VCCINT

V17

VCCINT

V10

VCCINT

U18

VCCINT

K18

VCCINT

J18

VCCINT

J17

VCCINT

J10

VCCINT

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCINT

H19

VCCINT

GND

AF26

GND

AF1

GND

AE25

GND

AE14

GND

AE13

GND

AE2

GND

AD24

GND

AD3

GND

AC23

GND

AC4

GND

AB22

GND

AB5

GND

AA21

GND

AA6

GND

U17

GND

U16

GND

U15

GND

U14

GND

U13

GND

U12

GND

U11

GND

U10

GND

T17

GND

T16

GND

T15

GND

T14

GND

T13

GND

T12

GND

T11

GND

T10

GND

R17

GND

R16

GND

R15

GND

R14

GND

R13

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

R12

GND

R11

GND

R10

GND

P25

GND

P17

GND

P16

GND

P15

GND

P14

GND

P13

GND

P12

GND

P11

GND

P10

GND

N25

GND

N17

GND

N16

GND

N15

GND

N14

GND

N13

GND

N12

GND

N11

GND

N10

GND

M17

GND

M16

GND

M15

GND

M14

GND

M13

GND

M12

GND

M11

GND

M10

GND

L17

GND

L16

GND

L15

GND

L14

GND

L13

GND

L12

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

L11

GND

L10

GND

K17

GND

K16

GND

K15

GND

K14

GND

K13

GND

K12

GND

K11

GND

K10

GND

F21

GND

E22

GND

D23

GND

C24

GND

B25

GND

B14

GND

B13

GND

A26

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 8: FG676 BGA -- XC2V1500, XC2V2000, and XC2V3000

Bank

Pin Description

Pin Number

No Connect in XC2V1500

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

FG676 Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 4: FG676 Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

BG575 Standard BGA Package

As shown in

Table 9

, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575 BGA package.

Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the XC2V1000
and XC2V1500 devices shown in the No Connect columns. Following this table are the

BG575 Standard BGA Package

Specifications (1.27mm pitch)

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L04N_0/VREF_0

IO_L04P_0

IO_L05N_0

IO_L05P_0

IO_L06N_0

IO_L06P_0

IO_L19N_0

IO_L19P_0

IO_L21N_0

IO_L21P_0/VREF_0

IO_L22N_0

IO_L22P_0

IO_L24N_0

IO_L24P_0

IO_L49N_0

G10

IO_L49P_0

H10

IO_L51N_0

IO_L51P_0/VREF_0

IO_L52N_0

IO_L52P_0

IO_L54N_0

IO_L54P_0

IO_L67N_0

IO_L67P_0

IO_L69N_0

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L69P_0/VREF_0

IO_L70N_0

F10

IO_L70P_0

E10

IO_L72N_0

A10

IO_L72P_0

A11

IO_L73N_0

C10

IO_L73P_0

B10

IO_L91N_0/VREF_0

D11

IO_L91P_0

C11

IO_L92N_0

G11

IO_L92P_0

E11

IO_L93N_0

C12

IO_L93P_0

B12

IO_L94N_0/VREF_0

E12

IO_L94P_0

D12

IO_L95N_0/GCLK7P

G12

IO_L95P_0/GCLK6S

F12

IO_L96N_0/GCLK5P

H11

IO_L96P_0/GCLK4S

H12

IO_L96N_1/GCLK3P

A13

IO_L96P_1/GCLK2S

A14

IO_L95N_1/GCLK1P

B13

IO_L95P_1/GCLK0S

C13

IO_L94N_1

D13

IO_L94P_1/VREF_1

E13

IO_L93N_1

F13

IO_L93P_1

G13

IO_L92N_1

H13

IO_L92P_1

H14

IO_L91N_1

C14

IO_L91P_1/VREF_1

D14

IO_L73N_1

E14

IO_L73P_1

G14

IO_L72N_1

A15

IO_L72P_1

A16

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L70N_1

B15

IO_L70P_1

C15

IO_L69N_1/VREF_1

E15

IO_L69P_1

F15

IO_L67N_1

G15

IO_L67P_1

H15

IO_L54N_1

B16

IO_L54P_1

C16

IO_L52N_1

D16

IO_L52P_1

E16

IO_L51N_1/VREF_1

F16

IO_L51P_1

G16

IO_L49N_1

A17

IO_L49P_1

A19

IO_L24N_1

B17

IO_L24P_1

B18

IO_L22N_1

C17

IO_L22P_1

D17

IO_L21N_1/VREF_1

F17

IO_L21P_1

E17

IO_L19N_1

A20

IO_L19P_1

A21

IO_L06N_1

B19

IO_L06P_1

B20

IO_L05N_1

C18

IO_L05P_1

D18

IO_L04N_1

C20

IO_L04P_1/VREF_1

D20

IO_L03N_1/VRP_1

D19

IO_L03P_1/VRN_1

E19

IO_L02N_1

E18

IO_L02P_1

F18

IO_L01N_1

H16

IO_L01P_1

G17

IO_L01N_2

D22

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L01P_2

D23

IO_L02N_2/VRP_2

E21

IO_L02P_2/VRN_2

E22

IO_L03N_2

F21

IO_L03P_2/VREF_2

F20

IO_L04N_2

G20

IO_L04P_2

G19

IO_L06N_2

H18

IO_L06P_2

J17

IO_L19N_2

D24

IO_L19P_2

E23

IO_L21N_2

E24

IO_L21P_2/VREF_2

F24

IO_L22N_2

F23

IO_L22P_2

G23

IO_L24N_2

G21

IO_L24P_2

G22

IO_L43N_2

H19

IO_L43P_2

H20

IO_L45N_2

J18

IO_L45P_2/VREF_2

J19

IO_L46N_2

K17

IO_L46P_2

K18

IO_L48N_2

H23

IO_L48P_2

H24

IO_L49N_2

H21

IO_L49P_2

H22

IO_L51N_2

J24

IO_L51P_2/VREF_2

K24

IO_L52N_2

J22

IO_L52P_2

J23

IO_L54N_2

J20

IO_L54P_2

J21

IO_L67N_2

K19

IO_L67P_2

K20

IO_L69N_2

L17

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L69P_2/VREF_2

L18

IO_L70N_2

K23

IO_L70P_2

L24

IO_L72N_2

K22

IO_L72P_2

L22

IO_L73N_2

L21

IO_L73P_2

L20

IO_L91N_2

M23

IO_L91P_2

N24

IO_L93N_2

M21

IO_L93P_2/VREF_2

M22

IO_L94N_2

M19

IO_L94P_2

M20

IO_L96N_2

M17

IO_L96P_2

M18

IO_L96N_3

N23

IO_L96P_3

N22

IO_L94N_3

N20

IO_L94P_3

N21

IO_L93N_3/VREF_3

N19

IO_L93P_3

N18

IO_L91N_3

N17

IO_L91P_3

P17

IO_L73N_3

P24

IO_L73P_3

R24

IO_L72N_3

R23

IO_L72P_3

R22

IO_L70N_3

P22

IO_L70P_3

P21

IO_L69N_3/VREF_3

P20

IO_L69P_3

P18

IO_L67N_3

T24

IO_L67P_3

U24

IO_L54N_3

T23

IO_L54P_3

T22

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52N_3

T21

IO_L52P_3

T20

IO_L51N_3/VREF_3

R20

IO_L51P_3

R19

IO_L49N_3

W24

IO_L49P_3

W23

IO_L48N_3

U23

IO_L48P_3

V23

IO_L46N_3

U22

IO_L46P_3

U21

IO_L45N_3/VREF_3

V22

IO_L45P_3

V21

IO_L43N_3

U19

IO_L43P_3

U20

IO_L24N_3

T19

IO_L24P_3

T18

IO_L22N_3

R18

IO_L22P_3

R17

IO_L21N_3/VREF_3

Y24

IO_L21P_3

Y23

IO_L19N_3

AA24

IO_L19P_3

AB24

IO_L06N_3

AA23

IO_L06P_3

AA22

IO_L04N_3

Y22

IO_L04P_3

Y21

IO_L03N_3/VREF_3

W21

IO_L03P_3

W20

IO_L02N_3/VRP_3

V20

IO_L02P_3/VRN_3

V19

IO_L01N_3

U18

IO_L01P_3

T17

IO_L01N_4/BUSY/DOUT

(1)

AD22

IO_L01P_4/INIT_B

AD21

IO_L02N_4/D0/DIN

(1)

AA20

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L02P_4/D1

AB20

IO_L03N_4/D2/ALT_VRP_4

Y19

IO_L03P_4/D3/ALT_VRN_4

AA19

IO_L04N_4/VREF_4

W18

IO_L04P_4

Y18

IO_L05N_4/VRP_4

U16

IO_L05P_4/VRN_4

V17

IO_L06N_4

AD20

IO_L06P_4

AD19

IO_L19N_4

AC20

IO_L19P_4

AC19

IO_L21N_4

AA18

IO_L21P_4/VREF_4

AB18

IO_L22N_4

AC18

IO_L22P_4

AC17

IO_L24N_4

AA17

IO_L24P_4

AB17

IO_L49N_4

Y17

IO_L49P_4

W17

IO_L51N_4

V16

IO_L51P_4/VREF_4

W16

IO_L52N_4

AD17

IO_L52P_4

AD16

IO_L54N_4

AB16

IO_L54P_4

AC16

IO_L67N_4

Y16

IO_L67P_4

AA16

IO_L69N_4

W15

IO_L69P_4/VREF_4

Y15

IO_L70N_4

U15

IO_L70P_4

V15

IO_L72N_4

AD15

IO_L72P_4

AD14

IO_L73N_4

AB15

IO_L73P_4

AC15

IO_L91N_4/VREF_4

AA14

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L91P_4

AB14

IO_L92N_4

V14

IO_L92P_4

Y14

IO_L93N_4

AB13

IO_L93P_4

AC13

IO_L94N_4/VREF_4

Y13

IO_L94P_4

AA13

IO_L95N_4/GCLK3S

V13

IO_L95P_4/GCLK2P

W13

IO_L96N_4/GCLK1S

U14

IO_L96P_4/GCLK0P

U13

IO_L96N_5/GCLK7S

AD12

IO_L96P_5/GCLK6P

AD11

IO_L95N_5/GCLK5S

AC12

IO_L95P_5/GCLK4P

AB12

IO_L94N_5

AA12

IO_L94P_5/VREF_5

Y12

IO_L93N_5

W12

IO_L93P_5

V12

IO_L92N_5

U12

IO_L92P_5

U11

IO_L91N_5

AB11

IO_L91P_5/VREF_5

AA11

IO_L73N_5

Y11

IO_L73P_5

V11

IO_L72N_5

AD10

IO_L72P_5

AD9

IO_L70N_5

AC10

IO_L70P_5

AB10

IO_L69N_5/VREF_5

Y10

IO_L69P_5

W10

IO_L67N_5

V10

IO_L67P_5

U10

IO_L54N_5

AC9

IO_L54P_5

AB9

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52N_5

AA9

IO_L52P_5

IO_L51N_5/VREF_5

IO_L51P_5

IO_L49N_5

AD8

IO_L49P_5

AD6

IO_L24N_5

AC8

IO_L24P_5

AC7

IO_L22N_5

AB8

IO_L22P_5

AA8

IO_L21N_5/VREF_5

IO_L21P_5

IO_L19N_5

AD5

IO_L19P_5

AD4

IO_L06N_5

AC6

IO_L06P_5

AC5

IO_L05N_5/VRP_5

AB7

IO_L05P_5/VRN_5

AA7

IO_L04N_5

AB5

IO_L04P_5/VREF_5

AA5

IO_L03N_5/D4/ALT_VRP_5

AA6

IO_L03P_5/D5/ALT_VRN_5

IO_L02N_5/D6

IO_L02P_5/D7

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

IO_L01P_6

AB2

IO_L01N_6

AB1

IO_L02P_6/VRN_6

AA3

IO_L02N_6/VRP_6

AA2

IO_L03P_6

IO_L03N_6/VREF_6

IO_L04P_6

IO_L04N_6

IO_L06P_6

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L06N_6

IO_L19P_6

IO_L19N_6

IO_L21P_6

AA1

IO_L21N_6/VREF_6

IO_L22P_6

IO_L22N_6

IO_L24P_6

IO_L24N_6

IO_L43P_6

IO_L43N_6

IO_L45P_6

IO_L45N_6/VREF_6

IO_L46P_6

IO_L46N_6

IO_L48P_6

IO_L48N_6

IO_L49P_6

IO_L49N_6

IO_L51P_6

IO_L51N_6/VREF_6

IO_L52P_6

IO_L52N_6

IO_L54P_6

IO_L54N_6

IO_L67P_6

IO_L67N_6

IO_L69P_6

IO_L69N_6/VREF_6

IO_L70P_6

IO_L70N_6

IO_L72P_6

IO_L72N_6

IO_L73P_6

IO_L73N_6

IO_L91P_6

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L91N_6

IO_L93P_6

IO_L93N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L91P_7

IO_L91N_7

IO_L73P_7

IO_L73N_7

IO_L72P_7

IO_L72N_7

IO_L70P_7

IO_L70N_7

IO_L69P_7/VREF_7

IO_L69N_7

IO_L67P_7

IO_L67N_7

IO_L54P_7

IO_L54N_7

IO_L52P_7

IO_L52N_7

IO_L51P_7/VREF_7

IO_L51N_7

IO_L49P_7

IO_L49N_7

IO_L48P_7

IO_L48N_7

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L46P_7

IO_L46N_7

IO_L45P_7/VREF_7

IO_L45N_7

IO_L43P_7

IO_L43N_7

IO_L24P_7

IO_L24N_7

IO_L22P_7

IO_L22N_7

IO_L21P_7/VREF_7

IO_L21N_7

IO_L19P_7

IO_L19N_7

IO_L06P_7

IO_L06N_7

IO_L04P_7

IO_L04N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

J12

VCCO_0

J11

VCCO_0

J10

VCCO_0

F11

VCCO_0

B11

VCCO_1

J15

VCCO_1

J14

VCCO_1

J13

VCCO_1

F14

VCCO_1

C19

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_1

B14

VCCO_2

M16

VCCO_2

L23

VCCO_2

L19

VCCO_2

L16

VCCO_2

K16

VCCO_2

F22

VCCO_3

W22

VCCO_3

R16

VCCO_3

P23

VCCO_3

P19

VCCO_3

P16

VCCO_3

N16

VCCO_4

AC14

VCCO_4

AB19

VCCO_4

W14

VCCO_4

T15

VCCO_4

T14

VCCO_4

T13

VCCO_5

AC11

VCCO_5

AB6

VCCO_5

W11

VCCO_5

T12

VCCO_5

T11

VCCO_5

T10

VCCO_6

VCCO_7

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_7

CCLK

AB23

PROG_B

DONE

AB21

AC4

AB4

AD3

HSWAP_EN

TCK

C23

TDI

TDO

C24

TMS

C21

PWRDWN_B

AC21

DXN

DXP

VBATT

B21

RSVD

A22

VCCAUX

AD13

VCCAUX

AC22

VCCAUX

AC3

VCCAUX

M24

VCCAUX

B22

VCCAUX

A12

VCCINT

U17

VCCINT

T16

VCCINT

R15

VCCINT

R14

VCCINT

R13

VCCINT

R12

VCCINT

R11

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCINT

R10

VCCINT

P15

VCCINT

P10

VCCINT

N15

VCCINT

N10

VCCINT

M15

VCCINT

M10

VCCINT

L15

VCCINT

L10

VCCINT

K15

VCCINT

K14

VCCINT

K13

VCCINT

K12

VCCINT

K11

VCCINT

K10

VCCINT

J16

VCCINT

H17

VCCINT

GND

AD24

GND

AD23

GND

AD18

GND

AD7

GND

AD2

GND

AD1

GND

AC24

GND

AC23

GND

AC2

GND

AC1

GND

AB22

GND

AB3

GND

AA21

GND

AA15

GND

AA10

GND

AA4

GND

Y20

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

W19

GND

V24

GND

V18

GND

R21

GND

P14

GND

P13

GND

P12

GND

P11

GND

N14

GND

N13

GND

N12

GND

N11

GND

M14

GND

M13

GND

M12

GND

M11

GND

L14

GND

L13

GND

L12

GND

L11

GND

K21

GND

G24

GND

G18

GND

F19

GND

E20

GND

D21

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

D15

GND

D10

GND

C22

GND

B24

GND

B23

GND

A24

GND

A23

GND

A18

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 9: BG575 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in XC2V1000

No Connect in XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

BG575 Standard BGA Package Specifications (1.27mm pitch)

Figure 5: BG575 Standard BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

BG728 Standard BGA Package

As shown in

Table 10

, XC2V3000 Virtex-II devices are available in the BG728 BGA package. Following this table are the

BG728 Standard BGA Package Specifications (1.27mm pitch)

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

IO_L01N_0

IO_L01P_0

IO_L02N_0

IO_L02P_0

IO_L03N_0/VRP_0

IO_L03P_0/VRN_0

IO_L04N_0/VREF_0

IO_L04P_0

IO_L05N_0

IO_L05P_0

IO_L06N_0

IO_L06P_0

IO_L19N_0

IO_L19P_0

IO_L21N_0

IO_L21P_0/VREF_0

IO_L22N_0

IO_L22P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0/VREF_0

IO_L28N_0

IO_L28P_0

IO_L30N_0

IO_L30P_0

IO_L49N_0

IO_L49P_0

IO_L51N_0

G10

IO_L51P_0/VREF_0

H10

IO_L52N_0

F10

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52P_0

E10

IO_L54N_0

D10

IO_L54P_0

C10

IO_L67N_0

B10

IO_L67P_0

A10

IO_L69N_0

G11

IO_L69P_0/VREF_0

H11

IO_L70N_0

F11

IO_L70P_0

F12

IO_L72N_0

D11

IO_L72P_0

C11

IO_L73N_0

B11

IO_L73P_0

A11

IO_L75N_0

H12

IO_L75P_0/VREF_0

J12

IO_L76N_0

E12

IO_L76P_0

D12

IO_L78N_0

B12

IO_L78P_0

A12

IO_L91N_0/VREF_0

J13

IO_L91P_0

H13

IO_L92N_0

G13

IO_L92P_0

F13

IO_L93N_0

E13

IO_L93P_0

D13

IO_L94N_0/VREF_0

B13

IO_L94P_0

A13

IO_L95N_0/GCLK7P

C13

IO_L95P_0/GCLK6S

C14

IO_L96N_0/GCLK5P

F14

IO_L96P_0/GCLK4S

E14

IO_L96N_1/GCLK3P

G14

IO_L96P_1/GCLK2S

H14

IO_L95N_1/GCLK1P

A15

IO_L95P_1/GCLK0S

B15

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L94N_1

C15

IO_L94P_1/VREF_1

D15

IO_L93N_1

E15

IO_L93P_1

F15

IO_L92N_1

G15

IO_L92P_1

H15

IO_L91N_1

J15

IO_L91P_1/VREF_1

J16

IO_L78N_1

A16

IO_L78P_1

B16

IO_L76N_1

D16

IO_L76P_1

E16

IO_L75N_1/VREF_1

F16

IO_L75P_1

F17

IO_L73N_1

H16

IO_L73P_1

H17

IO_L72N_1

A17

IO_L72P_1

B17

IO_L70N_1

C17

IO_L70P_1

D17

IO_L69N_1/VREF_1

G18

IO_L69P_1

G17

IO_L67N_1

A18

IO_L67P_1

B18

IO_L54N_1

C18

IO_L54P_1

D18

IO_L52N_1

E18

IO_L52P_1

F18

IO_L51N_1/VREF_1

H19

IO_L51P_1

H18

IO_L49N_1

A19

IO_L49P_1

A20

IO_L30N_1

B19

IO_L30P_1

C19

IO_L28N_1

D19

IO_L28P_1

E19

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L27N_1/VREF_1

F19

IO_L27P_1

G19

IO_L25N_1

J19

IO_L25P_1

J20

IO_L24N_1

C20

IO_L24P_1

C21

IO_L22N_1

D20

IO_L22P_1

E21

IO_L21N_1/VREF_1

E20

IO_L21P_1

F20

IO_L19N_1

A21

IO_L19P_1

B21

IO_L06N_1

A22

IO_L06P_1

B22

IO_L05N_1

C22

IO_L05P_1

C23

IO_L04N_1

D22

IO_L04P_1/VREF_1

E22

IO_L03N_1/VRP_1

A23

IO_L03P_1/VRN_1

B23

IO_L02N_1

A24

IO_L02P_1

B24

IO_L01N_1

A25

IO_L01P_1

B25

IO_L01N_2

C27

IO_L01P_2

D27

IO_L02N_2/VRP_2

D25

IO_L02P_2/VRN_2

D26

IO_L03N_2

E24

IO_L03P_2/VREF_2

E25

IO_L04N_2

E26

IO_L04P_2

E27

IO_L06N_2

F23

IO_L06P_2

F24

IO_L19N_2

F25

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L19P_2

F26

IO_L21N_2

F27

IO_L21P_2/VREF_2

G27

IO_L22N_2

G23

IO_L22P_2

H23

IO_L24N_2

G25

IO_L24P_2

G26

IO_L25N_2

H21

IO_L25P_2

J21

IO_L27N_2

H22

IO_L27P_2/VREF_2

J22

IO_L28N_2

H24

IO_L28P_2

H25

IO_L30N_2

H27

IO_L30P_2

J27

IO_L43N_2

J23

IO_L43P_2

J24

IO_L45N_2

J25

IO_L45P_2/VREF_2

J26

IO_L46N_2

K20

IO_L46P_2

K21

IO_L48N_2

K22

IO_L48P_2

K23

IO_L49N_2

K24

IO_L49P_2

K25

IO_L51N_2

K26

IO_L51P_2/VREF_2

K27

IO_L52N_2

L20

IO_L52P_2

M20

IO_L54N_2

L21

IO_L54P_2

L22

IO_L67N_2

L24

IO_L67P_2

L25

IO_L69N_2

L26

IO_L69P_2/VREF_2

L27

IO_L70N_2

M19

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L70P_2

N19

IO_L72N_2

M22

IO_L72P_2

M23

IO_L73N_2

M24

IO_L73P_2

N24

IO_L75N_2

M26

IO_L75P_2/VREF_2

M27

IO_L76N_2

N20

IO_L76P_2

N21

IO_L78N_2

N22

IO_L78P_2

N23

IO_L91N_2

N25

IO_L91P_2

P25

IO_L93N_2

N26

IO_L93P_2/VREF_2

N27

IO_L94N_2

P20

IO_L94P_2

P21

IO_L96N_2

P22

IO_L96P_2

P23

IO_L96N_3

R27

IO_L96P_3

R26

IO_L94N_3

R25

IO_L94P_3

R24

IO_L93N_3/VREF_3

R23

IO_L93P_3

T23

IO_L91N_3

R22

IO_L91P_3

R21

IO_L78N_3

R20

IO_L78P_3

R19

IO_L76N_3

T27

IO_L76P_3

T26

IO_L75N_3/VREF_3

T24

IO_L75P_3

U24

IO_L73N_3

T22

IO_L73P_3

U22

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L72N_3

T20

IO_L72P_3

T19

IO_L70N_3

U27

IO_L70P_3

U26

IO_L69N_3/VREF_3

U25

IO_L69P_3

V25

IO_L67N_3

U21

IO_L67P_3

U20

IO_L54N_3

V27

IO_L54P_3

V26

IO_L52N_3

V24

IO_L52P_3

V23

IO_L51N_3/VREF_3

V22

IO_L51P_3

W22

IO_L49N_3

V21

IO_L49P_3

V20

IO_L48N_3

W27

IO_L48P_3

Y27

IO_L46N_3

W26

IO_L46P_3

W25

IO_L45N_3/VREF_3

W24

IO_L45P_3

W23

IO_L43N_3

W21

IO_L43P_3

W20

IO_L28N_3

W19

IO_L28P_3

Y19

IO_L27N_3/VREF_3

Y25

IO_L27P_3

Y24

IO_L25N_3

Y23

IO_L25P_3

AA23

IO_L24N_3

Y22

IO_L24P_3

Y21

IO_L22N_3

AA27

IO_L22P_3

AB27

IO_L21N_3/VREF_3

AA26

IO_L21P_3

AA25

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L19N_3

AB26

IO_L19P_3

AB25

IO_L06N_3

AB24

IO_L06P_3

AB23

IO_L04N_3

AC27

IO_L04P_3

AC26

IO_L03N_3/VREF_3

AC25

IO_L03P_3

AC24

IO_L02N_3/VRP_3

AD27

IO_L02P_3/VRN_3

AE27

IO_L01N_3

AD26

IO_L01P_3

AD25

IO_L01N_4/BUSY/DOUT

(1)

AF25

IO_L01P_4/INIT_B

AG25

IO_L02N_4/D0/DIN

(1)

AF24

IO_L02P_4/D1

AG24

IO_L03N_4/D2/ALT_VRP_4

AD23

IO_L03P_4/D3/ALT_VRN_4

AE23

IO_L04N_4/VREF_4

AF23

IO_L04P_4

AG23

IO_L05N_4/VRP_4

AD22

IO_L05P_4/VRN_4

AE22

IO_L06N_4

AF22

IO_L06P_4

AG22

IO_L19N_4

AC21

IO_L19P_4

AB21

IO_L21N_4

AE21

IO_L21P_4/VREF_4

AE20

IO_L22N_4

AF21

IO_L22P_4

AG21

IO_L24N_4

AB20

IO_L24P_4

AA20

IO_L25N_4

AC20

IO_L25P_4

AD20

IO_L27N_4

AG20

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L27P_4/VREF_4

AG19

IO_L28N_4

AB19

IO_L28P_4

AA19

IO_L30N_4

AC19

IO_L30P_4

AD19

IO_L49N_4

AE19

IO_L49P_4

AF19

IO_L51N_4

AA18

IO_L51P_4/VREF_4

Y18

IO_L52N_4

AB18

IO_L52P_4

AC18

IO_L54N_4

AD18

IO_L54P_4

AE18

IO_L67N_4

AF18

IO_L67P_4

AG18

IO_L69N_4

AA17

IO_L69P_4/VREF_4

Y17

IO_L70N_4

AB17

IO_L70P_4

AB16

IO_L72N_4

AD17

IO_L72P_4

AE17

IO_L73N_4

AF17

IO_L73P_4

AG17

IO_L75N_4

Y16

IO_L75P_4/VREF_4

W16

IO_L76N_4

AC16

IO_L76P_4

AD16

IO_L78N_4

AF16

IO_L78P_4

AG16

IO_L91N_4/VREF_4

W15

IO_L91P_4

Y15

IO_L92N_4

AB15

IO_L92P_4

AA15

IO_L93N_4

AC15

IO_L93P_4

AD15

IO_L94N_4/VREF_4

AE15

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L94P_4

AE14

IO_L95N_4/GCLK3S

AF15

IO_L95P_4/GCLK2P

AG15

IO_L96N_4/GCLK1S

Y14

IO_L96P_4/GCLK0P

AA14

IO_L96N_5/GCLK7S

AC14

IO_L96P_5/GCLK6P

AB14

IO_L95N_5/GCLK5S

AG13

IO_L95P_5/GCLK4P

AF13

IO_L94N_5

AE13

IO_L94P_5/VREF_5

AD13

IO_L93N_5

AC13

IO_L93P_5

AB13

IO_L92N_5

AA13

IO_L92P_5

Y13

IO_L91N_5

W13

IO_L91P_5/VREF_5

W12

IO_L78N_5

AG12

IO_L78P_5

AF12

IO_L76N_5

AD12

IO_L76P_5

AC12

IO_L75N_5/VREF_5

AB12

IO_L75P_5

AB11

IO_L73N_5

Y12

IO_L73P_5

Y11

IO_L72N_5

AG11

IO_L72P_5

AF11

IO_L70N_5

AE11

IO_L70P_5

AD11

IO_L69N_5/VREF_5

AA10

IO_L69P_5

AA11

IO_L67N_5

AG10

IO_L67P_5

AF10

IO_L54N_5

AE10

IO_L54P_5

AD10

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52N_5

AC10

IO_L52P_5

AB10

IO_L51N_5/VREF_5

IO_L51P_5

Y10

IO_L49N_5

AG9

IO_L49P_5

AG8

IO_L30N_5

AF9

IO_L30P_5

AE9

IO_L28N_5

AD9

IO_L28P_5

AC9

IO_L27N_5/VREF_5

AB9

IO_L27P_5

AA9

IO_L25N_5

AE8

IO_L25P_5

AE7

IO_L24N_5

AD8

IO_L24P_5

AC8

IO_L22N_5

AB8

IO_L22P_5

AA8

IO_L21N_5/VREF_5

AG7

IO_L21P_5

AF7

IO_L19N_5

AC7

IO_L19P_5

AB7

IO_L06N_5

AG6

IO_L06P_5

AF6

IO_L05N_5/VRP_5

AE6

IO_L05P_5/VRN_5

AD6

IO_L04N_5

AG5

IO_L04P_5/VREF_5

AF5

IO_L03N_5/D4/ALT_VRP_5

AE5

IO_L03P_5/D5/ALT_VRN_5

AD5

IO_L02N_5/D6

AG4

IO_L02P_5/D7

AF4

IO_L01N_5/RDWR_B

AG3

IO_L01P_5/CS_B

AF3

IO_L01P_6

AE1

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L01N_6

AD1

IO_L02P_6/VRN_6

AD3

IO_L02N_6/VRP_6

AD2

IO_L03P_6

AC4

IO_L03N_6/VREF_6

AC3

IO_L04P_6

AC2

IO_L04N_6

AC1

IO_L06P_6

AB5

IO_L06N_6

AB4

IO_L19P_6

AB3

IO_L19N_6

AB2

IO_L21P_6

AB1

IO_L21N_6/VREF_6

AA1

IO_L22P_6

AA5

IO_L22N_6

AA6

IO_L24P_6

AA3

IO_L24N_6

AA2

IO_L25P_6

IO_L25N_6

IO_L27P_6

IO_L27N_6/VREF_6

IO_L28P_6

IO_L28N_6

IO_L43P_6

IO_L43N_6

IO_L45P_6

IO_L45N_6/VREF_6

IO_L46P_6

IO_L46N_6

IO_L48P_6

IO_L48N_6

IO_L49P_6

IO_L49N_6

IO_L51P_6

IO_L51N_6/VREF_6

IO_L52P_6

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L52N_6

IO_L54P_6

IO_L54N_6

IO_L67P_6

IO_L67N_6

IO_L69P_6

IO_L69N_6/VREF_6

IO_L70P_6

IO_L70N_6

IO_L72P_6

IO_L72N_6

IO_L73P_6

IO_L73N_6

IO_L75P_6

IO_L75N_6/VREF_6

IO_L76P_6

IO_L76N_6

IO_L78P_6

IO_L78N_6

IO_L91P_6

IO_L91N_6

IO_L93P_6

IO_L93N_6/VREF_6

IO_L94P_6

IO_L94N_6

IO_L96P_6

IO_L96N_6

IO_L96P_7

IO_L96N_7

IO_L94P_7

IO_L94N_7

IO_L93P_7/VREF_7

IO_L93N_7

IO_L91P_7

IO_L91N_7

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L78P_7

IO_L78N_7

IO_L76P_7

IO_L76N_7

IO_L75P_7/VREF_7

IO_L75N_7

IO_L73P_7

IO_L73N_7

IO_L72P_7

IO_L72N_7

IO_L70P_7

IO_L70N_7

IO_L69P_7/VREF_7

IO_L69N_7

IO_L67P_7

IO_L67N_7

IO_L54P_7

IO_L54N_7

IO_L52P_7

IO_L52N_7

IO_L51P_7/VREF_7

IO_L51N_7

IO_L49P_7

IO_L49N_7

IO_L48P_7

IO_L48N_7

IO_L46P_7

IO_L46N_7

IO_L45P_7/VREF_7

IO_L45N_7

IO_L43P_7

IO_L43N_7

IO_L30P_7

IO_L30N_7

IO_L28P_7

IO_L28N_7

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

IO_L27P_7/VREF_7

IO_L27N_7

IO_L25P_7

IO_L25N_7

IO_L24P_7

IO_L24N_7

IO_L22P_7

IO_L22N_7

IO_L21P_7/VREF_7

IO_L21N_7

IO_L19P_7

IO_L19N_7

IO_L06P_7

IO_L06N_7

IO_L04P_7

IO_L04N_7

IO_L03P_7/VREF_7

IO_L03N_7

IO_L02P_7/VRN_7

IO_L02N_7/VRP_7

IO_L01P_7

IO_L01N_7

VCCO_0

K13

VCCO_0

K12

VCCO_0

K11

VCCO_0

J11

VCCO_0

J10

VCCO_0

G12

VCCO_0

C12

VCCO_1

K17

VCCO_1

K16

VCCO_1

K15

VCCO_1

J18

VCCO_1

J17

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_1

G16

VCCO_1

D21

VCCO_1

C16

VCCO_2

N18

VCCO_2

M25

VCCO_2

M21

VCCO_2

M18

VCCO_2

L19

VCCO_2

L18

VCCO_2

K19

VCCO_2

G24

VCCO_3

AA24

VCCO_3

V19

VCCO_3

U19

VCCO_3

U18

VCCO_3

T25

VCCO_3

T21

VCCO_3

T18

VCCO_3

R18

VCCO_4

AE16

VCCO_4

AD21

VCCO_4

AA16

VCCO_4

W18

VCCO_4

W17

VCCO_4

V17

VCCO_4

V16

VCCO_4

V15

VCCO_5

AE12

VCCO_5

AD7

VCCO_5

AA12

VCCO_5

W11

VCCO_5

W10

VCCO_5

V13

VCCO_5

V12

VCCO_5

V11

VCCO_6

AA4

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCO_6

U10

VCCO_6

T10

VCCO_6

R10

VCCO_7

M10

VCCO_7

L10

VCCO_7

N10

CCLK

AA22

PROG_B

DONE

AC22

AC6

AE4

HSWAP_EN

TCK

G20

TDI

TDO

G22

TMS

F21

PWRDWN_B

AE24

DXN

DXP

VBATT

D23

RSVD

C24

VCCAUX

AF14

VCCAUX

AE26

VCCAUX

AE2

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCAUX

P26

VCCAUX

C26

VCCAUX

B14

VCCINT

V18

VCCINT

V14

VCCINT

V10

VCCINT

U17

VCCINT

U16

VCCINT

U15

VCCINT

U14

VCCINT

U13

VCCINT

U12

VCCINT

U11

VCCINT

T17

VCCINT

T11

VCCINT

R17

VCCINT

R11

VCCINT

P18

VCCINT

P17

VCCINT

P11

VCCINT

P10

VCCINT

N17

VCCINT

N11

VCCINT

M17

VCCINT

M11

VCCINT

L17

VCCINT

L16

VCCINT

L15

VCCINT

L14

VCCINT

L13

VCCINT

L12

VCCINT

L11

VCCINT

K18

VCCINT

K14

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

VCCINT

K10

GND

AG27

GND

AG26

GND

AG14

GND

AG2

GND

AG1

GND

AF27

GND

AF26

GND

AF20

GND

AF8

GND

AF2

GND

AF1

GND

AE25

GND

AE3

GND

AD24

GND

AD14

GND

AD4

GND

AC23

GND

AC17

GND

AC11

GND

AC5

GND

AB22

GND

AB6

GND

AA21

GND

AA7

GND

Y26

GND

Y20

GND

W14

GND

U23

GND

T16

GND

T15

GND

T14

GND

T13

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

T12

GND

R16

GND

R15

GND

R14

GND

R13

GND

R12

GND

P27

GND

P24

GND

P19

GND

P16

GND

P15

GND

P14

GND

P13

GND

P12

GND

N16

GND

N15

GND

N14

GND

N13

GND

N12

GND

M16

GND

M15

GND

M14

GND

M13

GND

M12

GND

L23

GND

J14

GND

H26

GND

H20

GND

G21

GND

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

GND

F22

GND

E23

GND

E17

GND

E11

GND

D24

GND

D14

GND

C25

GND

B27

GND

B26

GND

B20

GND

A27

GND

A26

GND

A14

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 10: BG728 BGA -- XC2V3000

Bank

Pin Description

Pin Number

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

BG728 Standard BGA Package Specifications (1.27mm pitch)

Figure 6: BG728 Standard BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

FF896 Flip-Chip Fine-Pitch BGA Package

As shown in

Table 11

, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the FF896 flip-chip fine-pitch

BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the
XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the

FF896 Flip-Chip

Fine-Pitch BGA Package Specifications (1.00mm pitch)

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

IO_L01N_0

B27

IO_L01P_0

A27

IO_L02N_0

F24

IO_L02P_0

E24

IO_L03N_0/VRP_0

C26

IO_L03P_0/VRN_0

C25

IO_L04N_0/VREF_0

A26

IO_L04P_0

A25

IO_L05N_0

F23

IO_L05P_0

F22

IO_L06N_0

C24

IO_L06P_0

D25

IO_L19N_0

A24

IO_L19P_0

B25

IO_L20N_0

G22

IO_L20P_0

G21

IO_L21N_0

D24

IO_L21P_0/VREF_0

D23

IO_L22N_0

B23

IO_L22P_0

B24

IO_L23N_0

H21

IO_L23P_0

H20

IO_L24N_0

E22

IO_L24P_0

E23

IO_L49N_0

A22

IO_L49P_0

B22

IO_L50N_0

F21

IO_L50P_0

F20

IO_L51N_0

C23

IO_L51P_0/VREF_0

C22

IO_L52N_0

B20

IO_L52P_0

B21

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

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IO_L53N_0

G20

IO_L53P_0

G19

IO_L54N_0

D21

IO_L54P_0

D22

IO_L67N_0

E20

IO_L67P_0

E21

IO_L68N_0

H19

IO_L68P_0

H18

IO_L69N_0

D20

IO_L69P_0/VREF_0

D19

IO_L70N_0

A20

IO_L70P_0

A21

IO_L71N_0

F19

IO_L71P_0

F18

IO_L72N_0

C19

IO_L72P_0

C20

IO_L73N_0

B18

IO_L73P_0

B19

IO_L74N_0

G18

IO_L74P_0

H17

IO_L75N_0

E18

IO_L75P_0/VREF_0

D18

IO_L76N_0

A18

IO_L76P_0

A19

IO_L77N_0

J17

IO_L77P_0

J16

IO_L78N_0

E16

IO_L78P_0

E17

IO_L91N_0/VREF_0

B17

IO_L91P_0

B16

IO_L92N_0

F17

IO_L92P_0

F16

IO_L93N_0

D16

IO_L93P_0

D17

IO_L94N_0/VREF_0

A17

IO_L94P_0

A16

IO_L95N_0/GCLK7P

H16

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L95P_0/GCLK6S

G16

IO_L96N_0/GCLK5P

C17

IO_L96P_0/GCLK4S

C16

IO_L96N_1/GCLK3P

C15

IO_L96P_1/GCLK2S

C14

IO_L95N_1/GCLK1P

F15

IO_L95P_1/GCLK0S

F14

IO_L94N_1

B15

IO_L94P_1/VREF_1

B14

IO_L93N_1

D14

IO_L93P_1

D15

IO_L92N_1

G15

IO_L92P_1

H15

IO_L91N_1

A14

IO_L91P_1/VREF_1

A13

IO_L78N_1

E14

IO_L78P_1

E15

IO_L77N_1

J15

IO_L77P_1

J14

IO_L76N_1

B12

IO_L76P_1

B13

IO_L75N_1/VREF_1

D13

IO_L75P_1

E13

IO_L74N_1

H14

IO_L74P_1

H13

IO_L73N_1

A11

IO_L73P_1

A12

IO_L72N_1

C11

IO_L72P_1

C12

IO_L71N_1

F13

IO_L71P_1

F12

IO_L70N_1

B10

IO_L70P_1

B11

IO_L69N_1/VREF_1

D12

IO_L69P_1

D11

IO_L68N_1

G13

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L68P_1

G12

IO_L67N_1

IO_L67P_1

A10

IO_L54N_1

E10

IO_L54P_1

E11

IO_L53N_1

H12

IO_L53P_1

H11

IO_L52N_1

IO_L52P_1

D10

IO_L51N_1/VREF_1

IO_L51P_1

IO_L50N_1

F11

IO_L50P_1

F10

IO_L49N_1

IO_L49P_1

IO_L24N_1

IO_L24P_1

IO_L23N_1

G11

IO_L23P_1

H10

IO_L22N_1

IO_L22P_1

IO_L21N_1/VREF_1

IO_L21P_1

IO_L20N_1

G10

IO_L20P_1

IO_L19N_1

IO_L19P_1

IO_L06N_1

IO_L06P_1

IO_L05N_1

IO_L05P_1

IO_L04N_1

IO_L04P_1/VREF_1

IO_L03N_1/VRP_1

IO_L03P_1/VRN_1

IO_L02N_1

IO_L02P_1

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L01N_1

IO_L01P_1

IO_L01N_2

IO_L01P_2

IO_L02N_2/VRP_2

IO_L02P_2/VRN_2

IO_L03N_2

IO_L03P_2/VREF_2

IO_L04N_2

IO_L04P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2/VREF_2

IO_L22N_2

IO_L22P_2

IO_L23N_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L43N_2

IO_L43P_2

IO_L44N_2

IO_L44P_2

IO_L45N_2

IO_L45P_2/VREF_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

IO_L48N_2

IO_L48P_2

IO_L49N_2

IO_L49P_2

IO_L50N_2

IO_L50P_2

IO_L51N_2

IO_L51P_2/VREF_2

IO_L52N_2

IO_L52P_2

IO_L53N_2

IO_L53P_2

IO_L54N_2

IO_L54P_2

IO_L67N_2

IO_L67P_2

IO_L68N_2

IO_L68P_2

IO_L69N_2

IO_L69P_2/VREF_2

IO_L70N_2

IO_L70P_2

IO_L71N_2

IO_L71P_2

IO_L72N_2

IO_L72P_2

IO_L73N_2

IO_L73P_2

IO_L74N_2

IO_L74P_2

IO_L75N_2

IO_L75P_2/VREF_2

IO_L76N_2

IO_L76P_2

IO_L77N_2

IO_L77P_2

IO_L78N_2

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

100

IO_L78P_2

IO_L91N_2

IO_L91P_2

IO_L92N_2

IO_L92P_2

IO_L93N_2

IO_L93P_2/VREF_2

IO_L94N_2

IO_L94P_2

IO_L95N_2

IO_L95P_2

IO_L96N_2

IO_L96P_2

IO_L96N_3

IO_L96P_3

IO_L95N_3

IO_L95P_3

IO_L94N_3

IO_L94P_3

IO_L93N_3/VREF_3

IO_L93P_3

IO_L92N_3

IO_L92P_3

IO_L91N_3

IO_L91P_3

IO_L78N_3

IO_L78P_3

IO_L77N_3

IO_L77P_3

IO_L76N_3

IO_L76P_3

IO_L75N_3/VREF_3

IO_L75P_3

IO_L74N_3

IO_L74P_3

IO_L73N_3

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

101

IO_L73P_3

IO_L72N_3

IO_L72P_3

IO_L71N_3

IO_L71P_3

IO_L70N_3

IO_L70P_3

IO_L69N_3/VREF_3

IO_L69P_3

IO_L68N_3

AA1

IO_L68P_3

AB1

IO_L67N_3

IO_L67P_3

AA4

IO_L54N_3

AA6

IO_L54P_3

IO_L53N_3

AA2

IO_L53P_3

AB2

IO_L52N_3

IO_L52P_3

AA5

IO_L51N_3/VREF_3

IO_L51P_3

AA8

IO_L50N_3

AC2

IO_L50P_3

AD2

IO_L49N_3

IO_L49P_3

AA7

IO_L48N_3

AC6

IO_L48P_3

AB6

IO_L47N_3

AD1

IO_L47P_3

AE1

IO_L46N_3

AB3

IO_L46P_3

AC3

IO_L45N_3/VREF_3

AB7

IO_L45P_3

AC7

IO_L44N_3

AB4

IO_L44P_3

AC4

IO_L43N_3

AB5

IO_L43P_3

AC5

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

102

IO_L24N_3

AC8

IO_L24P_3

AB8

IO_L23N_3

AE2

IO_L23P_3

AF3

IO_L22N_3

AD3

IO_L22P_3

AE3

IO_L21N_3/VREF_3

AD6

IO_L21P_3

AD7

IO_L20N_3

AF1

IO_L20P_3

AG1

IO_L19N_3

AD4

IO_L19P_3

AE4

IO_L06N_3

AD8

IO_L06P_3

AE7

IO_L05N_3

AG2

IO_L05P_3

AH2

IO_L04N_3

AD5

IO_L04P_3

AE5

IO_L03N_3/VREF_3

AC9

IO_L03P_3

AD9

IO_L02N_3/VRP_3

AH1

IO_L02P_3/VRN_3

AJ1

IO_L01N_3

AF4

IO_L01P_3

AG3

IO_L01N_4/BUSY/DOUT

(1)

AK2

IO_L01P_4/INIT_B

AJ3

IO_L02N_4/D0/DIN

(1)

AE8

IO_L02P_4/D1

AF9

IO_L03N_4/D2/ALT_VRP_4

AH5

IO_L03P_4/D3/ALT_VRN_4

AH6

IO_L04N_4/VREF_4

AJ4

IO_L04P_4

AK4

IO_L05N_4/VRP_4

AC10

IO_L05P_4/VRN_4

AC11

IO_L06N_4

AH7

IO_L06P_4

AG6

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

103

IO_L19N_4

AK6

IO_L19P_4

AK5

IO_L20N_4

AE9

IO_L20P_4

AE10

IO_L21N_4

AF7

IO_L21P_4/VREF_4

AF8

IO_L22N_4

AK7

IO_L22P_4

AJ6

IO_L23N_4

AD10

IO_L23P_4

AD11

IO_L24N_4

AG8

IO_L24P_4

AG7

IO_L49N_4

AJ8

IO_L49P_4

AJ7

IO_L50N_4

AE11

IO_L50P_4

AE12

IO_L51N_4

AG9

IO_L51P_4/VREF_4

AG10

IO_L52N_4

AK9

IO_L52P_4

AJ9

IO_L53N_4

AH8

IO_L53P_4

AH9

IO_L54N_4

AF11

IO_L54P_4

AF10

IO_L67N_4

AJ11

IO_L67P_4

AJ10

IO_L68N_4

AC12

IO_L68P_4

AC13

IO_L69N_4

AG11

IO_L69P_4/VREF_4

AG12

IO_L70N_4

AK11

IO_L70P_4

AK10

IO_L71N_4

AD12

IO_L71P_4

AD13

IO_L72N_4

AH12

IO_L72P_4

AH11

IO_L73N_4

AJ13

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

104

IO_L73P_4

AJ12

IO_L74N_4

AE13

IO_L74P_4

AE14

IO_L75N_4

AF13

IO_L75P_4/VREF_4

AG13

IO_L76N_4

AK13

IO_L76P_4

AK12

IO_L77N_4

AB14

IO_L77P_4

AB15

IO_L78N_4

AF15

IO_L78P_4

AF14

IO_L91N_4/VREF_4

AJ14

IO_L91P_4

AJ15

IO_L92N_4

AC14

IO_L92P_4

AC15

IO_L93N_4

AG15

IO_L93P_4

AG14

IO_L94N_4/VREF_4

AK14

IO_L94P_4

AK15

IO_L95N_4/GCLK3S

AD15

IO_L95P_4/GCLK2P

AE15

IO_L96N_4/GCLK1S

AH14

IO_L96P_4/GCLK0P

AH15

IO_L96N_5/GCLK7S

AH16

IO_L96P_5/GCLK6P

AH17

IO_L95N_5/GCLK5S

AE16

IO_L95P_5/GCLK4P

AD16

IO_L94N_5

AJ16

IO_L94P_5/VREF_5

AJ17

IO_L93N_5

AG17

IO_L93P_5

AG16

IO_L92N_5

AC16

IO_L92P_5

AC17

IO_L91N_5

AK17

IO_L91P_5/VREF_5

AK18

IO_L78N_5

AF17

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

105

IO_L78P_5

AF16

IO_L77N_5

AB16

IO_L77P_5

AB17

IO_L76N_5

AJ19

IO_L76P_5

AJ18

IO_L75N_5/VREF_5

AG18

IO_L75P_5

AF18

IO_L74N_5

AE17

IO_L74P_5

AE18

IO_L73N_5

AK20

IO_L73P_5

AK19

IO_L72N_5

AH20

IO_L72P_5

AH19

IO_L71N_5

AD18

IO_L71P_5

AD19

IO_L70N_5

AJ21

IO_L70P_5

AJ20

IO_L69N_5/VREF_5

AG19

IO_L69P_5

AG20

IO_L68N_5

AC18

IO_L68P_5

AC19

IO_L67N_5

AK22

IO_L67P_5

AK21

IO_L54N_5

AF21

IO_L54P_5

AF20

IO_L53N_5

AH22

IO_L53P_5

AH23

IO_L52N_5

AG22

IO_L52P_5

AG21

IO_L51N_5/VREF_5

AF22

IO_L51P_5

AF23

IO_L50N_5

AE19

IO_L50P_5

AE20

IO_L49N_5

AJ23

IO_L49P_5

AJ22

IO_L24N_5

AF24

IO_L24P_5

AG23

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

106

IO_L23N_5

AD20

IO_L23P_5

AD21

IO_L22N_5

AK25

IO_L22P_5

AK24

IO_L21N_5/VREF_5

AH24

IO_L21P_5

AH25

IO_L20N_5

AE21

IO_L20P_5

AD22

IO_L19N_5

AJ25

IO_L19P_5

AJ24

IO_L06N_5

AG25

IO_L06P_5

AG24

IO_L05N_5/VRP_5

AC20

IO_L05P_5/VRN_5

AC21

IO_L04N_5

AK26

IO_L04P_5/VREF_5

AK27

IO_L03N_5/D4/ALT_VRP_5

AH26

IO_L03P_5/D5/ALT_VRN_5

AJ27

IO_L02N_5/D6

AE22

IO_L02P_5/D7

AE23

IO_L01N_5/RDWR_B

AJ28

IO_L01P_5/CS_B

AK29

IO_L01P_6

AC22

IO_L01N_6

AB23

IO_L02P_6/VRN_6

AG28

IO_L02N_6/VRP_6

AF28

IO_L03P_6

AJ30

IO_L03N_6/VREF_6

AH30

IO_L04P_6

AD23

IO_L04N_6

AC23

IO_L05P_6

AF27

IO_L05N_6

AE27

IO_L06P_6

AG29

IO_L06N_6

AH29

IO_L19P_6

AE24

IO_L19N_6

AD24

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

107

IO_L20P_6

AE26

IO_L20N_6

AD26

IO_L21P_6

AG30

IO_L21N_6/VREF_6

AF30

IO_L22P_6

AD25

IO_L22N_6

AC25

IO_L23P_6

AE28

IO_L23N_6

AD28

IO_L24P_6

AD29

IO_L24N_6

AE29

IO_L43P_6

AC24

IO_L43N_6

AB24

IO_L44P_6

AD27

IO_L44N_6

AC27

IO_L45P_6

AC26

IO_L45N_6/VREF_6

AB26

IO_L46P_6

AA23

IO_L46N_6

Y23

IO_L47P_6

AC28

IO_L47N_6

AB28

IO_L48P_6

AD30

IO_L48N_6

AE30

IO_L49P_6

AB25

IO_L49N_6

AA25

IO_L50P_6

AA24

IO_L50N_6

Y24

IO_L51P_6

AC29

IO_L51N_6/VREF_6

AB30

IO_L52P_6

Y25

IO_L52N_6

W25

IO_L53P_6

AB27

IO_L53N_6

AA27

IO_L54P_6

AA29

IO_L54N_6

AB29

IO_L67P_6

W23

IO_L67N_6

V23

IO_L68P_6

AA26

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

108

IO_L68N_6

Y26

IO_L69P_6

AA30

IO_L69N_6/VREF_6

Y30

IO_L70P_6

W24

IO_L70N_6

V24

IO_L71P_6

Y27

IO_L71N_6

W27

IO_L72P_6

W28

IO_L72N_6

Y28

IO_L73P_6

V25

IO_L73N_6

U25

IO_L74P_6

V26

IO_L74N_6

V27

IO_L75P_6

Y29

IO_L75N_6/VREF_6

W29

IO_L76P_6

U22

IO_L76N_6

T22

IO_L77P_6

U26

IO_L77N_6

T26

IO_L78P_6

V30

IO_L78N_6

W30

IO_L91P_6

U23

IO_L91N_6

T23

IO_L92P_6

U27

IO_L92N_6

T27

IO_L93P_6

V29

IO_L93N_6/VREF_6

U29

IO_L94P_6

T24

IO_L94N_6

T25

IO_L95P_6

U28

IO_L95N_6

T28

IO_L96P_6

T30

IO_L96N_6

U30

IO_L96P_7

P28

IO_L96N_7

R28

IO_L95P_7

R25

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

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Module 4 of 4

Product Specification

1-800-255-7778

109

IO_L95N_7

R24

IO_L94P_7

R29

IO_L94N_7

T29

IO_L93P_7/VREF_7

R27

IO_L93N_7

P27

IO_L92P_7

R23

IO_L92N_7

P23

IO_L91P_7

N30

IO_L91N_7

P30

IO_L78P_7

P26

IO_L78N_7

R26

IO_L77P_7

R22

IO_L77N_7

P22

IO_L76P_7

N29

IO_L76N_7

P29

IO_L75P_7/VREF_7

N27

IO_L75N_7

N26

IO_L74P_7

P25

IO_L74N_7

N25

IO_L73P_7

L30

IO_L73N_7

M30

IO_L72P_7

L28

IO_L72N_7

M28

IO_L71P_7

N24

IO_L71N_7

M24

IO_L70P_7

L29

IO_L70N_7

M29

IO_L69P_7/VREF_7

M27

IO_L69N_7

L27

IO_L68P_7

N23

IO_L68N_7

M23

IO_L67P_7

J30

IO_L67N_7

K30

IO_L54P_7

K26

IO_L54N_7

L26

IO_L53P_7

M25

IO_L53N_7

L25

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

110

IO_L52P_7

J29

IO_L52N_7

K29

IO_L51P_7/VREF_7

K27

IO_L51N_7

J27

IO_L50P_7

L24

IO_L50N_7

K24

IO_L49P_7

H27

IO_L49N_7

J28

IO_L48P_7

H26

IO_L48N_7

J26

IO_L47P_7

K25

IO_L47N_7

J25

IO_L46P_7

H28

IO_L46N_7

H29

IO_L45P_7/VREF_7

G28

IO_L45N_7

F28

IO_L44P_7

L23

IO_L44N_7

K23

IO_L43P_7

F30

IO_L43N_7

G30

IO_L24P_7

F26

IO_L24N_7

G27

IO_L23P_7

J24

IO_L23N_7

H24

IO_L22P_7

F29

IO_L22N_7

G29

IO_L21P_7/VREF_7

G26

IO_L21N_7

G25

IO_L20P_7

H25

IO_L20N_7

G24

IO_L19P_7

D30

IO_L19N_7

E30

IO_L06P_7

E27

IO_L06N_7

F27

IO_L05P_7

J23

IO_L05N_7

H22

IO_L04P_7

C29

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

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Module 4 of 4

Product Specification

1-800-255-7778

111

IO_L04N_7

D29

IO_L03P_7/VREF_7

E28

IO_L03N_7

D28

IO_L02P_7/VRN_7

H23

IO_L02N_7/VRP_7

G23

IO_L01P_7

B30

IO_L01N_7

C30

VCCO_0

K20

VCCO_0

K19

VCCO_0

K18

VCCO_0

K17

VCCO_0

K16

VCCO_0

J21

VCCO_0

J20

VCCO_0

J19

VCCO_0

J18

VCCO_0

C18

VCCO_0

B26

VCCO_1

K15

VCCO_1

K14

VCCO_1

K13

VCCO_1

K12

VCCO_1

K11

VCCO_1

J13

VCCO_1

J12

VCCO_1

J11

VCCO_1

J10

VCCO_1

C13

VCCO_1

VCCO_2

R10

VCCO_2

P10

VCCO_2

N10

VCCO_2

M10

VCCO_2

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

112

VCCO_2

L10

VCCO_2

VCCO_3

AF2

VCCO_3

AA9

VCCO_3

Y10

VCCO_3

W10

VCCO_3

V10

VCCO_3

U10

VCCO_3

T10

VCCO_4

AJ5

VCCO_4

AH13

VCCO_4

AB13

VCCO_4

AB12

VCCO_4

AB11

VCCO_4

AB10

VCCO_4

AA15

VCCO_4

AA14

VCCO_4

AA13

VCCO_4

AA12

VCCO_4

AA11

VCCO_5

AJ26

VCCO_5

AH18

VCCO_5

AB21

VCCO_5

AB20

VCCO_5

AB19

VCCO_5

AB18

VCCO_5

AA20

VCCO_5

AA19

VCCO_5

AA18

VCCO_5

AA17

VCCO_5

AA16

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

113

VCCO_6

AF29

VCCO_6

AA22

VCCO_6

Y22

VCCO_6

Y21

VCCO_6

W22

VCCO_6

W21

VCCO_6

V28

VCCO_6

V22

VCCO_6

V21

VCCO_6

U21

VCCO_6

T21

VCCO_7

R21

VCCO_7

P21

VCCO_7

N28

VCCO_7

N22

VCCO_7

N21

VCCO_7

M22

VCCO_7

M21

VCCO_7

L22

VCCO_7

L21

VCCO_7

K22

VCCO_7

E29

CCLK

AF6

PROG_B

B28

DONE

AG5

AF25

AG26

AH27

HSWAP_EN

C27

TCK

TDI

A29

TDO

TMS

PWRDWN_B

AH4

DXN

D26

DXP

E25

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

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Module 4 of 4

Product Specification

1-800-255-7778

114

VBATT

RSVD

VCCAUX

AK28

VCCAUX

AK16

VCCAUX

AK3

VCCAUX

R30

VCCAUX

A28

VCCAUX

A15

VCCAUX

VCCINT

AB22

VCCINT

AB9

VCCINT

AA21

VCCINT

AA10

VCCINT

Y20

VCCINT

Y19

VCCINT

Y18

VCCINT

Y17

VCCINT

Y16

VCCINT

Y15

VCCINT

Y14

VCCINT

Y13

VCCINT

Y12

VCCINT

Y11

VCCINT

W20

VCCINT

W11

VCCINT

V20

VCCINT

V11

VCCINT

U20

VCCINT

U11

VCCINT

T20

VCCINT

T11

VCCINT

R20

VCCINT

R11

VCCINT

P20

VCCINT

P11

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

115

VCCINT

N20

VCCINT

N11

VCCINT

M20

VCCINT

M11

VCCINT

L20

VCCINT

L19

VCCINT

L18

VCCINT

L17

VCCINT

L16

VCCINT

L15

VCCINT

L14

VCCINT

L13

VCCINT

L12

VCCINT

L11

VCCINT

K21

VCCINT

K10

VCCINT

J22

VCCINT

GND

AK23

GND

AK8

GND

AJ29

GND

AJ2

GND

AH28

GND

AH21

GND

AH10

GND

AH3

GND

AG27

GND

AG4

GND

AF26

GND

AF19

GND

AF12

GND

AF5

GND

AE25

GND

AE6

GND

AD17

GND

AD14

GND

AC30

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

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Module 4 of 4

Product Specification

1-800-255-7778

116

GND

AC1

GND

AA28

GND

AA3

GND

W26

GND

W19

GND

W18

GND

W17

GND

W16

GND

W15

GND

W14

GND

W13

GND

W12

GND

V19

GND

V18

GND

V17

GND

V16

GND

V15

GND

V14

GND

V13

GND

V12

GND

U24

GND

U19

GND

U18

GND

U17

GND

U16

GND

U15

GND

U14

GND

U13

GND

U12

GND

T19

GND

T18

GND

T17

GND

T16

GND

T15

GND

T14

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

117

GND

T13

GND

T12

GND

R19

GND

R18

GND

R17

GND

R16

GND

R15

GND

R14

GND

R13

GND

R12

GND

P24

GND

P19

GND

P18

GND

P17

GND

P16

GND

P15

GND

P14

GND

P13

GND

P12

GND

N19

GND

N18

GND

N17

GND

N16

GND

N15

GND

N14

GND

N13

GND

N12

GND

M26

GND

M19

GND

M18

GND

M17

GND

M16

GND

M15

GND

M14

GND

M13

GND

M12

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

118

GND

K28

GND

H30

GND

G17

GND

G14

GND

F25

GND

E26

GND

E19

GND

E12

GND

D27

GND

C28

GND

C21

GND

C10

GND

B29

GND

A23

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 11: FF896 BGA -- XC2V1000, XC2V1500, and XC2V2000

Bank

Pin Description

Pin Number

No Connect in the XC2V1000

No Connect in the XC2V1500

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

119

FF896 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 7: FF896 Flip-Chip Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

120

FF1152 Flip-Chip Fine-Pitch BGA Package

As shown in

Table 12

, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1152

flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V3000
device shown in the No Connect column. Following this table are the

FF1152 Flip-Chip Fine-Pitch BGA Package

Specifications (1.00mm pitch)

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

IO_L01N_0

D29

IO_L01P_0

C29

IO_L02N_0

H26

IO_L02P_0

G26

IO_L03N_0/VRP_0

E28

IO_L03P_0/VRN_0

E27

IO_L04N_0/VREF_0

F25

IO_L04P_0

F26

IO_L05N_0

H25

IO_L05P_0

H24

IO_L06N_0

E26

IO_L06P_0

F27

IO_L19N_0

B32

IO_L19P_0

C33

IO_L20N_0

J24

IO_L20P_0

J23

IO_L21N_0

C27

IO_L21P_0/VREF_0

C28

IO_L22N_0

B30

IO_L22P_0

B31

IO_L23N_0

K23

IO_L23P_0

K22

IO_L24N_0

C26

IO_L24P_0

D27

IO_L25N_0

A30

IO_L25P_0

A31

IO_L26N_0

G24

IO_L26P_0

G25

IO_L27N_0

E25

IO_L27P_0/VREF_0

E24

IO_L28N_0

D25

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

121

IO_L28P_0

D26

IO_L29N_0

H23

IO_L29P_0

H22

IO_L30N_0

F23

IO_L30P_0

F24

IO_L49N_0

B28

IO_L49P_0

B29

IO_L50N_0

J22

IO_L50P_0

J21

IO_L51N_0

A28

IO_L51P_0/VREF_0

A29

IO_L52N_0

A26

IO_L52P_0

B27

IO_L53N_0

C24

IO_L53P_0

D24

IO_L54N_0

D22

IO_L54P_0

D23

IO_L60N_0

B25

IO_L60P_0

B26

IO_L67N_0

B23

IO_L67P_0

B24

IO_L68N_0

G22

IO_L68P_0

G23

IO_L69N_0

F22

IO_L69P_0/VREF_0

F21

IO_L70N_0

A23

IO_L70P_0

A24

IO_L71N_0

K21

IO_L71P_0

K20

IO_L72N_0

C22

IO_L72P_0

C23

IO_L73N_0

E21

IO_L73P_0

E22

IO_L74N_0

H21

IO_L74P_0

H20

IO_L75N_0

G20

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

122

IO_L75P_0/VREF_0

F20

IO_L76N_0

B21

IO_L76P_0

B22

IO_L77N_0

J20

IO_L77P_0

K19

IO_L78N_0

D20

IO_L78P_0

D21

IO_L79N_0

A21

IO_L79P_0

A22

IO_L80N_0

L19

IO_L80P_0

L18

IO_L81N_0

B19

IO_L81P_0/VREF_0

A20

IO_L82N_0

A18

IO_L82P_0

B18

IO_L83N_0

H19

IO_L83P_0

H18

IO_L84N_0

C20

IO_L84P_0

C21

IO_L91N_0/VREF_0

D19

IO_L91P_0

D18

IO_L92N_0

G18

IO_L92P_0

G19

IO_L93N_0

F18

IO_L93P_0

F19

IO_L94N_0/VREF_0

C19

IO_L94P_0

C18

IO_L95N_0/GCLK7P

K18

IO_L95P_0/GCLK6S

J18

IO_L96N_0/GCLK5P

E19

IO_L96P_0/GCLK4S

E18

IO_L96N_1/GCLK3P

E17

IO_L96P_1/GCLK2S

E16

IO_L95N_1/GCLK1P

H17

IO_L95P_1/GCLK0S

H16

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

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Module 4 of 4

Product Specification

1-800-255-7778

123

IO_L94N_1

D17

IO_L94P_1/VREF_1

D16

IO_L93N_1

F16

IO_L93P_1

F17

IO_L92N_1

G16

IO_L92P_1

G17

IO_L91N_1

C16

IO_L91P_1/VREF_1

C15

IO_L84N_1

D14

IO_L84P_1

D15

IO_L83N_1

J17

IO_L83P_1

K17

IO_L82N_1

B17

IO_L82P_1

A17

IO_L81N_1/VREF_1

A15

IO_L81P_1

B16

IO_L80N_1

L17

IO_L80P_1

L16

IO_L79N_1

A13

IO_L79P_1

A14

IO_L78N_1

C13

IO_L78P_1

C14

IO_L77N_1

K16

IO_L77P_1

K15

IO_L76N_1

B13

IO_L76P_1

B14

IO_L75N_1/VREF_1

F15

IO_L75P_1

G15

IO_L74N_1

H15

IO_L74P_1

H14

IO_L73N_1

A11

IO_L73P_1

A12

IO_L72N_1

E13

IO_L72P_1

E14

IO_L71N_1

J15

IO_L71P_1

J14

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

124

IO_L70N_1

D12

IO_L70P_1

D13

IO_L69N_1/VREF_1

F14

IO_L69P_1

F13

IO_L68N_1

C11

IO_L68P_1

C12

IO_L67N_1

B11

IO_L67P_1

B12

IO_L60N_1

F11

IO_L60P_1

F12

IO_L54N_1

D10

IO_L54P_1

D11

IO_L53N_1

G12

IO_L53P_1

G13

IO_L52N_1

IO_L52P_1

B10

IO_L51N_1/VREF_1

IO_L51P_1

IO_L50N_1

K14

IO_L50P_1

K13

IO_L49N_1

IO_L49P_1

IO_L30N_1

IO_L30P_1

IO_L29N_1

H13

IO_L29P_1

H12

IO_L28N_1

IO_L28P_1

IO_L27N_1/VREF_1

E11

IO_L27P_1

E10

IO_L26N_1

J13

IO_L26P_1

K12

IO_L25N_1

IO_L25P_1

IO_L24N_1

IO_L24P_1

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

125

IO_L23N_1

G10

IO_L23P_1

G11

IO_L22N_1

IO_L22P_1

IO_L21N_1/VREF_1

F10

IO_L21P_1

IO_L20N_1

J12

IO_L20P_1

J11

IO_L19N_1

IO_L19P_1

IO_L06N_1

IO_L06P_1

IO_L05N_1

H11

IO_L05P_1

J10

IO_L04N_1

IO_L04P_1/VREF_1

IO_L03N_1/VRP_1

IO_L03P_1/VRN_1

IO_L02N_1

H10

IO_L02P_1

IO_L01N_1

IO_L01P_1

IO_L01N_2

IO_L01P_2

IO_L02N_2/VRP_2

K11

IO_L02P_2/VRN_2

K10

IO_L03N_2

IO_L03P_2/VREF_2

IO_L04N_2

IO_L04P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L19N_2

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

126

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2/VREF_2

IO_L22N_2

IO_L22P_2

IO_L23N_2

L10

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L25N_2

IO_L25P_2

IO_L26N_2

M10

IO_L26P_2

N10

IO_L27N_2

IO_L27P_2/VREF_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L30N_2

IO_L30P_2

IO_L43N_2

IO_L43P_2

IO_L44N_2

IO_L44P_2

IO_L45N_2

IO_L45P_2/VREF_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

IO_L48N_2

IO_L48P_2

IO_L49N_2

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

127

IO_L49P_2

IO_L50N_2

IO_L50P_2

IO_L51N_2

IO_L51P_2/VREF_2

IO_L52N_2

IO_L52P_2

IO_L53N_2

IO_L53P_2

IO_L54N_2

IO_L54P_2

IO_L67N_2

IO_L67P_2

IO_L68N_2

IO_L68P_2

IO_L69N_2

IO_L69P_2/VREF_2

IO_L70N_2

IO_L70P_2

IO_L71N_2

P10

IO_L71P_2

R10

IO_L72N_2

IO_L72P_2

IO_L73N_2

IO_L73P_2

IO_L74N_2

IO_L74P_2

IO_L75N_2

IO_L75P_2/VREF_2

IO_L76N_2

IO_L76P_2

IO_L77N_2

IO_L77P_2

IO_L78N_2

IO_L78P_2

IO_L79N_2

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

128

IO_L79P_2

IO_L80N_2

T11

IO_L80P_2

U11

IO_L81N_2

IO_L81P_2/VREF_2

IO_L82N_2

IO_L82P_2

IO_L83N_2

T10

IO_L83P_2

U10

IO_L84N_2

IO_L84P_2

IO_L91N_2

IO_L91P_2

IO_L92N_2

IO_L92P_2

IO_L93N_2

IO_L93P_2/VREF_2

IO_L94N_2

IO_L94P_2

IO_L95N_2

IO_L95P_2

IO_L96N_2

IO_L96P_2

IO_L96N_3

IO_L96P_3

IO_L95N_3

IO_L95P_3

IO_L94N_3

IO_L94P_3

IO_L93N_3/VREF_3

V10

IO_L93P_3

W10

IO_L92N_3

IO_L92P_3

IO_L91N_3

IO_L91P_3

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

129

IO_L84N_3

IO_L84P_3

IO_L83N_3

IO_L83P_3

IO_L82N_3

W11

IO_L82P_3

V11

IO_L81N_3/VREF_3

IO_L81P_3

IO_L80N_3

IO_L80P_3

IO_L79N_3

AA3

IO_L79P_3

AB3

IO_L78N_3

IO_L78P_3

AA6

IO_L77N_3

AA4

IO_L77P_3

AB4

IO_L76N_3

IO_L76P_3

AA8

IO_L75N_3/VREF_3

Y10

IO_L75P_3

AA10

IO_L74N_3

AA1

IO_L74P_3

AB1

IO_L73N_3

AA5

IO_L73P_3

AB5

IO_L72N_3

AA9

IO_L72P_3

IO_L71N_3

AA2

IO_L71P_3

AB2

IO_L70N_3

AB6

IO_L70P_3

AC6

IO_L69N_3/VREF_3

AD1

IO_L69P_3

AC1

IO_L68N_3

AC3

IO_L68P_3

AD3

IO_L67N_3

AC4

IO_L67P_3

AD4

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

130

IO_L54N_3

AB7

IO_L54P_3

AC7

IO_L53N_3

AC2

IO_L53P_3

AD2

IO_L52N_3

AC8

IO_L52P_3

AB8

IO_L51N_3/VREF_3

AB10

IO_L51P_3

AC10

IO_L50N_3

AD5

IO_L50P_3

AE5

IO_L49N_3

AE4

IO_L49P_3

AF4

IO_L48N_3

AB9

IO_L48P_3

AC9

IO_L47N_3

AE2

IO_L47P_3

AF1

IO_L46N_3

AD6

IO_L46P_3

AE6

IO_L45N_3/VREF_3

AD9

IO_L45P_3

AE9

IO_L44N_3

AF2

IO_L44P_3

AG2

IO_L43N_3

AF3

IO_L43P_3

AG3

IO_L30N_3

AD7

IO_L30P_3

AE7

IO_L29N_3

AF5

IO_L29P_3

AG5

IO_L28N_3

AE8

IO_L28P_3

AD8

IO_L27N_3/VREF_3

AF8

IO_L27P_3

AF9

IO_L26N_3

AH1

IO_L26P_3

AJ1

IO_L25N_3

AG4

IO_L25P_3

AH5

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

131

IO_L24N_3

AF6

IO_L24P_3

AG6

IO_L23N_3

AH3

IO_L23P_3

AJ3

IO_L22N_3

AF7

IO_L22P_3

AG7

IO_L21N_3/VREF_3

AL1

IO_L21P_3

AK1

IO_L20N_3

AH2

IO_L20P_3

AJ2

IO_L19N_3

AJ4

IO_L19P_3

AK4

IO_L06N_3

AE10

IO_L06P_3

AD10

IO_L05N_3

AK2

IO_L05P_3

AL2

IO_L04N_3

AH6

IO_L04P_3

AJ5

IO_L03N_3/VREF_3

AE11

IO_L03P_3

AF11

IO_L02N_3/VRP_3

AK3

IO_L02P_3/VRN_3

AL3

IO_L01N_3

AF10

IO_L01P_3

AG9

IO_L01N_4/BUSY/DOUT

(1)

AM4

IO_L01P_4/INIT_B

AL5

IO_L02N_4/D0/DIN

(1)

AG10

IO_L02P_4/D1

AH11

IO_L03N_4/D2/ALT_VRP_4

AK7

IO_L03P_4/D3/ALT_VRN_4

AK8

IO_L04N_4/VREF_4

AL6

IO_L04P_4

AM6

IO_L05N_4/VRP_4

AK9

IO_L05P_4/VRN_4

AJ8

IO_L06N_4

AM8

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

132

IO_L06P_4

AM7

IO_L19N_4

AN3

IO_L19P_4

AM2

IO_L20N_4

AJ10

IO_L20P_4

AJ9

IO_L21N_4

AH9

IO_L21P_4/VREF_4

AH10

IO_L22N_4

AN5

IO_L22P_4

AN4

IO_L23N_4

AE12

IO_L23P_4

AE13

IO_L24N_4

AM9

IO_L24P_4

AL8

IO_L25N_4

AP5

IO_L25P_4

AP4

IO_L26N_4

AG11

IO_L26P_4

AG12

IO_L27N_4

AN7

IO_L27P_4/VREF_4

AN6

IO_L28N_4

AL10

IO_L28P_4

AL9

IO_L29N_4

AF12

IO_L29P_4

AF13

IO_L30N_4

AK10

IO_L30P_4

AK11

IO_L49N_4

AP7

IO_L49P_4

AP6

IO_L50N_4

AH13

IO_L50P_4

AH12

IO_L51N_4

AJ11

IO_L51P_4/VREF_4

AJ12

IO_L52N_4

AP9

IO_L52P_4

AN8

IO_L53N_4

AG13

IO_L53P_4

AG14

IO_L54N_4

AM11

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

133

IO_L54P_4

AL11

IO_L60N_4

AN10

IO_L60P_4

AN9

IO_L67N_4

AN12

IO_L67P_4

AN11

IO_L68N_4

AE14

IO_L68P_4

AE15

IO_L69N_4

AJ13

IO_L69P_4/VREF_4

AJ14

IO_L70N_4

AL13

IO_L70P_4

AL12

IO_L71N_4

AF14

IO_L71P_4

AF15

IO_L72N_4

AM13

IO_L72P_4

AM12

IO_L73N_4

AP12

IO_L73P_4

AP11

IO_L74N_4

AG15

IO_L74P_4

AG16

IO_L75N_4

AN14

IO_L75P_4/VREF_4

AN13

IO_L76N_4

AP14

IO_L76P_4

AP13

IO_L77N_4

AD16

IO_L77P_4

AD17

IO_L78N_4

AK14

IO_L78P_4

AK13

IO_L79N_4

AN16

IO_L79P_4

AP15

IO_L80N_4

AE16

IO_L80P_4

AE17

IO_L81N_4

AH15

IO_L81P_4/VREF_4

AJ15

IO_L82N_4

AP17

IO_L82P_4

AN17

IO_L83N_4

AH17

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

134

IO_L83P_4

AH16

IO_L84N_4

AL15

IO_L84P_4

AL14

IO_L91N_4/VREF_4

AL16

IO_L91P_4

AL17

IO_L92N_4

AJ17

IO_L92P_4

AJ16

IO_L93N_4

AM15

IO_L93P_4

AM14

IO_L94N_4/VREF_4

AM16

IO_L94P_4

AM17

IO_L95N_4/GCLK3S

AF17

IO_L95P_4/GCLK2P

AG17

IO_L96N_4/GCLK1S

AK16

IO_L96P_4/GCLK0P

AK17

IO_L96N_5/GCLK7S

AK18

IO_L96P_5/GCLK6P

AK19

IO_L95N_5/GCLK5S

AG18

IO_L95P_5/GCLK4P

AF18

IO_L94N_5

AL18

IO_L94P_5/VREF_5

AL19

IO_L93N_5

AJ19

IO_L93P_5

AJ18

IO_L92N_5

AH19

IO_L92P_5

AH18

IO_L91N_5

AM19

IO_L91P_5/VREF_5

AM20

IO_L84N_5

AL21

IO_L84P_5

AL20

IO_L83N_5

AM22

IO_L83P_5

AM21

IO_L82N_5

AN18

IO_L82P_5

AP18

IO_L81N_5/VREF_5

AP20

IO_L81P_5

AN19

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

135

IO_L80N_5

AE18

IO_L80P_5

AE19

IO_L79N_5

AP22

IO_L79P_5

AP21

IO_L78N_5

AK22

IO_L78P_5

AK21

IO_L77N_5

AD18

IO_L77P_5

AD19

IO_L76N_5

AN22

IO_L76P_5

AN21

IO_L75N_5/VREF_5

AJ20

IO_L75P_5

AH20

IO_L74N_5

AG19

IO_L74P_5

AG20

IO_L73N_5

AP24

IO_L73P_5

AP23

IO_L72N_5

AL23

IO_L72P_5

AL22

IO_L71N_5

AF20

IO_L71P_5

AF21

IO_L70N_5

AM24

IO_L70P_5

AM23

IO_L69N_5/VREF_5

AJ21

IO_L69P_5

AJ22

IO_L68N_5

AJ24

IO_L68P_5

AJ23

IO_L67N_5

AN24

IO_L67P_5

AN23

IO_L60N_5

AN26

IO_L60P_5

AN25

IO_L54N_5

AL25

IO_L54P_5

AL24

IO_L53N_5

AE20

IO_L53P_5

AE21

IO_L52N_5

AN27

IO_L52P_5

AP26

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

136

IO_L51N_5/VREF_5

AP29

IO_L51P_5

AP28

IO_L50N_5

AG21

IO_L50P_5

AG22

IO_L49N_5

AN29

IO_L49P_5

AN28

IO_L30N_5

AK24

IO_L30P_5

AK25

IO_L29N_5

AH23

IO_L29P_5

AH22

IO_L28N_5

AP31

IO_L28P_5

AP30

IO_L27N_5/VREF_5

AH24

IO_L27P_5

AH25

IO_L26N_5

AF22

IO_L26P_5

AF23

IO_L25N_5

AM27

IO_L25P_5

AM26

IO_L24N_5

AL27

IO_L24P_5

AL26

IO_L23N_5

AH26

IO_L23P_5

AJ25

IO_L22N_5

AN31

IO_L22P_5

AN30

IO_L21N_5/VREF_5

AK26

IO_L21P_5

AK27

IO_L20N_5

AG23

IO_L20P_5

AF24

IO_L19N_5

AM33

IO_L19P_5

AN32

IO_L06N_5

AJ27

IO_L06P_5

AJ26

IO_L05N_5/VRP_5

AE22

IO_L05P_5/VRN_5

AE23

IO_L04N_5

AM28

IO_L04P_5/VREF_5

AM29

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

137

IO_L03N_5/D4/ALT_VRP_5

AK28

IO_L03P_5/D5/ALT_VRN_5

AL29

IO_L02N_5/D6

AG24

IO_L02P_5/D7

AG25

IO_L01N_5/RDWR_B

AL30

IO_L01P_5/CS_B

AM31

IO_L01P_6

AE24

IO_L01N_6

AD25

IO_L02P_6/VRN_6

AJ30

IO_L02N_6/VRP_6

AH30

IO_L03P_6

AL32

IO_L03N_6/VREF_6

AK32

IO_L04P_6

AF25

IO_L04N_6

AE25

IO_L05P_6

AJ31

IO_L05N_6

AK31

IO_L06P_6

AH29

IO_L06N_6

AG29

IO_L19P_6

AG26

IO_L19N_6

AF26

IO_L20P_6

AL33

IO_L20N_6

AK33

IO_L21P_6

AJ32

IO_L21N_6/VREF_6

AH32

IO_L22P_6

AG28

IO_L22N_6

AF28

IO_L23P_6

AG30

IO_L23N_6

AF30

IO_L24P_6

AF29

IO_L24N_6

AE29

IO_L25P_6

AF27

IO_L25N_6

AE27

IO_L26P_6

AL34

IO_L26N_6

AK34

IO_L27P_6

AE28

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

138

IO_L27N_6/VREF_6

AD28

IO_L28P_6

AE26

IO_L28N_6

AD26

IO_L29P_6

AF31

IO_L29N_6

AG31

IO_L30P_6

AF32

IO_L30N_6

AG32

IO_L43P_6

AC25

IO_L43N_6

AB25

IO_L44P_6

AJ33

IO_L44N_6

AH33

IO_L45P_6

AE31

IO_L45N_6/VREF_6

AD32

IO_L46P_6

AD27

IO_L46N_6

AC27

IO_L47P_6

AJ34

IO_L47N_6

AH34

IO_L48P_6

AE30

IO_L48N_6

AD30

IO_L49P_6

AC26

IO_L49N_6

AB26

IO_L50P_6

AD29

IO_L50N_6

AC29

IO_L51P_6

AF33

IO_L51N_6/VREF_6

AG33

IO_L52P_6

AC28

IO_L52N_6

AB28

IO_L53P_6

AF34

IO_L53N_6

AE33

IO_L54P_6

AB27

IO_L54N_6

AA27

IO_L67P_6

AA25

IO_L67N_6

Y25

IO_L68P_6

AD33

IO_L68N_6

AC33

IO_L69P_6

AC32

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

139

IO_L69N_6/VREF_6

AB32

IO_L70P_6

AA26

IO_L70N_6

Y26

IO_L71P_6

AD34

IO_L71N_6

AC34

IO_L72P_6

AC31

IO_L72N_6

AD31

IO_L73P_6

Y27

IO_L73N_6

W27

IO_L74P_6

AB29

IO_L74N_6

AA29

IO_L75P_6

AB31

IO_L75N_6/VREF_6

AA31

IO_L76P_6

Y28

IO_L76N_6

Y29

IO_L77P_6

AB33

IO_L77N_6

AA33

IO_L78P_6

AA30

IO_L78N_6

AB30

IO_L79P_6

W24

IO_L79N_6

V24

IO_L80P_6

AB34

IO_L80N_6

AA34

IO_L81P_6

W33

IO_L81N_6/VREF_6

Y34

IO_L82P_6

W25

IO_L82N_6

V25

IO_L83P_6

Y32

IO_L83N_6

AA32

IO_L84P_6

W29

IO_L84N_6

V29

IO_L91P_6

W28

IO_L91N_6

V28

IO_L92P_6

V33

IO_L92N_6

V34

IO_L93P_6

Y31

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

140

IO_L93N_6/VREF_6

W31

IO_L94P_6

V26

IO_L94N_6

V27

IO_L95P_6

W30

IO_L95N_6

V30

IO_L96P_6

V32

IO_L96N_6

W32

IO_L96P_7

U31

IO_L96N_7

V31

IO_L95P_7

T28

IO_L95N_7

U28

IO_L94P_7

U33

IO_L94N_7

U34

IO_L93P_7/VREF_7

U29

IO_L93N_7

T29

IO_L92P_7

U27

IO_L92N_7

U26

IO_L91P_7

T30

IO_L91N_7

U30

IO_L84P_7

R32

IO_L84N_7

T32

IO_L83P_7

U25

IO_L83N_7

T25

IO_L82P_7

R34

IO_L82N_7

T33

IO_L81P_7/VREF_7

N34

IO_L81N_7

P34

IO_L80P_7

U24

IO_L80N_7

T24

IO_L79P_7

R31

IO_L79N_7

T31

IO_L78P_7

N32

IO_L78N_7

P32

IO_L77P_7

T27

IO_L77N_7

R27

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

141

IO_L76P_7

N33

IO_L76N_7

P33

IO_L75P_7/VREF_7

R29

IO_L75N_7

R28

IO_L74P_7

R26

IO_L74N_7

P26

IO_L73P_7

N31

IO_L73N_7

P31

IO_L72P_7

N30

IO_L72N_7

P30

IO_L71P_7

R25

IO_L71N_7

P25

IO_L70P_7

L34

IO_L70N_7

M34

IO_L69P_7/VREF_7

P29

IO_L69N_7

N29

IO_L68P_7

P27

IO_L68N_7

N27

IO_L67P_7

L32

IO_L67N_7

M32

IO_L54P_7

L31

IO_L54N_7

M31

IO_L53P_7

K29

IO_L53N_7

L30

IO_L52P_7

L33

IO_L52N_7

M33

IO_L51P_7/VREF_7

M29

IO_L51N_7

L29

IO_L50P_7

M28

IO_L50N_7

N28

IO_L49P_7

K30

IO_L49N_7

K31

IO_L48P_7

H32

IO_L48N_7

J32

IO_L47P_7

N26

IO_L47N_7

M26

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

142

IO_L46P_7

J33

IO_L46N_7

K33

IO_L45P_7/VREF_7

H33

IO_L45N_7

J34

IO_L44P_7

M27

IO_L44N_7

L27

IO_L43P_7

H31

IO_L43N_7

J31

IO_L30P_7

F32

IO_L30N_7

G32

IO_L29P_7

N25

IO_L29N_7

M25

IO_L28P_7

F34

IO_L28N_7

G34

IO_L27P_7/VREF_7

J30

IO_L27N_7

H30

IO_L26P_7

K28

IO_L26N_7

L28

IO_L25P_7

H28

IO_L25N_7

J29

IO_L24P_7

G29

IO_L24N_7

H29

IO_L23P_7

L26

IO_L23N_7

K26

IO_L22P_7

F33

IO_L22N_7

G33

IO_L21P_7/VREF_7

J28

IO_L21N_7

J27

IO_L20P_7

K27

IO_L20N_7

J26

IO_L19P_7

E31

IO_L19N_7

F31

IO_L06P_7

D32

IO_L06N_7

E32

IO_L05P_7

L25

IO_L05N_7

K24

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

143

IO_L04P_7

D34

IO_L04N_7

E34

IO_L03P_7/VREF_7

G30

IO_L03N_7

F30

IO_L02P_7/VRN_7

K25

IO_L02N_7/VRP_7

J25

IO_L01P_7

D33

IO_L01N_7

E33

VCCO_0

M22

VCCO_0

M21

VCCO_0

M20

VCCO_0

M19

VCCO_0

M18

VCCO_0

L23

VCCO_0

L22

VCCO_0

L21

VCCO_0

L20

VCCO_0

E20

VCCO_0

D28

VCCO_0

A25

VCCO_0

A19

VCCO_1

M17

VCCO_1

M16

VCCO_1

M15

VCCO_1

M14

VCCO_1

M13

VCCO_1

L15

VCCO_1

L14

VCCO_1

L13

VCCO_1

L12

VCCO_1

E15

VCCO_1

A16

VCCO_1

A10

VCCO_2

U12

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

144

VCCO_2

T12

VCCO_2

R12

VCCO_2

R11

VCCO_2

P12

VCCO_2

P11

VCCO_2

N12

VCCO_2

N11

VCCO_2

M11

VCCO_2

VCCO_3

AH4

VCCO_3

AE1

VCCO_3

AC11

VCCO_3

AB12

VCCO_3

AB11

VCCO_3

AA12

VCCO_3

AA11

VCCO_3

Y12

VCCO_3

Y11

VCCO_3

W12

VCCO_3

V12

VCCO_4

AP16

VCCO_4

AP10

VCCO_4

AL7

VCCO_4

AK15

VCCO_4

AD15

VCCO_4

AD14

VCCO_4

AD13

VCCO_4

AD12

VCCO_4

AC17

VCCO_4

AC16

VCCO_4

AC15

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

145

VCCO_4

AC14

VCCO_4

AC13

VCCO_5

AP25

VCCO_5

AP19

VCCO_5

AL28

VCCO_5

AK20

VCCO_5

AD23

VCCO_5

AD22

VCCO_5

AD21

VCCO_5

AD20

VCCO_5

AC22

VCCO_5

AC21

VCCO_5

AC20

VCCO_5

AC19

VCCO_5

AC18

VCCO_6

AH31

VCCO_6

AE34

VCCO_6

AC24

VCCO_6

AB24

VCCO_6

AB23

VCCO_6

AA24

VCCO_6

AA23

VCCO_6

Y30

VCCO_6

Y24

VCCO_6

Y23

VCCO_6

W34

VCCO_6

W23

VCCO_6

V23

VCCO_7

U23

VCCO_7

T34

VCCO_7

T23

VCCO_7

R30

VCCO_7

R24

VCCO_7

R23

VCCO_7

P24

VCCO_7

P23

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

146

VCCO_7

N24

VCCO_7

N23

VCCO_7

M24

VCCO_7

K34

VCCO_7

G31

CCLK

AH8

PROG_B

D30

DONE

AJ7

AH27

AJ28

AK29

HSWAP_EN

E29

TCK

TDI

C31

TDO

TMS

PWRDWN_B

AK6

DXN

F28

DXP

G27

VBATT

RSVD

VCCAUX

AM30

VCCAUX

AM18

VCCAUX

AM5

VCCAUX

U32

VCCAUX

C30

VCCAUX

C17

VCCAUX

VCCINT

AD24

VCCINT

AD11

VCCINT

AC23

VCCINT

AC12

VCCINT

AB22

VCCINT

AB21

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

147

VCCINT

AB20

VCCINT

AB19

VCCINT

AB18

VCCINT

AB17

VCCINT

AB16

VCCINT

AB15

VCCINT

AB14

VCCINT

AB13

VCCINT

AA22

VCCINT

AA13

VCCINT

Y22

VCCINT

Y13

VCCINT

W22

VCCINT

W13

VCCINT

V22

VCCINT

V13

VCCINT

U22

VCCINT

U13

VCCINT

T22

VCCINT

T13

VCCINT

R22

VCCINT

R13

VCCINT

P22

VCCINT

P13

VCCINT

N22

VCCINT

N21

VCCINT

N20

VCCINT

N19

VCCINT

N18

VCCINT

N17

VCCINT

N16

VCCINT

N15

VCCINT

N14

VCCINT

N13

VCCINT

M23

VCCINT

M12

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

148

VCCINT

L24

VCCINT

L11

GND

AP33

GND

AP32

GND

AP27

GND

AP8

GND

AP3

GND

AP2

GND

AN34

GND

AN33

GND

AN20

GND

AN15

GND

AN2

GND

AN1

GND

AM34

GND

AM32

GND

AM25

GND

AM10

GND

AM3

GND

AM1

GND

AL31

GND

AL4

GND

AK30

GND

AK23

GND

AK12

GND

AK5

GND

AJ29

GND

AJ6

GND

AH28

GND

AH21

GND

AH14

GND

AH7

GND

AG34

GND

AG27

GND

AG8

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

149

GND

AG1

GND

AF19

GND

AF16

GND

AE32

GND

AE3

GND

AC30

GND

AC5

GND

AA28

GND

AA21

GND

AA20

GND

AA19

GND

AA18

GND

AA17

GND

AA16

GND

AA15

GND

AA14

GND

AA7

GND

Y33

GND

Y21

GND

Y20

GND

Y19

GND

Y18

GND

Y17

GND

Y16

GND

Y15

GND

Y14

GND

W26

GND

W21

GND

W20

GND

W19

GND

W18

GND

W17

GND

W16

GND

W15

GND

W14

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

150

GND

V21

GND

V20

GND

V19

GND

V18

GND

V17

GND

V16

GND

V15

GND

V14

GND

U21

GND

U20

GND

U19

GND

U18

GND

U17

GND

U16

GND

U15

GND

U14

GND

T26

GND

T21

GND

T20

GND

T19

GND

T18

GND

T17

GND

T16

GND

T15

GND

T14

GND

R33

GND

R21

GND

R20

GND

R19

GND

R18

GND

R17

GND

R16

GND

R15

GND

R14

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

151

GND

P28

GND

P21

GND

P20

GND

P19

GND

P18

GND

P17

GND

P16

GND

P15

GND

P14

GND

M30

GND

K32

GND

J19

GND

J16

GND

H34

GND

H27

GND

G28

GND

G21

GND

G14

GND

F29

GND

E30

GND

E23

GND

E12

GND

D31

GND

C34

GND

C32

GND

C25

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

152

GND

C10

GND

B34

GND

B33

GND

B20

GND

B15

GND

A33

GND

A32

GND

A27

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 12: FF1152 BGA -- XC2V3000, XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V3000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

153

FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 8: FF1152 Flip-Chip Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

154

FF1517 Flip-Chip Fine-Pitch BGA Package

As shown in

Table 13

, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1517 flip-chip

fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V4000 and
XC2V6000 devices shown in the No Connect columns. Following this table are the

FF1517 Flip-Chip Fine-Pitch BGA

Package Specifications (1.00mm pitch)

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

IO_L01N_0

B36

IO_L01P_0

C36

IO_L02N_0

J30

IO_L02P_0

J29

IO_L03N_0/VRP_0

D33

IO_L03P_0/VRN_0

D34

IO_L04N_0/VREF_0

C34

IO_L04P_0

C35

IO_L05N_0

H30

IO_L05P_0

G30

IO_L06N_0

D32

IO_L06P_0

E33

IO_L07N_0

A35

IO_L07P_0

A36

IO_L08N_0

K28

IO_L08P_0

J28

IO_L09N_0

E32

IO_L09P_0/VREF_0

F32

IO_L10N_0

B34

IO_L10P_0

B35

IO_L11N_0

H29

IO_L11P_0

H28

IO_L12N_0

F31

IO_L12P_0

G31

IO_L19N_0

C32

IO_L19P_0

C33

IO_L20N_0

M26

IO_L20P_0

M25

IO_L21N_0

E30

IO_L21P_0/VREF_0

E31

IO_L22N_0

A33

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

155

IO_L22P_0

A34

IO_L23N_0

K27

IO_L23P_0

K26

IO_L24N_0

F29

IO_L24P_0

F30

IO_L25N_0

B32

IO_L25P_0

B33

IO_L26N_0

L26

IO_L26P_0

L25

IO_L27N_0

G28

IO_L27P_0/VREF_0

G29

IO_L28N_0

C30

IO_L28P_0

C31

IO_L29N_0

J27

IO_L29P_0

J26

IO_L30N_0

D30

IO_L30P_0

D31

IO_L31N_0

A31

IO_L31P_0

A32

IO_L32N_0

H27

IO_L32P_0

H26

IO_L33N_0

F27

IO_L33P_0/VREF_0

F28

IO_L34N_0

B30

IO_L34P_0

B31

IO_L35N_0

M24

IO_L35P_0

M23

IO_L36N_0

D28

IO_L36P_0

D29

IO_L49N_0

C28

IO_L49P_0

C29

IO_L50N_0

K25

IO_L50P_0

L24

IO_L51N_0

E27

IO_L51P_0/VREF_0

E28

IO_L52N_0

A29

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

156

IO_L52P_0

A30

IO_L53N_0

G26

IO_L53P_0

G25

IO_L54N_0

D26

IO_L54P_0

D27

IO_L55N_0

B27

IO_L55P_0

B28

IO_L56N_0

H25

IO_L56P_0

H24

IO_L57N_0

F25

IO_L57P_0/VREF_0

F26

IO_L58N_0

A27

IO_L58P_0

A28

IO_L59N_0

K24

IO_L59P_0

K23

IO_L60N_0

E24

IO_L60P_0

E25

IO_L67N_0

C26

IO_L67P_0

C27

IO_L68N_0

J24

IO_L68P_0

J23

IO_L69N_0

D24

IO_L69P_0/VREF_0

D25

IO_L70N_0

A25

IO_L70P_0

A26

IO_L71N_0

M22

IO_L71P_0

M21

IO_L72N_0

G23

IO_L72P_0

G24

IO_L73N_0

B25

IO_L73P_0

C25

IO_L74N_0

L22

IO_L74P_0

L21

IO_L75N_0

F23

IO_L75P_0/VREF_0

F24

IO_L76N_0

C23

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

157

IO_L76P_0

C24

IO_L77N_0

K22

IO_L77P_0

K21

IO_L78N_0

E22

IO_L78P_0

E23

IO_L79N_0

B23

IO_L79P_0

B24

IO_L80N_0

J22

IO_L80P_0

J21

IO_L81N_0

G21

IO_L81P_0/VREF_0

G22

IO_L82N_0

A23

IO_L82P_0

A24

IO_L83N_0

H22

IO_L83P_0

H21

IO_L84N_0

F21

IO_L84P_0

F22

IO_L91N_0/VREF_0

B21

IO_L91P_0

B22

IO_L92N_0

L20

IO_L92P_0

M20

IO_L93N_0

E21

IO_L93P_0

D22

IO_L94N_0/VREF_0

A21

IO_L94P_0

A22

IO_L95N_0/GCLK7P

H20

IO_L95P_0/GCLK6S

J20

IO_L96N_0/GCLK5P

C21

IO_L96P_0/GCLK4S

D21

IO_L96N_1/GCLK3P

F19

IO_L96P_1/GCLK2S

F20

IO_L95N_1/GCLK1P

H19

IO_L95P_1/GCLK0S

H18

IO_L94N_1

C19

IO_L94P_1/VREF_1

C20

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

158

IO_L93N_1

E19

IO_L93P_1

E20

IO_L92N_1

J19

IO_L92P_1

J18

IO_L91N_1

A18

IO_L91P_1/VREF_1

A19

IO_L84N_1

D18

IO_L84P_1

D19

IO_L83N_1

K19

IO_L83P_1

K18

IO_L82N_1

B18

IO_L82P_1

B19

IO_L81N_1/VREF_1

G18

IO_L81P_1

G19

IO_L80N_1

E18

IO_L80P_1

E17

IO_L79N_1

A16

IO_L79P_1

A17

IO_L78N_1

F17

IO_L78P_1

F18

IO_L77N_1

L19

IO_L77P_1

L18

IO_L76N_1

B16

IO_L76P_1

B17

IO_L75N_1/VREF_1

G16

IO_L75P_1

G17

IO_L74N_1

M19

IO_L74P_1

M18

IO_L73N_1

C16

IO_L73P_1

C17

IO_L72N_1

D15

IO_L72P_1

D16

IO_L71N_1

J17

IO_L71P_1

J16

IO_L70N_1

A14

IO_L70P_1

A15

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

159

IO_L69N_1/VREF_1

E15

IO_L69P_1

E16

IO_L68N_1

K17

IO_L68P_1

K16

IO_L67N_1

C15

IO_L67P_1

B15

IO_L60N_1

F15

IO_L60P_1

F16

IO_L59N_1

H16

IO_L59P_1

H15

IO_L58N_1

C13

IO_L58P_1

C14

IO_L57N_1/VREF_1

D13

IO_L57P_1

D14

IO_L56N_1

M17

IO_L56P_1

M16

IO_L55N_1

A12

IO_L55P_1

A13

IO_L54N_1

B12

IO_L54P_1

B13

IO_L53N_1

G15

IO_L53P_1

G14

IO_L52N_1

C11

IO_L52P_1

C12

IO_L51N_1/VREF_1

F13

IO_L51P_1

F14

IO_L50N_1

L16

IO_L50P_1

L15

IO_L49N_1

A10

IO_L49P_1

A11

IO_L36N_1

E12

IO_L36P_1

E13

IO_L35N_1

K15

IO_L35P_1

J14

IO_L34N_1

IO_L34P_1

B10

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

160

IO_L33N_1/VREF_1

D11

IO_L33P_1

D12

IO_L32N_1

H14

IO_L32P_1

H13

IO_L31N_1

IO_L31P_1

IO_L30N_1

F11

IO_L30P_1

F12

IO_L29N_1

K14

IO_L29P_1

L14

IO_L28N_1

IO_L28P_1

C10

IO_L27N_1/VREF_1

G11

IO_L27P_1

G12

IO_L26N_1

M15

IO_L26P_1

M14

IO_L25N_1

IO_L25P_1

IO_L24N_1

IO_L24P_1

D10

IO_L23N_1

J13

IO_L23P_1

J12

IO_L22N_1

IO_L22P_1

IO_L21N_1/VREF_1

IO_L21P_1

E10

IO_L20N_1

IO_L20P_1

IO_L19N_1

IO_L19P_1

IO_L12N_1

IO_L12P_1

F10

IO_L11N_1

H12

IO_L11P_1

H11

IO_L10N_1

IO_L10P_1

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

161

IO_L09N_1/VREF_1

IO_L09P_1

G10

IO_L08N_1

K13

IO_L08P_1

K12

IO_L07N_1

IO_L07P_1

IO_L06N_1

IO_L06P_1

IO_L05N_1

J11

IO_L05P_1

K11

IO_L04N_1

IO_L04P_1/VREF_1

IO_L03N_1/VRP_1

IO_L03P_1/VRN_1

IO_L02N_1

H10

IO_L02P_1

J10

IO_L01N_1

IO_L01P_1

IO_L01N_2

IO_L01P_2

IO_L02N_2/VRP_2

L13

IO_L02P_2/VRN_2

M13

IO_L03N_2

IO_L03P_2/VREF_2

IO_L04N_2

IO_L04P_2

IO_L05N_2

L12

IO_L05P_2

M11

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

M12

IO_L08P_2

N12

IO_L09N_2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

162

IO_L09P_2/VREF_2

IO_L10N_2

IO_L10P_2

IO_L11N_2

IO_L11P_2

IO_L12N_2

IO_L12P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

L10

IO_L21N_2

IO_L21P_2/VREF_2

IO_L22N_2

IO_L22P_2

IO_L23N_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L25N_2

IO_L25P_2

IO_L26N_2

M10

IO_L26P_2

N10

IO_L27N_2

IO_L27P_2/VREF_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

N11

IO_L29P_2

P11

IO_L30N_2

IO_L30P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

163

IO_L33P_2/VREF_2

IO_L34N_2

IO_L34P_2

IO_L35N_2

P12

IO_L35P_2

R12

IO_L36N_2

IO_L36P_2

IO_L43N_2

IO_L43P_2

IO_L44N_2

IO_L44P_2

IO_L45N_2

IO_L45P_2/VREF_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

P10

IO_L47P_2

R10

IO_L48N_2

IO_L48P_2

IO_L49N_2

IO_L49P_2

IO_L50N_2

IO_L50P_2

IO_L51N_2

T11

IO_L51P_2/VREF_2

R11

IO_L52N_2

IO_L52P_2

IO_L53N_2

T12

IO_L53P_2

U12

IO_L54N_2

IO_L54P_2

IO_L55N_2

IO_L55P_2

IO_L56N_2

IO_L56P_2

IO_L57N_2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

164

IO_L57P_2/VREF_2

IO_L58N_2

IO_L58P_2

IO_L59N_2

T10

IO_L59P_2

U10

IO_L60N_2

IO_L60P_2

IO_L67N_2

IO_L67P_2

IO_L68N_2

IO_L68P_2

IO_L69N_2

IO_L69P_2/VREF_2

IO_L70N_2

IO_L70P_2

IO_L71N_2

V12

IO_L71P_2

W12

IO_L72N_2

IO_L72P_2

IO_L73N_2

IO_L73P_2

IO_L74N_2

V11

IO_L74P_2

W11

IO_L75N_2

IO_L75P_2/VREF_2

IO_L76N_2

IO_L76P_2

IO_L77N_2

V10

IO_L77P_2

W10

IO_L78N_2

IO_L78P_2

IO_L79N_2

IO_L79P_2

IO_L80N_2

IO_L80P_2

IO_L81N_2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

165

IO_L81P_2/VREF_2

IO_L82N_2

IO_L82P_2

IO_L83N_2

IO_L83P_2

IO_L84N_2

IO_L84P_2

IO_L91N_2

IO_L91P_2

IO_L92N_2

Y11

IO_L92P_2

Y12

IO_L93N_2

IO_L93P_2/VREF_2

IO_L94N_2

IO_L94P_2

IO_L95N_2

IO_L95P_2

IO_L96N_2

IO_L96P_2

IO_L96N_3

AB8

IO_L96P_3

AA8

IO_L95N_3

IO_L95P_3

AA3

IO_L94N_3

IO_L94P_3

AA6

IO_L93N_3/VREF_3

AB9

IO_L93P_3

AA9

IO_L92N_3

AA1

IO_L92P_3

AB1

IO_L91N_3

IO_L91P_3

AA5

IO_L84N_3

AB10

IO_L84P_3

AA10

IO_L83N_3

AA2

IO_L83P_3

AB2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

166

IO_L82N_3

AA4

IO_L82P_3

AB4

IO_L81N_3/VREF_3

AB11

IO_L81P_3

AA11

IO_L80N_3

AC1

IO_L80P_3

AD1

IO_L79N_3

AA7

IO_L79P_3

AB7

IO_L78N_3

AB12

IO_L78P_3

AA12

IO_L77N_3

AC2

IO_L77P_3

AC3

IO_L76N_3

AB5

IO_L76P_3

AC5

IO_L75N_3/VREF_3

AD9

IO_L75P_3

AC9

IO_L74N_3

AD2

IO_L74P_3

AE2

IO_L73N_3

AB6

IO_L73P_3

AC6

IO_L72N_3

AD10

IO_L72P_3

AC10

IO_L71N_3

AD3

IO_L71P_3

AE3

IO_L70N_3

AC7

IO_L70P_3

AD7

IO_L69N_3/VREF_3

AE8

IO_L69P_3

AD8

IO_L68N_3

AE1

IO_L68P_3

AF1

IO_L67N_3

AD4

IO_L67P_3

AE4

IO_L60N_3

AD12

IO_L60P_3

AC12

IO_L59N_3

AF3

IO_L59P_3

AG3

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

167

IO_L58N_3

AD5

IO_L58P_3

AE5

IO_L57N_3/VREF_3

AE11

IO_L57P_3

AD11

IO_L56N_3

AG1

IO_L56P_3

AH1

IO_L55N_3

AD6

IO_L55P_3

AE6

IO_L54N_3

AF10

IO_L54P_3

AE10

IO_L53N_3

AG2

IO_L53P_3

AH2

IO_L52N_3

AF4

IO_L52P_3

AG4

IO_L51N_3/VREF_3

AG8

IO_L51P_3

AF8

IO_L50N_3

AH3

IO_L50P_3

AJ3

IO_L49N_3

AE7

IO_L49P_3

AF7

IO_L48N_3

AG9

IO_L48P_3

AF9

IO_L47N_3

AF6

IO_L47P_3

AG6

IO_L46N_3

AG5

IO_L46P_3

AH5

IO_L45N_3/VREF_3

AF12

IO_L45P_3

AE12

IO_L44N_3

AJ1

IO_L44P_3

AK1

IO_L43N_3

AH4

IO_L43P_3

AJ4

IO_L36N_3

AG11

IO_L36P_3

AF11

IO_L35N_3

AK2

IO_L35P_3

AL2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

168

IO_L34N_3

AH6

IO_L34P_3

AJ6

IO_L33N_3/VREF_3

AJ8

IO_L33P_3

AH8

IO_L32N_3

AL1

IO_L32P_3

AM1

IO_L31N_3

AH7

IO_L31P_3

AJ7

IO_L30N_3

AH10

IO_L30P_3

AG10

IO_L29N_3

AK3

IO_L29P_3

AL3

IO_L28N_3

AK4

IO_L28P_3

AL4

IO_L27N_3/VREF_3

AJ9

IO_L27P_3

AH9

IO_L26N_3

AM2

IO_L26P_3

AN2

IO_L25N_3

AK5

IO_L25P_3

AL5

IO_L24N_3

AK9

IO_L24P_3

AK8

IO_L23N_3

AN1

IO_L23P_3

AP1

IO_L22N_3

AK6

IO_L22P_3

AL6

IO_L21N_3/VREF_3

AH12

IO_L21P_3

AG12

IO_L20N_3

AM3

IO_L20P_3

AN3

IO_L19N_3

AM4

IO_L19P_3

AN4

IO_L12N_3

AJ12

IO_L12P_3

AH11

IO_L11N_3

AP2

IO_L11P_3

AR2

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

169

IO_L10N_3

AK7

IO_L10P_3

AL7

IO_L09N_3/VREF_3

AK11

IO_L09P_3

AJ10

IO_L08N_3

AR1

IO_L08P_3

AT1

IO_L07N_3

AM5

IO_L07P_3

AN5

IO_L06N_3

AM7

IO_L06P_3

AL8

IO_L05N_3

AP3

IO_L05P_3

AP4

IO_L04N_3

AM6

IO_L04P_3

AN6

IO_L03N_3/VREF_3

AJ13

IO_L03P_3

AH13

IO_L02N_3/VRP_3

AR3

IO_L02P_3/VRN_3

AT2

IO_L01N_3

AP5

IO_L01P_3

AR4

IO_L01N_4/BUSY/DOUT

(1)

AV4

IO_L01P_4/INIT_B

AU4

IO_L02N_4/D0/DIN

(1)

AM9

IO_L02P_4/D1

AM10

IO_L03N_4/D2/ALT_VRP_4

AT6

IO_L03P_4/D3/ALT_VRN_4

AR6

IO_L04N_4/VREF_4

AU6

IO_L04P_4

AU5

IO_L05N_4/VRP_4

AL10

IO_L05P_4/VRN_4

AL11

IO_L06N_4

AR8

IO_L06P_4

AR7

IO_L07N_4

AW5

IO_L07P_4

AW4

IO_L08N_4

AK12

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

170

IO_L08P_4

AL12

IO_L09N_4

AP9

IO_L09P_4/VREF_4

AP8

IO_L10N_4

AV6

IO_L10P_4

AV5

IO_L11N_4

AM11

IO_L11P_4

AM12

IO_L12N_4

AN10

IO_L12P_4

AN9

IO_L19N_4

AU8

IO_L19P_4

AU7

IO_L20N_4

AH14

IO_L20P_4

AH15

IO_L21N_4

AT8

IO_L21P_4/VREF_4

AT7

IO_L22N_4

AW7

IO_L22P_4

AW6

IO_L23N_4

AK13

IO_L23P_4

AK14

IO_L24N_4

AR10

IO_L24P_4

AR9

IO_L25N_4

AV8

IO_L25P_4

AV7

IO_L26N_4

AJ14

IO_L26P_4

AJ15

IO_L27N_4

AP11

IO_L27P_4/VREF_4

AP10

IO_L28N_4

AU10

IO_L28P_4

AU9

IO_L29N_4

AL13

IO_L29P_4

AL14

IO_L30N_4

AN12

IO_L30P_4

AN11

IO_L31N_4

AW9

IO_L31P_4

AW8

IO_L32N_4

AM13

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

171

IO_L32P_4

AM14

IO_L33N_4

AT10

IO_L33P_4/VREF_4

AT9

IO_L34N_4

AV10

IO_L34P_4

AV9

IO_L35N_4

AH16

IO_L35P_4

AH17

IO_L36N_4

AP13

IO_L36P_4

AP12

IO_L49N_4

AU12

IO_L49P_4

AU11

IO_L50N_4

AK15

IO_L50P_4

AJ16

IO_L51N_4

AT12

IO_L51P_4/VREF_4

AT11

IO_L52N_4

AN15

IO_L52P_4

AN14

IO_L53N_4

AR12

IO_L53P_4

AR13

IO_L54N_4

AT14

IO_L54P_4

AT13

IO_L55N_4

AW11

IO_L55P_4

AW10

IO_L56N_4

AM15

IO_L56P_4

AM16

IO_L57N_4

AP15

IO_L57P_4/VREF_4

AP14

IO_L58N_4

AV13

IO_L58P_4

AV12

IO_L59N_4

AK16

IO_L59P_4

AK17

IO_L60N_4

AR16

IO_L60P_4

AR15

IO_L67N_4

AW13

IO_L67P_4

AW12

IO_L68N_4

AL16

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

172

IO_L68P_4

AL17

IO_L69N_4

AT16

IO_L69P_4/VREF_4

AT15

IO_L70N_4

AU14

IO_L70P_4

AU13

IO_L71N_4

AH18

IO_L71P_4

AH19

IO_L72N_4

AN17

IO_L72P_4

AN16

IO_L73N_4

AW15

IO_L73P_4

AW14

IO_L74N_4

AJ18

IO_L74P_4

AJ19

IO_L75N_4

AP17

IO_L75P_4/VREF_4

AP16

IO_L76N_4

AV15

IO_L76P_4

AU15

IO_L77N_4

AK18

IO_L77P_4

AK19

IO_L78N_4

AR18

IO_L78P_4

AR17

IO_L79N_4

AU17

IO_L79P_4

AU16

IO_L80N_4

AL18

IO_L80P_4

AL19

IO_L81N_4

AN19

IO_L81P_4/VREF_4

AN18

IO_L82N_4

AV17

IO_L82P_4

AV16

IO_L83N_4

AM18

IO_L83P_4

AM19

IO_L84N_4

AP19

IO_L84P_4

AP18

IO_L85N_4

AW17

IO_L85P_4

AW16

IO_L91N_4/VREF_4

AV19

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

173

IO_L91P_4

AV18

IO_L92N_4

AH20

IO_L92P_4

AJ20

IO_L93N_4

AR19

IO_L93P_4

AT18

IO_L94N_4/VREF_4

AW19

IO_L94P_4

AW18

IO_L95N_4/GCLK3S

AL20

IO_L95P_4/GCLK2P

AM20

IO_L96N_4/GCLK1S

AU19

IO_L96P_4/GCLK0P

AT19

IO_L96N_5/GCLK7S

AP21

IO_L96P_5/GCLK6P

AP20

IO_L95N_5/GCLK5S

AN21

IO_L95P_5/GCLK4P

AN22

IO_L94N_5

AU21

IO_L94P_5/VREF_5

AU20

IO_L93N_5

AR21

IO_L93P_5

AR20

IO_L92N_5

AM21

IO_L92P_5

AM22

IO_L91N_5

AW22

IO_L91P_5/VREF_5

AW21

IO_L85N_5

AV22

IO_L85P_5

AV21

IO_L84N_5

AT22

IO_L84P_5

AT21

IO_L83N_5

AL21

IO_L83P_5

AL22

IO_L82N_5

AW24

IO_L82P_5

AW23

IO_L81N_5/VREF_5

AR23

IO_L81P_5

AR22

IO_L80N_5

AK21

IO_L80P_5

AK22

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

174

IO_L79N_5

AV24

IO_L79P_5

AV23

IO_L78N_5

AP23

IO_L78P_5

AP22

IO_L77N_5

AJ21

IO_L77P_5

AJ22

IO_L76N_5

AU24

IO_L76P_5

AU23

IO_L75N_5/VREF_5

AT25

IO_L75P_5

AT24

IO_L74N_5

AH21

IO_L74P_5

AH22

IO_L73N_5

AW26

IO_L73P_5

AW25

IO_L72N_5

AR25

IO_L72P_5

AR24

IO_L71N_5

AN23

IO_L71P_5

AN24

IO_L70N_5

AU25

IO_L70P_5

AV25

IO_L69N_5/VREF_5

AL24

IO_L69P_5

AL23

IO_L68N_5

AK23

IO_L68P_5

AK24

IO_L67N_5

AU27

IO_L67P_5

AU26

IO_L60N_5

AP25

IO_L60P_5

AP24

IO_L59N_5

AM24

IO_L59P_5

AM25

IO_L58N_5

AW28

IO_L58P_5

AW27

IO_L57N_5/VREF_5

AT27

IO_L57P_5

AT26

IO_L56N_5

AH23

IO_L56P_5

AH24

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

175

IO_L55N_5

AV28

IO_L55P_5

AV27

IO_L54N_5

AP27

IO_L54P_5

AP26

IO_L53N_5

AN25

IO_L53P_5

AN26

IO_L52N_5

AU29

IO_L52P_5

AU28

IO_L51N_5/VREF_5

AR28

IO_L51P_5

AR27

IO_L50N_5

AJ24

IO_L50P_5

AJ25

IO_L49N_5

AW30

IO_L49P_5

AW29

IO_L36N_5

AT29

IO_L36P_5

AT28

IO_L35N_5

AK25

IO_L35P_5

AL26

IO_L34N_5

AV31

IO_L34P_5

AV30

IO_L33N_5/VREF_5

AP29

IO_L33P_5

AP28

IO_L32N_5

AK26

IO_L32P_5

AJ26

IO_L31N_5

AW32

IO_L31P_5

AW31

IO_L30N_5

AM27

IO_L30P_5

AM26

IO_L29N_5

AN28

IO_L29P_5

AN29

IO_L28N_5

AU31

IO_L28P_5

AU30

IO_L27N_5/VREF_5

AT31

IO_L27P_5

AT30

IO_L26N_5

AH25

IO_L26P_5

AH26

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

176

IO_L25N_5

AV33

IO_L25P_5

AV32

IO_L24N_5

AR31

IO_L24P_5

AR30

IO_L23N_5

AL27

IO_L23P_5

AL28

IO_L22N_5

AW34

IO_L22P_5

AW33

IO_L21N_5/VREF_5

AN30

IO_L21P_5

AP30

IO_L20N_5

AM28

IO_L20P_5

AM29

IO_L19N_5

AU33

IO_L19P_5

AU32

IO_L12N_5

AT33

IO_L12P_5

AT32

IO_L11N_5

AK27

IO_L11P_5

AK28

IO_L10N_5

AV35

IO_L10P_5

AV34

IO_L09N_5/VREF_5

AP32

IO_L09P_5

AP31

IO_L08N_5

AL29

IO_L08P_5

AK29

IO_L07N_5

AW36

IO_L07P_5

AW35

IO_L06N_5

AR33

IO_L06P_5

AR32

IO_L05N_5/VRP_5

AM30

IO_L05P_5/VRN_5

AL30

IO_L04N_5

AU35

IO_L04P_5/VREF_5

AU34

IO_L03N_5/D4/ALT_VRP_5

AR34

IO_L03P_5/D5/ALT_VRN_5

AT34

IO_L02N_5/D6

AN31

IO_L02P_5/D7

AM31

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

177

IO_L01N_5/RDWR_B

AU36

IO_L01P_5/CS_B

AV36

IO_L01P_6

AJ27

IO_L01N_6

AH27

IO_L02P_6/VRN_6

AT38

IO_L02N_6/VRP_6

AR37

IO_L03P_6

AP36

IO_L03N_6/VREF_6

AR36

IO_L04P_6

AJ28

IO_L04N_6

AH29

IO_L05P_6

AT39

IO_L05N_6

AR39

IO_L06P_6

AN34

IO_L06N_6

AP35

IO_L07P_6

AH28

IO_L07N_6

AG28

IO_L08P_6

AR38

IO_L08N_6

AP38

IO_L09P_6

AM34

IO_L09N_6/VREF_6

AM33

IO_L10P_6

AL32

IO_L10N_6

AK32

IO_L11P_6

AP37

IO_L11N_6

AN37

IO_L12P_6

AM35

IO_L12N_6

AN35

IO_L19P_6

AK31

IO_L19N_6

AJ30

IO_L20P_6

AP39

IO_L20N_6

AN39

IO_L21P_6

AK33

IO_L21N_6/VREF_6

AL33

IO_L22P_6

AJ31

IO_L22N_6

AH31

IO_L23P_6

AN38

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

178

IO_L23N_6

AM38

IO_L24P_6

AM36

IO_L24N_6

AN36

IO_L25P_6

AH30

IO_L25N_6

AG30

IO_L26P_6

AM37

IO_L26N_6

AL37

IO_L27P_6

AK34

IO_L27N_6/VREF_6

AL34

IO_L28P_6

AG29

IO_L28N_6

AF29

IO_L29P_6

AL35

IO_L29N_6

AK35

IO_L30P_6

AH33

IO_L30N_6

AJ33

IO_L31P_6

AJ32

IO_L31N_6

AH32

IO_L32P_6

AM39

IO_L32N_6

AL39

IO_L33P_6

AK36

IO_L33N_6/VREF_6

AL36

IO_L34P_6

AF28

IO_L34N_6

AE28

IO_L35P_6

AL38

IO_L35N_6

AK38

IO_L36P_6

AH34

IO_L36N_6

AJ34

IO_L43P_6

AG31

IO_L43N_6

AF31

IO_L44P_6

AK37

IO_L44N_6

AJ37

IO_L45P_6

AH36

IO_L45N_6/VREF_6

AJ36

IO_L46P_6

AF30

IO_L46N_6

AE30

IO_L47P_6

AK39

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

179

IO_L47N_6

AJ39

IO_L48P_6

AG35

IO_L48N_6

AH35

IO_L49P_6

AG32

IO_L49N_6

AF32

IO_L50P_6

AH37

IO_L50N_6

AG37

IO_L51P_6

AD29

IO_L51N_6/VREF_6

AE29

IO_L52P_6

AD28

IO_L52N_6

AC28

IO_L53P_6

AH38

IO_L53N_6

AG38

IO_L54P_6

AF34

IO_L54N_6

AG34

IO_L55P_6

AE32

IO_L55N_6

AD32

IO_L56P_6

AH39

IO_L56N_6

AG39

IO_L57P_6

AE33

IO_L57N_6/VREF_6

AF33

IO_L58P_6

AD30

IO_L58N_6

AC30

IO_L59P_6

AF37

IO_L59N_6

AE37

IO_L60P_6

AF36

IO_L60N_6

AG36

IO_L67P_6

AD31

IO_L67N_6

AC31

IO_L68P_6

AE34

IO_L68N_6

AD34

IO_L69P_6

AD35

IO_L69N_6/VREF_6

AE35

IO_L70P_6

AB28

IO_L70N_6

AA28

IO_L71P_6

AF39

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

180

IO_L71N_6

AE39

IO_L72P_6

AD36

IO_L72N_6

AE36

IO_L73P_6

AB29

IO_L73N_6

AA29

IO_L74P_6

AE38

IO_L74N_6

AD38

IO_L75P_6

AC33

IO_L75N_6/VREF_6

AD33

IO_L76P_6

AB30

IO_L76N_6

AA30

IO_L77P_6

AD37

IO_L77N_6

AC37

IO_L78P_6

AB34

IO_L78N_6

AC34

IO_L79P_6

AB31

IO_L79N_6

AA31

IO_L80P_6

AD39

IO_L80N_6

AC39

IO_L81P_6

AB35

IO_L81N_6/VREF_6

AC35

IO_L82P_6

AB32

IO_L82N_6

AA32

IO_L83P_6

AC38

IO_L83N_6

AB38

IO_L84P_6

AA33

IO_L84N_6

AB33

IO_L91P_6

Y28

IO_L91N_6

Y29

IO_L92P_6

AB39

IO_L92N_6

AA39

IO_L93P_6

AA36

IO_L93N_6/VREF_6

AB36

IO_L94P_6

Y31

IO_L94N_6

Y32

IO_L95P_6

AA37

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

181

IO_L95N_6

AA38

IO_L96P_6

AA35

IO_L96N_6

AA34

IO_L96P_7

W34

IO_L96N_7

Y34

IO_L95P_7

W32

IO_L95N_7

V32

IO_L94P_7

W37

IO_L94N_7

Y37

IO_L93P_7/VREF_7

W35

IO_L93N_7

Y35

IO_L92P_7

W31

IO_L92N_7

V31

IO_L91P_7

V39

IO_L91N_7

W39

IO_L84P_7

V36

IO_L84N_7

W36

IO_L83P_7

W30

IO_L83N_7

V30

IO_L82P_7

V38

IO_L82N_7

W38

IO_L81P_7/VREF_7

V33

IO_L81N_7

W33

IO_L80P_7

W29

IO_L80N_7

V29

IO_L79P_7

T39

IO_L79N_7

U39

IO_L78P_7

U35

IO_L78N_7

V35

IO_L77P_7

W28

IO_L77N_7

V28

IO_L76P_7

U37

IO_L76N_7

U38

IO_L75P_7/VREF_7

U34

IO_L75N_7

V34

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

182

IO_L74P_7

U31

IO_L74N_7

T31

IO_L73P_7

R38

IO_L73N_7

T38

IO_L72P_7

T33

IO_L72N_7

U33

IO_L71P_7

U30

IO_L71N_7

T30

IO_L70P_7

R37

IO_L70N_7

T37

IO_L69P_7/VREF_7

R36

IO_L69N_7

T36

IO_L68P_7

T32

IO_L68N_7

R32

IO_L67P_7

P39

IO_L67N_7

R39

IO_L60P_7

R35

IO_L60N_7

T35

IO_L59P_7

U28

IO_L59N_7

T28

IO_L58P_7

N37

IO_L58N_7

P37

IO_L57P_7/VREF_7

R34

IO_L57N_7

T34

IO_L56P_7

T29

IO_L56N_7

R29

IO_L55P_7

M39

IO_L55N_7

N39

IO_L54P_7

N36

IO_L54N_7

P36

IO_L53P_7

R30

IO_L53N_7

P30

IO_L52P_7

M38

IO_L52N_7

N38

IO_L51P_7/VREF_7

P33

IO_L51N_7

R33

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

183

IO_L50P_7

P32

IO_L50N_7

N32

IO_L49P_7

L37

IO_L49N_7

M37

IO_L48P_7

N34

IO_L48N_7

P34

IO_L47P_7

P31

IO_L47N_7

N31

IO_L46P_7

M35

IO_L46N_7

N35

IO_L45P_7/VREF_7

L36

IO_L45N_7

M36

IO_L44P_7

R28

IO_L44N_7

P28

IO_L43P_7

K39

IO_L43N_7

L39

IO_L36P_7

L34

IO_L36N_7

M34

IO_L35P_7

P29

IO_L35N_7

N29

IO_L34P_7

J38

IO_L34N_7

K38

IO_L33P_7/VREF_7

L33

IO_L33N_7

M33

IO_L32P_7

M32

IO_L32N_7

L32

IO_L31P_7

H39

IO_L31N_7

J39

IO_L30P_7

J36

IO_L30N_7

K36

IO_L29P_7

N30

IO_L29N_7

M30

IO_L28P_7

J37

IO_L28N_7

K37

IO_L27P_7/VREF_7

J35

IO_L27N_7

K35

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

184

IO_L26P_7

M31

IO_L26N_7

L31

IO_L25P_7

G38

IO_L25N_7

H38

IO_L24P_7

J34

IO_L24N_7

K34

IO_L23P_7

K32

IO_L23N_7

K31

IO_L22P_7

F39

IO_L22N_7

G39

IO_L21P_7/VREF_7

G36

IO_L21N_7

H36

IO_L20P_7

N28

IO_L20N_7

M28

IO_L19P_7

G37

IO_L19N_7

H37

IO_L12P_7

J33

IO_L12N_7

K33

IO_L11P_7

M29

IO_L11N_7

L28

IO_L10P_7

E38

IO_L10N_7

F38

IO_L09P_7/VREF_7

G35

IO_L09N_7

H35

IO_L08P_7

L30

IO_L08N_7

K29

IO_L07P_7

D39

IO_L07N_7

E39

IO_L06P_7

G34

IO_L06N_7

H34

IO_L05P_7

J32

IO_L05N_7

H33

IO_L04P_7

F36

IO_L04N_7

F37

IO_L03P_7/VREF_7

E36

IO_L03N_7

F35

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

185

IO_L02P_7/VRN_7

M27

IO_L02N_7/VRP_7

L27

IO_L01P_7

D38

IO_L01N_7

E37

VCCO_0

P25

VCCO_0

P24

VCCO_0

P23

VCCO_0

P22

VCCO_0

P21

VCCO_0

N26

VCCO_0

N25

VCCO_0

N24

VCCO_0

N23

VCCO_0

N22

VCCO_0

N21

VCCO_0

L23

VCCO_0

J25

VCCO_0

G27

VCCO_0

E29

VCCO_0

C22

VCCO_0

B26

VCCO_1

P19

VCCO_1

P18

VCCO_1

P17

VCCO_1

P16

VCCO_1

P15

VCCO_1

N19

VCCO_1

N18

VCCO_1

N17

VCCO_1

N16

VCCO_1

N15

VCCO_1

N14

VCCO_1

L17

VCCO_1

J15

VCCO_1

G13

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

186

VCCO_1

E11

VCCO_1

C18

VCCO_1

B14

VCCO_2

W14

VCCO_2

W13

VCCO_2

V14

VCCO_2

V13

VCCO_2

U14

VCCO_2

U13

VCCO_2

U11

VCCO_2

T14

VCCO_2

T13

VCCO_2

R14

VCCO_2

R13

VCCO_2

P13

VCCO_2

VCCO_3

AJ5

VCCO_3

AG7

VCCO_3

AF13

VCCO_3

AF2

VCCO_3

AE14

VCCO_3

AE13

VCCO_3

AE9

VCCO_3

AD14

VCCO_3

AD13

VCCO_3

AC14

VCCO_3

AC13

VCCO_3

AC11

VCCO_3

AB14

VCCO_3

AB13

VCCO_3

AB3

VCCO_3

AA14

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

187

VCCO_3

AA13

VCCO_4

AV14

VCCO_4

AU18

VCCO_4

AR11

VCCO_4

AN13

VCCO_4

AL15

VCCO_4

AJ17

VCCO_4

AG19

VCCO_4

AG18

VCCO_4

AG17

VCCO_4

AG16

VCCO_4

AG15

VCCO_4

AG14

VCCO_4

AF19

VCCO_4

AF18

VCCO_4

AF17

VCCO_4

AF16

VCCO_4

AF15

VCCO_5

AV26

VCCO_5

AU22

VCCO_5

AR29

VCCO_5

AN27

VCCO_5

AL25

VCCO_5

AJ23

VCCO_5

AG26

VCCO_5

AG25

VCCO_5

AG24

VCCO_5

AG23

VCCO_5

AG22

VCCO_5

AG21

VCCO_5

AF25

VCCO_5

AF24

VCCO_5

AF23

VCCO_5

AF22

VCCO_5

AF21

VCCO_6

AJ35

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

188

VCCO_6

AG33

VCCO_6

AF38

VCCO_6

AF27

VCCO_6

AE31

VCCO_6

AE27

VCCO_6

AE26

VCCO_6

AD27

VCCO_6

AD26

VCCO_6

AC29

VCCO_6

AC27

VCCO_6

AC26

VCCO_6

AB37

VCCO_6

AB27

VCCO_6

AB26

VCCO_6

AA27

VCCO_6

AA26

VCCO_7

W27

VCCO_7

W26

VCCO_7

V37

VCCO_7

V27

VCCO_7

V26

VCCO_7

U29

VCCO_7

U27

VCCO_7

U26

VCCO_7

T27

VCCO_7

T26

VCCO_7

R31

VCCO_7

R27

VCCO_7

R26

VCCO_7

P38

VCCO_7

P27

VCCO_7

N33

VCCO_7

L35

CCLK

AT5

PROG_B

H31

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

189

DONE

AP7

AN32

AP33

AT35

HSWAP_EN

E34

TCK

TDI

D35

TDO

TMS

PWRDWN_B

AN8

DXN

G32

DXP

F33

VBATT

RSVD

VCCAUX

AV20

VCCAUX

AT37

VCCAUX

AT3

VCCAUX

Y38

VCCAUX

D37

VCCAUX

B20

VCCINT

AG27

VCCINT

AG20

VCCINT

AG13

VCCINT

AF26

VCCINT

AF20

VCCINT

AF14

VCCINT

AE25

VCCINT

AE24

VCCINT

AE23

VCCINT

AE22

VCCINT

AE21

VCCINT

AE20

VCCINT

AE19

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

190

VCCINT

AE18

VCCINT

AE17

VCCINT

AE16

VCCINT

AE15

VCCINT

AD25

VCCINT

AD24

VCCINT

AD16

VCCINT

AD15

VCCINT

AC25

VCCINT

AC15

VCCINT

AB25

VCCINT

AB15

VCCINT

AA25

VCCINT

AA15

VCCINT

Y27

VCCINT

Y26

VCCINT

Y25

VCCINT

Y15

VCCINT

Y14

VCCINT

Y13

VCCINT

W25

VCCINT

W15

VCCINT

V25

VCCINT

V15

VCCINT

U25

VCCINT

U15

VCCINT

T25

VCCINT

T24

VCCINT

T16

VCCINT

T15

VCCINT

R25

VCCINT

R24

VCCINT

R23

VCCINT

R22

VCCINT

R21

VCCINT

R20

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

191

VCCINT

R19

VCCINT

R18

VCCINT

R17

VCCINT

R16

VCCINT

R15

VCCINT

P26

VCCINT

P20

VCCINT

P14

VCCINT

N27

VCCINT

N20

VCCINT

N13

GND

AW38

GND

AW37

GND

AW20

GND

AW3

GND

AW2

GND

AV39

GND

AV38

GND

AV37

GND

AV29

GND

AV11

GND

AV3

GND

AV2

GND

AV1

GND

AU39

GND

AU38

GND

AU37

GND

AU3

GND

AU2

GND

AU1

GND

AT36

GND

AT23

GND

AT20

GND

AT17

GND

AT4

GND

AR35

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

192

GND

AR26

GND

AR14

GND

AR5

GND

AP34

GND

AP6

GND

AN33

GND

AN20

GND

AN7

GND

AM32

GND

AM23

GND

AM17

GND

AM8

GND

AL31

GND

AL9

GND

AK30

GND

AK20

GND

AK10

GND

AJ38

GND

AJ29

GND

AJ11

GND

AJ2

GND

AF35

GND

AF5

GND

AD23

GND

AD22

GND

AD21

GND

AD20

GND

AD19

GND

AD18

GND

AD17

GND

AC36

GND

AC32

GND

AC24

GND

AC23

GND

AC22

GND

AC21

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

193

GND

AC20

GND

AC19

GND

AC18

GND

AC17

GND

AC16

GND

AC8

GND

AC4

GND

AB24

GND

AB23

GND

AB22

GND

AB21

GND

AB20

GND

AB19

GND

AB18

GND

AB17

GND

AB16

GND

AA24

GND

AA23

GND

AA22

GND

AA21

GND

AA20

GND

AA19

GND

AA18

GND

AA17

GND

AA16

GND

Y39

GND

Y36

GND

Y33

GND

Y30

GND

Y24

GND

Y23

GND

Y22

GND

Y21

GND

Y20

GND

Y19

GND

Y18

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

194

GND

Y17

GND

Y16

GND

Y10

GND

W24

GND

W23

GND

W22

GND

W21

GND

W20

GND

W19

GND

W18

GND

W17

GND

W16

GND

V24

GND

V23

GND

V22

GND

V21

GND

V20

GND

V19

GND

V18

GND

V17

GND

V16

GND

U36

GND

U32

GND

U24

GND

U23

GND

U22

GND

U21

GND

U20

GND

U19

GND

U18

GND

U17

GND

U16

GND

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

195

GND

T23

GND

T22

GND

T21

GND

T20

GND

T19

GND

T18

GND

T17

GND

P35

GND

L38

GND

L29

GND

L11

GND

K30

GND

K20

GND

K10

GND

J31

GND

H32

GND

H23

GND

H17

GND

G33

GND

G20

GND

F34

GND

E35

GND

E26

GND

E14

GND

D36

GND

D23

GND

D20

GND

D17

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

196

GND

C39

GND

C38

GND

C37

GND

B39

GND

B38

GND

B37

GND

B29

GND

B11

GND

A38

GND

A37

GND

A20

GND

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 13: FF1517 BGA -- XC2V4000, XC2V6000, and XC2V8000

Bank

Pin Description

Pin Number

No Connect in the XC2V4000

No Connect in the XC2V6000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

197

FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch)

Figure 9: FF1517 Flip-Chip Fine-Pitch BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

198

BF957 Flip-Chip BGA Package

As shown in

Table 14

, XC2V2000, XC2V3000, XC2V4000, and XC2V6000 Virtex-II devices are available in the BF957

package. Pins in each of these devices are the same, except for the pin differences in the XC2V2000 device shown in the
No Connect column. Following this table are the

BF957 Flip-Chip BGA Package Specifications (1.27mm pitch)

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

IO_L01N_0

H23

IO_L01P_0

H22

IO_L02N_0

G24

IO_L02P_0

E25

IO_L03N_0/VRP_0

B29

IO_L03P_0/VRN_0

C27

IO_L04N_0/VREF_0

F24

IO_L04P_0

F23

IO_L05N_0

D26

IO_L05P_0

D25

IO_L06N_0

A28

IO_L06P_0

A27

IO_L19N_0

J22

IO_L19P_0

J21

IO_L20N_0

G23

IO_L20P_0

G22

IO_L21N_0

B27

IO_L21P_0/VREF_0

B26

IO_L22N_0

K20

IO_L22P_0

K19

IO_L23N_0

C26

IO_L23P_0

C24

IO_L24N_0

D24

IO_L24P_0

D23

IO_L25N_0

E24

IO_L25P_0

E23

IO_L26N_0

G21

IO_L26P_0

G20

IO_L27N_0

A26

IO_L27P_0/VREF_0

A25

IO_L29N_0

H21

IO_L29P_0

H20

IO_L30N_0

B25

IO_L30P_0

B23

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

199

IO_L49N_0

C23

IO_L49P_0

C22

IO_L50N_0

E22

IO_L50P_0

E21

IO_L51N_0

F21

IO_L51P_0/VREF_0

F20

IO_L52N_0

A24

IO_L52P_0

A23

IO_L53N_0

E20

IO_L53P_0

E19

IO_L54N_0

B22

IO_L54P_0

B21

IO_L67N_0

D21

IO_L67P_0

D20

IO_L68N_0

J20

IO_L68P_0

J19

IO_L69N_0

F19

IO_L69P_0/VREF_0

F18

IO_L70N_0

A22

IO_L70P_0

A21

IO_L71N_0

H19

IO_L71P_0

H17

IO_L72N_0

C21

IO_L72P_0

C20

IO_L73N_0

B20

IO_L73P_0

B19

IO_L74N_0

G18

IO_L74P_0

G17

IO_L75N_0

E18

IO_L75P_0/VREF_0

D17

IO_L76N_0

A20

IO_L76P_0

A19

IO_L77N_0

D19

IO_L77P_0

D18

IO_L78N_0

C19

IO_L78P_0

C17

IO_L91N_0/VREF_0

K18

IO_L91P_0

J18

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

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www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

200

IO_L92N_0

F17

IO_L92P_0

F16

IO_L93N_0

B18

IO_L93P_0

B17

IO_L94N_0/VREF_0

J17

IO_L94P_0

J16

IO_L95N_0/GCLK7P

E17

IO_L95P_0/GCLK6S

E16

IO_L96N_0/GCLK5P

A18

IO_L96P_0/GCLK4S

A17

IO_L96N_1/GCLK3P

C16

IO_L96P_1/GCLK2S

C15

IO_L95N_1/GCLK1P

H16

IO_L95P_1/GCLK0S

H15

IO_L94N_1

A15

IO_L94P_1/VREF_1

A14

IO_L93N_1

F15

IO_L93P_1

F14

IO_L92N_1

G15

IO_L92P_1

G14

IO_L91N_1

B15

IO_L91P_1/VREF_1

B14

IO_L78N_1

D15

IO_L78P_1

E15

IO_L77N_1

J15

IO_L77P_1

K14

IO_L76N_1

D14

IO_L76P_1

D13

IO_L75N_1/VREF_1

E14

IO_L75P_1

E13

IO_L74N_1

A13

IO_L74P_1

A12

IO_L73N_1

F13

IO_L73P_1

F12

IO_L72N_1

J14

IO_L72P_1

J13

IO_L71N_1

B13

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

201

IO_L71P_1

B12

IO_L70N_1

C13

IO_L70P_1

C12

IO_L69N_1/VREF_1

H13

IO_L69P_1

H12

IO_L68N_1

D12

IO_L68P_1

D11

IO_L67N_1

B11

IO_L67P_1

B10

IO_L54N_1

E12

IO_L54P_1

E11

IO_L53N_1

A11

IO_L53P_1

A10

IO_L52N_1

G12

IO_L52P_1

G11

IO_L51N_1/VREF_1

K13

IO_L51P_1

K12

IO_L50N_1

C11

IO_L50P_1

C10

IO_L49N_1

IO_L49P_1

IO_L30N_1

F11

IO_L30P_1

IO_L29N_1

IO_L29P_1

IO_L27N_1/VREF_1

IO_L27P_1

IO_L26N_1

J12

IO_L26P_1

J11

IO_L25N_1

IO_L25P_1

IO_L24N_1

E10

IO_L24P_1

IO_L23N_1

H11

IO_L23P_1

H10

IO_L22N_1

IO_L22P_1

IO_L21N_1/VREF_1

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

202

IO_L21P_1

IO_L20N_1

G10

IO_L20P_1

IO_L19N_1

IO_L19P_1

IO_L06N_1

IO_L06P_1

IO_L05N_1

IO_L05P_1

IO_L04N_1

IO_L04P_1/VREF_1

IO_L03N_1/VRP_1

IO_L03P_1/VRN_1

IO_L02N_1

IO_L02P_1

IO_L01N_1

IO_L01P_1

IO_L01N_2

IO_L01P_2

IO_L02N_2/VRP_2

IO_L02P_2/VRN_2

IO_L03N_2

IO_L03P_2/VREF_2

IO_L04N_2

K10

IO_L04P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L19N_2

L10

IO_L19P_2

M10

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2/VREF_2

IO_L22N_2

IO_L22P_2

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

203

IO_L23N_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L25N_2

IO_L25P_2

IO_L27N_2

IO_L27P_2/VREF_2

IO_L43N_2

IO_L43P_2

IO_L44N_2

IO_L44P_2

IO_L45N_2

IO_L45P_2/VREF_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

IO_L48N_2

IO_L48P_2

IO_L49N_2

IO_L49P_2

IO_L50N_2

N10

IO_L50P_2

P10

IO_L51N_2

IO_L51P_2/VREF_2

IO_L52N_2

IO_L52P_2

IO_L53N_2

IO_L53P_2

IO_L54N_2

IO_L54P_2

IO_L67N_2

IO_L67P_2

IO_L68N_2

IO_L68P_2

IO_L69N_2

IO_L69P_2/VREF_2

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

204

IO_L70N_2

IO_L70P_2

IO_L71N_2

IO_L71P_2

IO_L72N_2

IO_L72P_2

IO_L73N_2

IO_L73P_2

IO_L74N_2

IO_L74P_2

IO_L75N_2

IO_L75P_2/VREF_2

IO_L76N_2

IO_L76P_2

IO_L77N_2

IO_L77P_2

IO_L78N_2

IO_L78P_2

IO_L91N_2

IO_L91P_2

IO_L92N_2

IO_L92P_2

IO_L93N_2

IO_L93P_2/VREF_2

IO_L94N_2

IO_L94P_2

IO_L95N_2

IO_L95P_2

IO_L96N_2

IO_L96P_2

IO_L96N_3

IO_L96P_3

IO_L95N_3

IO_L95P_3

IO_L94N_3

IO_L94P_3

IO_L93N_3/VREF_3

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

205

IO_L93P_3

IO_L92N_3

IO_L92P_3

IO_L91N_3

IO_L91P_3

IO_L78N_3

IO_L78P_3

IO_L77N_3

IO_L77P_3

IO_L76N_3

IO_L76P_3

IO_L75N_3/VREF_3

IO_L75P_3

IO_L74N_3

IO_L74P_3

IO_L73N_3

IO_L73P_3

IO_L72N_3

IO_L72P_3

AA5

IO_L71N_3

IO_L71P_3

IO_L70N_3

IO_L70P_3

IO_L69N_3/VREF_3

IO_L69P_3

IO_L68N_3

AA1

IO_L68P_3

AB1

IO_L67N_3

IO_L67P_3

AA7

IO_L54N_3

AA6

IO_L54P_3

AC6

IO_L53N_3

AA2

IO_L53P_3

AB2

IO_L52N_3

AA4

IO_L52P_3

AC4

IO_L51N_3/VREF_3

V10

IO_L51P_3

W10

IO_L50N_3

AA3

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

206

IO_L50P_3

AB3

IO_L49N_3

AB5

IO_L49P_3

AC5

IO_L48N_3

IO_L48P_3

IO_L47N_3

AC1

IO_L47P_3

AD1

IO_L46N_3

AC3

IO_L46P_3

AD3

IO_L45N_3/VREF_3

IO_L45P_3

AA8

IO_L44N_3

AC2

IO_L44P_3

AE2

IO_L43N_3

AB7

IO_L43P_3

AC7

IO_L27N_3/VREF_3

Y10

IO_L27P_3

AA10

IO_L25N_3

AE1

IO_L25P_3

AF1

IO_L24N_3

AF2

IO_L24P_3

AG2

IO_L23N_3

AA9

IO_L23P_3

AB9

IO_L22N_3

AD4

IO_L22P_3

AE4

IO_L21N_3/VREF_3

AD5

IO_L21P_3

AE5

IO_L20N_3

AB8

IO_L20P_3

AC8

IO_L19N_3

AG1

IO_L19P_3

AH1

IO_L06N_3

AF4

IO_L06P_3

AG4

IO_L05N_3

AB10

IO_L05P_3

AB11

IO_L04N_3

AF3

IO_L04P_3

AG3

IO_L03N_3/VREF_3

AD6

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

207

IO_L03P_3

AD7

IO_L02N_3/VRP_3

AE6

IO_L02P_3/VRN_3

AF5

IO_L01N_3

AH2

IO_L01P_3

AH3

IO_L01N_4/BUSY/DOUT

(1)

AD9

IO_L01P_4/INIT_B

AD10

IO_L02N_4/D0/DIN

(1)

AF7

IO_L02P_4/D1

AG7

IO_L03N_4/D2/ALT_VRP_4

AK3

IO_L03P_4/D3/ALT_VRN_4

AJ5

IO_L04N_4/VREF_4

AE8

IO_L04P_4

AF8

IO_L05N_4/VRP_4

AK4

IO_L05P_4/VRN_4

AK5

IO_L06N_4

AH6

IO_L06P_4

AH7

IO_L19N_4

AC10

IO_L19P_4

AC11

IO_L20N_4

AE9

IO_L20P_4

AE10

IO_L21N_4

AL4

IO_L21P_4/VREF_4

AL5

IO_L22N_4

AB12

IO_L22P_4

AB13

IO_L23N_4

AJ6

IO_L23P_4

AJ8

IO_L24N_4

AK6

IO_L24P_4

AK7

IO_L25N_4

AG8

IO_L25P_4

AG9

IO_L26N_4

AF9

IO_L26P_4

AF11

IO_L27N_4

AH8

IO_L27P_4/VREF_4

AH9

IO_L28N_4

AD11

IO_L28P_4

AD12

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

208

IO_L29N_4

AL6

IO_L29P_4

AL7

IO_L30N_4

AJ9

IO_L30P_4

AJ10

IO_L49N_4

AE11

IO_L49P_4

AE12

IO_L50N_4

AG10

IO_L50P_4

AG11

IO_L51N_4

AL8

IO_L51P_4/VREF_4

AL9

IO_L52N_4

AF12

IO_L52P_4

AF13

IO_L53N_4

AK9

IO_L53P_4

AK10

IO_L54N_4

AH11

IO_L54P_4

AH12

IO_L67N_4

AC12

IO_L67P_4

AC13

IO_L68N_4

AG12

IO_L68P_4

AG13

IO_L69N_4

AL10

IO_L69P_4/VREF_4

AL11

IO_L70N_4

AD13

IO_L70P_4

AD15

IO_L71N_4

AJ11

IO_L71P_4

AJ12

IO_L72N_4

AK11

IO_L72P_4

AK12

IO_L73N_4

AE14

IO_L73P_4

AE15

IO_L74N_4

AF14

IO_L74P_4

AF15

IO_L75N_4

AL12

IO_L75P_4/VREF_4

AL13

IO_L76N_4

AB14

IO_L76P_4

AC14

IO_L77N_4

AH13

IO_L77P_4

AH14

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

209

IO_L78N_4

AJ13

IO_L78P_4

AK13

IO_L91N_4/VREF_4

AC15

IO_L91P_4

AC16

IO_L92N_4

AG14

IO_L92P_4

AG15

IO_L93N_4

AK14

IO_L93P_4

AK15

IO_L94N_4/VREF_4

AF16

IO_L94P_4

AG16

IO_L95N_4/GCLK3S

AL14

IO_L95P_4/GCLK2P

AL15

IO_L96N_4/GCLK1S

AH15

IO_L96P_4/GCLK0P

AJ15

IO_L96N_5/GCLK7S

AJ16

IO_L96P_5/GCLK6P

AH17

IO_L95N_5/GCLK5S

AD16

IO_L95P_5/GCLK4P

AD17

IO_L94N_5

AL17

IO_L94P_5/VREF_5

AL18

IO_L93N_5

AG17

IO_L93P_5

AF17

IO_L92N_5

AE17

IO_L92P_5

AE18

IO_L91N_5

AK17

IO_L91P_5/VREF_5

AJ17

IO_L78N_5

AK18

IO_L78P_5

AK19

IO_L77N_5

AC17

IO_L77P_5

AB18

IO_L76N_5

AH18

IO_L76P_5

AH19

IO_L75N_5/VREF_5

AL19

IO_L75P_5

AL20

IO_L74N_5

AC18

IO_L74P_5

AC19

IO_L73N_5

AJ19

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

210

IO_L73P_5

AJ20

IO_L72N_5

AG18

IO_L72P_5

AG19

IO_L71N_5

AF18

IO_L71P_5

AF19

IO_L70N_5

AK20

IO_L70P_5

AK21

IO_L69N_5/VREF_5

AH20

IO_L69P_5

AH21

IO_L68N_5

AD19

IO_L68P_5

AD20

IO_L67N_5

AL21

IO_L67P_5

AL22

IO_L54N_5

AG20

IO_L54P_5

AG21

IO_L53N_5

AB19

IO_L53P_5

AB20

IO_L52N_5

AJ21

IO_L52P_5

AJ22

IO_L51N_5/VREF_5

AF20

IO_L51P_5

AF21

IO_L50N_5

AE20

IO_L50P_5

AE21

IO_L49N_5

AK22

IO_L49P_5

AK23

IO_L30N_5

AJ23

IO_L30P_5

AJ24

IO_L29N_5

AC20

IO_L29P_5

AC21

IO_L28N_5

AL23

IO_L28P_5

AL24

IO_L27N_5/VREF_5

AL25

IO_L27P_5

AL26

IO_L26N_5

AD21

IO_L26P_5

AD22

IO_L25N_5

AH23

IO_L25P_5

AH24

IO_L24N_5

AG22

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

211

IO_L24P_5

AG23

IO_L23N_5

AE22

IO_L23P_5

AE23

IO_L22N_5

AK25

IO_L22P_5

AK26

IO_L21N_5/VREF_5

AH25

IO_L21P_5

AG25

IO_L20N_5

AB21

IO_L20P_5

AC22

IO_L19N_5

AL27

IO_L19P_5

AL28

IO_L06N_5

AK27

IO_L06P_5

AJ27

IO_L05N_5/VRP_5

AD23

IO_L05P_5/VRN_5

AE24

IO_L04N_5

AJ26

IO_L04P_5/VREF_5

AH26

IO_L03N_5/D4/ALT_VRP_5

AF23

IO_L03P_5/D5/ALT_VRN_5

AF24

IO_L02N_5/D6

AG24

IO_L02P_5/D7

AF25

IO_L01N_5/RDWR_B

AK28

IO_L01P_5/CS_B

AK29

IO_L01P_6

AF27

IO_L01N_6

AF28

IO_L02P_6/VRN_6

AE26

IO_L02N_6/VRP_6

AE27

IO_L03P_6

AH29

IO_L03N_6/VREF_6

AH30

IO_L04P_6

AB22

IO_L04N_6

AB23

IO_L05P_6

AG28

IO_L05N_6

AG29

IO_L06P_6

AH31

IO_L06N_6

AG31

IO_L19P_6

AA22

IO_L19N_6

Y22

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

212

IO_L20P_6

AD25

IO_L20N_6

AC24

IO_L21P_6

AG30

IO_L21N_6/VREF_6

AF30

IO_L22P_6

AD26

IO_L22N_6

AC26

IO_L23P_6

AF29

IO_L23N_6

AD29

IO_L24P_6

AE28

IO_L24N_6

AD28

IO_L25P_6

AB24

IO_L25N_6

AA24

IO_L27P_6

AC25

IO_L27N_6/VREF_6

AB25

IO_L43P_6

AF31

IO_L43N_6

AE31

IO_L44P_6

AA23

IO_L44N_6

Y23

IO_L45P_6

AE30

IO_L45N_6/VREF_6

AC30

IO_L46P_6

AC28

IO_L46N_6

AA28

IO_L47P_6

AD27

IO_L47N_6

AC27

IO_L48P_6

AA25

IO_L48N_6

Y25

IO_L49P_6

AC29

IO_L49N_6

AB29

IO_L50P_6

AB27

IO_L50N_6

AA27

IO_L51P_6

AA26

IO_L51N_6/VREF_6

Y26

IO_L52P_6

AD31

IO_L52N_6

AC31

IO_L53P_6

W22

IO_L53N_6

V22

IO_L54P_6

Y27

IO_L54N_6

W27

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

213

IO_L67P_6

AB30

IO_L67N_6

AA30

IO_L68P_6

W26

IO_L68N_6

V26

IO_L69P_6

AB31

IO_L69N_6/VREF_6

AA31

IO_L70P_6

AA29

IO_L70N_6

Y29

IO_L71P_6

Y24

IO_L71N_6

W24

IO_L72P_6

V25

IO_L72N_6

U25

IO_L73P_6

Y28

IO_L73N_6

W28

IO_L74P_6

W23

IO_L74N_6

V23

IO_L75P_6

Y30

IO_L75N_6/VREF_6

W30

IO_L76P_6

Y31

IO_L76N_6

W31

IO_L77P_6

V27

IO_L77N_6

U27

IO_L78P_6

W29

IO_L78N_6

U29

IO_L91P_6

U23

IO_L91N_6

T23

IO_L92P_6

U26

IO_L92N_6

T26

IO_L93P_6

V28

IO_L93N_6/VREF_6

U28

IO_L94P_6

U24

IO_L94N_6

T24

IO_L95P_6

V30

IO_L95N_6

U30

IO_L96P_6

V31

IO_L96N_6

U31

IO_L96P_7

T27

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

214

IO_L96N_7

R27

IO_L95P_7

R24

IO_L95N_7

N24

IO_L94P_7

T29

IO_L94N_7

R29

IO_L93P_7/VREF_7

R31

IO_L93N_7

P31

IO_L92P_7

R26

IO_L92N_7

P26

IO_L91P_7

R30

IO_L91N_7

P30

IO_L78P_7

R25

IO_L78N_7

P25

IO_L77P_7

R28

IO_L77N_7

P28

IO_L76P_7

N31

IO_L76N_7

M31

IO_L75P_7/VREF_7

R23

IO_L75N_7

P23

IO_L74P_7

N30

IO_L74N_7

M30

IO_L73P_7

P27

IO_L73N_7

N27

IO_L72P_7

P22

IO_L72N_7

N22

IO_L71P_7

N29

IO_L71N_7

M29

IO_L70P_7

N28

IO_L70N_7

M28

IO_L69P_7/VREF_7

N26

IO_L69N_7

M26

IO_L68P_7

L31

IO_L68N_7

K31

IO_L67P_7

M27

IO_L67N_7

L27

IO_L54P_7

N23

IO_L54N_7

M23

IO_L53P_7

L30

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

215

IO_L53N_7

K30

IO_L52P_7

L28

IO_L52N_7

J28

IO_L51P_7/VREF_7

M24

IO_L51N_7

L24

IO_L50P_7

L29

IO_L50N_7

K29

IO_L49P_7

M25

IO_L49N_7

L25

IO_L48P_7

L26

IO_L48N_7

J26

IO_L47P_7

J31

IO_L47N_7

H31

IO_L46P_7

J29

IO_L46N_7

H29

IO_L45P_7/VREF_7

M22

IO_L45N_7

L22

IO_L44P_7

J30

IO_L44N_7

G30

IO_L43P_7

K27

IO_L43N_7

J27

IO_L27P_7/VREF_7

L23

IO_L27N_7

K23

IO_L25P_7

G31

IO_L25N_7

F31

IO_L24P_7

F30

IO_L24N_7

E30

IO_L23P_7

K25

IO_L23N_7

J25

IO_L22P_7

H28

IO_L22N_7

G28

IO_L21P_7/VREF_7

H27

IO_L21N_7

G27

IO_L20P_7

K24

IO_L20N_7

J24

IO_L19P_7

E31

IO_L19N_7

D31

IO_L06P_7

F28

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

216

IO_L06N_7

E28

IO_L05P_7

K22

IO_L05N_7

K21

IO_L04P_7

F29

IO_L04N_7

E29

IO_L03P_7/VREF_7

H26

IO_L03N_7

H25

IO_L02P_7/VRN_7

G26

IO_L02N_7/VRP_7

F27

IO_L01P_7

D30

IO_L01N_7

D29

VCCO_0

C18

VCCO_0

C25

VCCO_0

F22

VCCO_0

H18

VCCO_0

L17

VCCO_0

L18

VCCO_0

L19

VCCO_0

L20

VCCO_0

M17

VCCO_0

M18

VCCO_0

M19

VCCO_1

C14

VCCO_1

F10

VCCO_1

H14

VCCO_1

L12

VCCO_1

L13

VCCO_1

L14

VCCO_1

L15

VCCO_1

M13

VCCO_1

M14

VCCO_1

M15

VCCO_2

M11

VCCO_2

N11

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

217

VCCO_2

N12

VCCO_2

P11

VCCO_2

P12

VCCO_2

R11

VCCO_2

R12

VCCO_3

U11

VCCO_3

U12

VCCO_3

V11

VCCO_3

V12

VCCO_3

W11

VCCO_3

W12

VCCO_3

Y11

VCCO_3

AB6

VCCO_3

AE3

VCCO_4

Y13

VCCO_4

Y14

VCCO_4

Y15

VCCO_4

AA12

VCCO_4

AA13

VCCO_4

AA14

VCCO_4

AA15

VCCO_4

AD14

VCCO_4

AF10

VCCO_4

AJ7

VCCO_4

AJ14

VCCO_5

Y17

VCCO_5

Y18

VCCO_5

Y19

VCCO_5

AA17

VCCO_5

AA18

VCCO_5

AA19

VCCO_5

AA20

VCCO_5

AD18

VCCO_5

AF22

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

218

VCCO_5

AJ18

VCCO_5

AJ25

VCCO_6

U20

VCCO_6

U21

VCCO_6

V20

VCCO_6

V21

VCCO_6

V24

VCCO_6

V29

VCCO_6

W20

VCCO_6

W21

VCCO_6

Y21

VCCO_6

AB26

VCCO_6

AE29

VCCO_7

G29

VCCO_7

K26

VCCO_7

M21

VCCO_7

N20

VCCO_7

N21

VCCO_7

P20

VCCO_7

P21

VCCO_7

P24

VCCO_7

P29

VCCO_7

R20

VCCO_7

R21

CCLK

AJ4

PROG_B

D27

DONE

AG6

AH27

AJ28

AG26

HSWAP_EN

E26

TCK

K11

TDI

C28

TDO

TMS

J10

PWRDWN_B

AH5

DXN

F25

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

219

DXP

B28

VBATT

RSVD

VCCAUX

B16

VCCAUX

C30

VCCAUX

T30

VCCAUX

AJ2

VCCAUX

AJ30

VCCAUX

AK16

VCCINT

K15

VCCINT

K17

VCCINT

L11

VCCINT

L16

VCCINT

L21

VCCINT

M12

VCCINT

M16

VCCINT

M20

VCCINT

N13

VCCINT

N14

VCCINT

N15

VCCINT

N16

VCCINT

N17

VCCINT

N18

VCCINT

N19

VCCINT

P13

VCCINT

P19

VCCINT

R10

VCCINT

R13

VCCINT

R19

VCCINT

R22

VCCINT

T11

VCCINT

T12

VCCINT

T13

VCCINT

T19

VCCINT

T20

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

220

VCCINT

T21

VCCINT

U10

VCCINT

U13

VCCINT

U19

VCCINT

U22

VCCINT

V13

VCCINT

V19

VCCINT

W13

VCCINT

W14

VCCINT

W15

VCCINT

W16

VCCINT

W17

VCCINT

W18

VCCINT

W19

VCCINT

Y12

VCCINT

Y16

VCCINT

Y20

VCCINT

AA11

VCCINT

AA16

VCCINT

AA21

VCCINT

AB15

VCCINT

AB17

GND

A16

GND

A29

GND

A30

GND

B24

GND

B30

GND

B31

GND

C29

GND

C31

GND

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

221

GND

D10

GND

D16

GND

D22

GND

D28

GND

E27

GND

F26

GND

G13

GND

G16

GND

G19

GND

G25

GND

H24

GND

H30

GND

J23

GND

K16

GND

K28

GND

N25

GND

P14

GND

P15

GND

P16

GND

P17

GND

P18

GND

R14

GND

R15

GND

R16

GND

R17

GND

R18

GND

T10

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

222

GND

T14

GND

T15

GND

T16

GND

T17

GND

T18

GND

T22

GND

T25

GND

T28

GND

T31

GND

U14

GND

U15

GND

U16

GND

U17

GND

U18

GND

V14

GND

V15

GND

V16

GND

V17

GND

V18

GND

W25

GND

AB4

GND

AB16

GND

AB28

GND

AC9

GND

AC23

GND

AD2

GND

AD8

GND

AD24

GND

AD30

GND

AE7

GND

AE13

GND

AE16

GND

AE19

GND

AE25

GND

AF6

GND

AF26

GND

AG5

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

223

GND

AG27

GND

AH4

GND

AH10

GND

AH16

GND

AH22

GND

AH28

GND

AJ1

GND

AJ3

GND

AJ29

GND

AJ31

GND

AK1

GND

AK2

GND

AK8

GND

AK24

GND

AK30

GND

AK31

GND

AL2

GND

AL3

GND

AL16

GND

AL29

GND

AL30

Notes:
1.

See

Table 4

for an explanation of the signals available on this pin.

Table 14: BF957 -- XC2V2000, XC2V3000, XC2V4000, and XC2V6000

Bank

Pin Description

Pin Number

No Connect in XC2V2000

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

224

BF957 Flip-Chip BGA Package Specifications (1.27mm pitch)

Figure 10: BF957 Flip-Chip BGA Package Specifications

VirtexTM-II Platform FPGAs: Pinout Information

DS031-4 (v2.0) August 1, 2003

www.xilinx.com

Module 4 of 4

Product Specification

1-800-255-7778

225

Revision History

This section records the change history for this module of the data sheet.

Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

VirtexTM-II Platform FPGAs: Introduction and Overview
(Module 1)

VirtexTM-II Platform FPGAs: Detailed Description
(Module 2)

VirtexTM-II Platform FPGAs: DC and Switching
Characteristics (Module 3)

VirtexTM-II Platform FPGAs: Pinout Information
(Module 4)

Date

Version

Revision

11/07/00

1.0

Early access draft.

11/22/00

1.1

Initial Xilinx release. Made the following corrections:
CS144 package -

Table 5, page 5

Added missing pin D10 in Bank 1.

Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP).

FG256 package -

Table 6, page 10

Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP).

FG896 package -

Table 11, page 94

Corrected pin AG1 in Bank 4 to be AG12.

FF1152 package -

Table 12, page 120

Corrected pin Y3 in Bank 6 to be Y32.

12/19/00

1.2

Reverse designations were fixed for pins in every package.

01/25/01

1.3

The data sheet was divided into four modules (per the current style standard). DXN and
DXP pin information was added for the CS144 package (

Table 5

) and the FG256 package

(

Table 6

02/07/01

1.4

DXN and DXP pin information was changed back to RSVD for the CS144 package (

Table 5

)

and the FG256 package (

Table 6

04/02/01

1.5

ALT_VRN and ALT_VRP pin information was added for each package.

Table 8, page 34

added No Connect designations for the XC2V1500 device in the

FG676 package.

Reverted to traditional double-column format.

11/07/01

1.6

Updated list of devices supported in the FF1152, FF1517, and BF957 packages.

09/26/02

1.7

Updated

Table 3

to reflect devices supported in the BG728 and BF957 packages.

Added mention of LVPECL to pin definition in

Table 4

10/07/02

1.8

Corrected

Table 10

heading to reflect supported devices in the BG728 package.

12/06/02

1.8.1

Enhanced the description of the PWRDWN_B pin in

Table 4

05/07/03

1.8.2

Added clarification to

Table 4

and all device pinout tables regarding the dual-use

nature of pins D0/DIN and BUSY/DOUT during configuration.

06/19/03

1.8.3

The final GND pin in each of five pinout tables was inadvertently deleted in v1.8.2. This
revision restores the deleted GND pins as follows:
-

Pin C5,

Table 5, page 5

(CS144)

Pin A1,

Table 6, page 10

(FG256)

Pin A2,

Table 10, page 72

(BG728)

Pin A2,

Table 12, page 120

(FF1152)

Pin AL30,

Table 14, page 198

(BF957)

08/01/03

2.0

All Virtex-II devices and speed grades now Production. See Table 13, Module 3.

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Document Outline

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