December 4, 1998 (Version 3.0) 1
Features
7.5 ns pin-to-pin logic delays on all pins
f
CNT
to 125 MHz
108 macrocells with 2400 usable gates
Up to 108 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See
Figure 2
for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC95108
device.
1
XC95108 In-System Programmable
CPLD
December 4, 1998 (Version 3.0)
1
1*
Product Specification
Clock Frequency (MHz)
Typical I
CC
(mA)
0
50
100
(180)
(250)
(170)
200
300
100
High Performance
Low Power
X5898
Figure 1: Typical I
CC
vs. Frequency for XC95108
XC95108 In-System Programmable CPLD
2 December 4, 1998 (Version 3.0)
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
X5897
1
Function
Block 2
36
Function
Block 3
36
Function
Block 4
36
Macrocells
1 to 18
Function
Block 5
36
Macrocells
1 to 18
Function
Block 6
36
18
18
18
18
18
18
FastCONNECT Switch Matrix
Figure 2: XC95108 Architecture
Note:
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
December 4, 1998 (Version 3.0) 3
XC95108 In-System Programmable CPLD
Absolute Maximum Ratings
Warning:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operation Conditions
1
Note:
1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol Parameter Value Units
V
CC
Supply voltage relative to GND -0.5 to 7.0 V
V
IN
DC input voltage relative to GND -0.5 to V
CC
+ 0.5 V
V
TS
Voltage applied to 3-state output with respect to GND -0.5 to V
CC
+ 0.5 V
T
STG
Storage temperature -65 to +150
C
T
SOL
Max soldering temperature (10 s @ 1/16 in = 1.5 mm) +260
C
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic and input buffer 4.75
(4.5)
5.25
(5.5)
V
V
CCIO
Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V
Supply voltage for output drivers for 3.3 V operation 3.0 3.6 V
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 V
CCINT
+0.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
t
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles 10,000 - Cycles
XC95108 In-System Programmable CPLD
4 December 4, 1998 (Version 3.0)
DC Characteristics Over Recommended Operating Conditions
AC Characteristics
Note:
1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 5 V operation I
OH
= -4.0 mA
V
CC
= Min
2.4 V
Output high voltage for 3.3 V operation I
OH
= -3.2 mA
V
CC
= Min 2.4
V
V
OL
Output low voltage for 5 V operation
I
OL
= 24 mA
V
CC
= Min
0.5 V
Output low voltage for 3.3 V operation I
OL
= 10 mA
V
CC
= Min
0.4 V
I
IL
Input leakage current V
CC
= Max
V
IN
= GND or V
CC
10.0
A
I
IH
I/O high-Z leakage current V
CC
= Max
V
IN
= GND or V
CC
10.0
A
C
IN
I/O capacitance V
IN
= GND
f = 1.0 MHz
10.0 pF
I
CC
Operating Supply Current
(low power mode, active)
V
I
= GND, No load
f = 1.0 MHz
100 (Typ) ma
Symbol Parameter
XC95108-7 XC95108-10
XC95108-15 XC95108-20
Units
Min Max Min Max Min Max Min Max
t
PD
I/O to output valid 7.5 10.0 15.0 20.0 ns
t
SU
I/O setup time before GCK 4.5 6.0 8.0 10.0 ns
t
H
I/O hold time after GCK 0.0 0.0 0.0 0.0 ns
t
CO
GCK to output valid 4.5 6.0 8.0 10.0 ns
f
CNT
1
16-bit counter frequency 125.0 111.1 95.2 83.3 MHz
f
SYSTEM
2
Multiple FB internal operating frequency 83.3 66.7 55.6 50.0 MHz
t
PSU
I/O setup time before p-term clock input 0.5 2.0 4.0 4.0 ns
t
PH
I/O hold time after p-term clock input 4.0 4.0 4.0 6.0 ns
t
PCO
P-term clock to output valid 8.5 10.0 12.0 16.0 ns
t
OE
GTS to output valid 5.5 6.0 11.0 16.0 ns
t
OD
GTS to output disable 5.5 6.0 11.0 16.0 ns
t
POE
Product term OE to output enabled 9.5 10.0 14.0 18.0 ns
t
POD
Product term OE to output disabled 9.5 10.0 14.0 18.0 ns
t
WLH
GCK pulse width (High or Low) 4.0 4.5 5.5 5.5 ns
December 4, 1998 (Version 3.0) 5
XC95108 In-System Programmable CPLD
Internal Timing Parameters
Note:
3. t
PTA
is multiplied by the span of the function as defined in the family data sheet.
Symbol Parameter
XC95108-7 XC95108-10
XC95108-15 XC95108-20
Units
Min Max Min Max Min Max Min Max
Buffer Delays
t
IN
Input buffer delay 2.5 3.5 4.5 6.5 ns
t
GCK
GCK buffer delay 1.5 2.5 3.0 3.0 ns
t
GSR
GSR buffer delay 4.5 6.0 7.5 9.5 ns
t
GTS
GTS buffer delay 5.5 6.0 11.0 16.0 ns
t
OUT
Output buffer delay 2.5 3.0 4.5 6.5 ns
t
EN
Output buffer enable/disable delay 0.0 0.0 0.0 0.0 ns
Product Term Control Delays
t
PTCK
Product term clock delay 3.0 3.0 2.5 2.5 ns
t
PTSR
Product term set/reset delay 2.0 2.5 3.0 3.0 ns
t
PTTS
Product term 3-state delay 4.5 3.5 5.0 5.0 ns
Internal Register and Combinatorial delays
t
PDI
Combinatorial logic propagation delay 0.5 1.0 3.0 4.0 ns
t
SUI
Register setup time 1.5 2.5 3.5 3.5 ns
t
HI
Register hold time 3.0 3.5 4.5 6.5 ns
t
COI
Register clock to output valid time 0.5 0.5 0.5 0.5 ns
t
AOI
Register async. S/R to output delay 6.5 7.0 8.0 8.0 ns
t
RAI
Register async. S/R recovery before clock 7.5 10.0 10.0 10.0 ns
t
LOGI
Internal logic delay 2.0 2.5 3.0 3.0 ns
t
LOGILP
Internal low power logic delay 10.0 11.0 11.5 11.5 ns
Feedback Delays
t
F
FastCONNECT matrix feedback delay 8.0 9.5 11.0 13.0 ns
t
LF
Function Block local feeback delay 4.0 3.5 3.5 5.0 ns
Time Adders
t
PTA
3
Incremental Product Term Allocator delay 1.0 1.0 1.0 1.5 ns
t
SLEW
Slew-rate limited delay 4.0 4.5 5.0 5.5 ns
R
1
V
TEST
C
L
R
2
Device Output
Output Type V
TEST
5.0 V
3.3 V
R
1
160
260
R
2
120
360
C
L
35 pF
35 pF
X5906
V
CCIO
5.0 V
3.3 V
Figure 3: AC Load Circuit
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