DS056 (v1.5) August 21, 2003
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
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http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
-
100-pin TQFP (81 user I/O pins)
-
144-pin TQFP (117 user I/O pins)
-
144-CSP (117 user I/O pins)
Optimized for high-performance 3.3V systems
-
Low power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
-
3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
Fast FLASHTM technology
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECTTM II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin with local
inversion
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See
Figure 2
for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HS
(0.175*PT
HS
+ 0.345) + MC
LP
(0.052*PT
LP
+ 0.272) + 0.04 * MC
TOG
(MC
HS
+MC
LP
)* f
where:
MC
HS
= # macrocells in high-speed configuration
PT
HS
= average number of high-speed product terms
per macrocell
MC
LP
= # macrocells in low power configuration
PT
LP
= average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
XAPP114, "Understanding XC9500XL
CPLD Power."
0
XC95144XL High Performance
CPLD
DS056 (v1.5) August 21, 2003
0
5
Preliminary Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XC95144XL
Clock Frequency (MHz)
Typical I
CC
(mA)
100
200
DS056_01_121501
200
250
50
50
150
150
100
0
104 MHz
High
Performance
178 MHz
Low
Powe
r
XC95144XL High Performance CPLD
DS056 (v1.5) August 21, 2003
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol
Description
Value
Units
V
CC
Supply voltage relative to GND
0.5 to 4.0
V
V
IN
Input voltage relative to GND
(1)
0.5 to 5.5
V
V
TS
Voltage applied to 3-state output
(1)
0.5 to 5.5
V
T
STG
Storage temperature (ambient)
65 to +150
o
C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
+220
o
C
T
J
Junction temperature
+150
o
C
Notes:
1.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to 2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol
Parameter
Min
Max
Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to 70
o
C
3.0
3.6
V
Industrial T
A
= 40
o
C to +85
o
C
3.0
3.6
V
V
CCIO
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.3
2.7
V
V
IL
Low-level input voltage
0
0.80
V
V
IH
High-level input voltage
2.0
5.5
V
V
O
Output voltage
0
V
CCIO
V
Symbol
Parameter
Min
Max
Units
T
DR
Data Retention
20
-
Years
N
PE
Program/Erase Cycles (Endurance)
10,000
-
Cycles
V
ESD
Electrostatic Discharge (ESD)
2,000
-
Volts
Symbol
Parameter
Test Conditions
Min
Max
Units
V
OH
Output high voltage for 3.3V outputs
I
OH
= 4.0 mA
2.4
-
V
Output high voltage for 2.5V outputs
I
OH
= 500
A
90% V
CCIO
-
V
V
OL
Output low voltage for 3.3V outputs
I
OL
= 8.0 mA
-
0.4
V
Output low voltage for 2.5V outputs
I
OL
= 500
A
-
0.4
V
I
IL
Input leakage current
V
CC
= Max; V
IN
= GND or V
CC
-
10
A
I
IH
I/O high-Z leakage current
V
CC
= Max; V
IN
= GND or V
CC
-
10
A
I
IH
I/O high-Z leakage current
V
CC
= Max; V
CCIO
= Max;
V
IN
= GND or 3.6V
-
10
A
V
CC
Min < V
IN
< 5.5V
-
50
A
C
IN
I/O capacitance
V
IN
= GND; f = 1.0 MHz
-
10
pF
I
CC
Operating supply current
(low power mode, active)
V
IN
= GND, No load; f = 1.0 MHz
45 (Typical)
mA
XC95144XL High Performance CPLD
4
www.xilinx.com
DS056 (v1.5) August 21, 2003
1-800-255-7778
Preliminary Product Specification
R
AC Characteristics
Symbol
Parameter
XC95144XL-5
XC95144XL-7
XC95144XL-10
Units
Min
Max
Min
Max
Min
Max
T
PD
I/O to output valid
-
5.0
-
7.5
-
10.0
ns
T
SU
I/O setup time before GCK
3.7
-
4.8
-
6.5
-
ns
T
H
I/O hold time after GCK
0
-
0
-
0
-
ns
T
CO
GCK to output valid
-
3.5
-
4.5
-
5.8
ns
f
SYSTEM
Multiple FB internal operating frequency
-
178.6
-
125.0
-
100.0
MHz
T
PSU
I/O setup time before p-term clock input
1.7
-
1.6
-
2.1
-
ns
T
PH
I/O hold time after p-term clock input
2.0
-
3.2
-
4.4
-
ns
T
PCO
P-term clock output valid
-
5.5
-
7.7
-
10.2
ns
T
OE
GTS to output valid
-
4.0
-
5.0
-
7.0
ns
T
OD
GTS to output disable
-
4.0
-
5.0
-
7.0
ns
T
POE
Product term OE to output enabled
-
7.0
-
9.5
-
11.0
ns
T
POD
Product term OE to output disabled
-
7.0
-
9.5
-
11.0
ns
T
AO
GSR to output valid
-
10.0
-
12.0
-
14.5
ns
T
PAO
P-term S/R to output valid
-
10.5
-
12.6
-
15.3
ns
T
WLH
GCK pulse width (High or Low)
2.8
-
4.0
-
4.5
-
ns
T
PLH
P-term clock pulse width (High or Low)
5.0
-
6.5
-
7.0
-
ns
Figure 3: AC Load Circuit
Device Output
Output Type
V
TEST
3.3V
2.5V
V
TEST
R
1
320
250
R
1
R
2
C
L
R
2
360
660
C
L
35 pF
35 pF
DS058_03_081500
V
CCIO
3.3V
2.5V
XC95144XL High Performance CPLD
DS056 (v1.5) August 21, 2003
www.xilinx.com
5
Preliminary Product Specification
1-800-255-7778
R
Internal Timing Parameters
Symbol
Parameter
XC95144XL-5
XC95144XL-7
XC95144XL-10
Units
Min
Max
Min
Max
Min
Max
Buffer Delays
T
IN
Input buffer delay
-
1.5
-
2.3
-
3.5
ns
T
GCK
GCK buffer delay
-
1.1
-
1.5
-
1.8
ns
T
GSR
GSR buffer delay
-
2.0
-
3.1
-
4.5
ns
T
GTS
GTS buffer delay
-
4.0
-
5.0
-
7.0
ns
T
OUT
Output buffer delay
-
2.0
-
2.5
-
3.0
ns
T
EN
Output buffer enable/disable
delay
-
0
-
0
-
0
ns
Product Term Control Delays
T
PTCK
Product term clock delay
-
1.6
-
2.4
-
2.7
ns
T
PTSR
Product term set/reset delay
-
1.0
-
1.4
-
1.8
ns
T
PTTS
Product term 3-state delay
-
5.5
-
7.2
-
7.5
ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay
-
0.5
-
1.3
-
1.7
ns
T
SUI
Register setup time
2.3
-
2.6
-
3.0
-
ns
T
HI
Register hold time
1.4
-
2.2
-
3.5
-
ns
T
ECSU
Register clock enable setup time
2.3
-
2.6
-
3.0
-
ns
T
ECHO
Register clock enable hold time
1.4
-
2.2
-
3.5
-
ns
T
COI
Register clock to output valid time
-
0.4
-
0.5
-
1.0
ns
T
AOI
Register async. S/R to output delay
-
6.0
-
6.4
-
7.0
ns
T
RAI
Register async. S/R recover before clock
5.0
7.5
10.0
ns
T
LOGI
Internal logic delay
-
1.0
-
1.4
-
1.8
ns
T
LOGILP
Internal low power logic delay
-
5.0
-
6.4
-
7.3
ns
Feedback Delays
T
F
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
T
PTA
Incremental product term allocator delay
-
0.7
-
0.8
-
1.0
ns
T
SLEW
Slew-rate limited delay
-
3.0
-
4.0
-
4.5
ns
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