http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-1 (v2.3) July 17, 2002

www.xilinx.com

Module 1 of 4

Production Product Specification

1-800-255-7778

Features

Fast, High-Density 1.8 V FPGA Family

Densities from 58 k to 4 M system gates

130 MHz internal performance (four LUT levels)

Designed for low-power operation

PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz

Highly Flexible SelectI/O+TM Technology

Supports 20 high-performance interface standards

Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s

Differential Signalling Support

LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

Differential I/O signals can be input, output, or I/O

Compatible with standard differential devices

LVPECL and LVDS clock inputs for 300+ MHz
clocks

Proprietary High-Performance SelectLinkTM
Technology

Double Data Rate (DDR) to Virtex-E link

Web-based HDL generation methodology

Sophisticated SelectRAM+TM Memory Hierarchy

1 Mb of internal configurable distributed RAM

Up to 832 Kb of synchronous internal block RAM

True Dual-Port BlockRAM capability

Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)

Designed for high-performance Interfaces to
External Memories

200 MHz ZBT* SRAMs

200 Mb/s DDR SDRAMs

Supported by free Synthesizable reference design

High-Performance Built-In Clock Management Circuitry

Eight fully digital Delay-Locked Loops (DLLs)

Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications

Clock Multiply and Divide

Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard

Flexible Architecture Balances Speed and Density

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input function

Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

Supported by Xilinx FoundationTM and Alliance SeriesTM
Development Systems

Further compile time reduction of 50%

Internet Team Design (ITD) tool ideal for
million-plus gate density designs

Wide selection of PC and workstation platforms

SRAM-Based In-System Configuration

Unlimited re-programmability

Advanced Packaging Options

0.8 mm Chip-scale

1.0 mm BGA

1.27 mm BGA

HQ/PQ

0.18

µm 6-Layer Metal Process

100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

VirtexTM-E 1.8 V
Field Programmable Gate Arrays

DS022-1 (v2.3) July 17, 2002

Production Product Specification

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 1 of 4

www.xilinx.com

DS022-1 (v2.3) July 17, 2002

1-800-255-7778

Production Product Specification

Virtex-E Compared to Virtex Devices

The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.

I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.

Virtex-E devices have up to 640 Kb of faster (250 MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.

CCINT

, the supply voltage for the internal logic and mem-

ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18

µm design rules have resulted in

smaller dice, faster speed, and lower power consumption.

I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100

resistor. PCI 5 V is not supported. With the

addition of appropriate external resistors, any pin can toler-
ate any voltage desired.

Banking rules are different. With Virtex devices, all input
buffers are powered by V

CCINT

. With Virtex-E devices, the

LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V

CCO

The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.

The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.

General Description

The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18

µm CMOS process. These

advances make Virtex-E FPGAs powerful and flexible alter-
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in

Table 1

Building on experience gained from Virtex FPGAs, the
Virtex-E family is an evolutionary step forward in program-
mable logic design. Combining a wide variety of program-
mable system features, a rich hierarchy of fast, flexible
interconnect resources, and advanced process technology,
the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.

Virtex-E Architecture

Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing

Table 1: Virtex-E Field-Programmable Gate Array Family Members

Device

System

Gates

Logic

Gates

CLB

Array

Logic

Cells

Differential

I/O Pairs

User

I/O

BlockRAM

Bits

Distributed

RAM Bits

XCV50E

71,693

20,736

16 x 24

1,728

176

65,536

24,576

XCV100E

128,236

32,400

20 x 30

2,700

196

81,920

38,400

XCV200E

306,393

63,504

28 x 42

5,292

119

284

114,688

75,264

XCV300E

411,955

82,944

32 x 48

6,912

137

316

131,072

98,304

XCV400E

569,952

129,600

40 x 60

10,800

183

404

163,840

153,600

XCV600E

985,882

186,624

48 x 72

15,552

247

512

294,912

221,184

XCV1000E

1,569,178

331,776

64 x 96

27,648

281

660

393,216

XCV1600E

2,188,742

419,904

72 x 108

34,992

344

724

589,824

497,664

XCV2000E

2,541,952

518,400

80 x 120

43,200

344

804

655,360

614,400

XCV2600E

3,263,755

685,584

92 x 138

57,132

344

804

753,664

812,544

XCV3200E

4,074,387

876,096

104 x 156

73,008

344

804

851,968

1,038,336

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-1 (v2.3) July 17, 2002

www.xilinx.com

Module 1 of 4

Production Product Specification

1-800-255-7778

resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.

Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAPTM, slave serial, and JTAG modes).

The standard Xilinx Foundation SeriesTM and Alliance
SeriesTM Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.

Higher Performance

Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.

While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.

Table 2

shows performance data for

representative circuits, using worst-case timing parameters.

Virtex-E Device/Package Combinations and Maximum I/O

Table 2: Performance for Common Circuit Functions

Function

Bits

Virtex-E (-7)

Adder

4.3 ns

6.3 ns

Pipelined Multiplier

8 x 8

16 x 16

4.4 ns

5.1 ns

Address Decoder

3.8 ns

5.5 ns

16:1 Multiplexer

4.6 ns

Parity Tree

3.5 ns

4.3 ns

5.9 ns

Chip-to-Chip

HSTL Class IV

LVTTL,16mA, fast slew

LVDS

LVPECL

Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)

XCV

50E

XCV

100E

XCV

200E

XCV

300E

XCV

400E

XCV

600E

XCV

1000E

XCV

1600E

XCV

2000E

XCV

2600E

XCV

3200E

CS144

PQ240

158

HQ240

158

BG352

196

260

BG432

316

BG560

404

FG256

176

FG456

284

312

FG676

404

444

FG680

512

FG860

660

FG900

512

660

700

FG1156

660

724

804

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 1 of 4

www.xilinx.com

DS022-1 (v2.3) July 17, 2002

1-800-255-7778

Production Product Specification

Virtex-E Ordering Information

Revision History

The following table shows the revision history for this document.

Figure 1: Ordering Information

Date

Version

Revision

12/7/99

1.0

Initial Xilinx release.

1/10/00

1.1

Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.

1/28/00

1.2

Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T

BYP

values, buffered Hex Line info, p. 8, I/O Timing

Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.

2/29/00

1.3

Updated pinout tables, V

page 20, and corrected Figure 20.

5/23/00

1.4

Correction to table on p. 22.

7/10/00

1.5

Numerous minor edits.

Data sheet upgraded to Preliminary.

Preview -8 numbers added to Virtex-E Electrical Characteristics tables.

8/1/00

1.6

Reformatted entire document to follow new style guidelines.

Changed speed grade values in tables on pages 35-37.

9/20/00

1.7

Min values added to Virtex-E Electrical Characteristics tables.

XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).

Corrected user I/O count for XCV100E device in Table 1 (Module 1).

Changed several pins to "No Connect in the XCV100E" and removed duplicate V

CCINT

pins in Table ~ (Module 4).

Changed pin J10 to "No connect in XCV600E" in Table 74 (Module 4).

Changed pin J30 to "VREF option only in the XCV600E" in Table 74 (Module 4).

Corrected pair 18 in Table 75 (Module 4) to be "AO in the XCV1000E, XCV1600E".

Example: XCV300E-6PQ240C

Device Type

Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)

Number of Pins

Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation

Speed Grade

(-6, -7, -8)

DS022_043_072000

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-1 (v2.3) July 17, 2002

www.xilinx.com

Module 1 of 4

Production Product Specification

1-800-255-7778

Virtex-E Data Sheet

The Virtex-E Data Sheet contains the following modules:

DS022-1, Virtex-E 1.8V FPGAs:

Introduction and Ordering Information (Module 1)

DS022-2, Virtex-E 1.8V FPGAs:

Functional Description (Module 2)

DS022-3, Virtex-E 1.8V FPGAs:

DC and Switching Characteristics (Module 3)

DS022-4, Virtex-E 1.8V FPGAs:

Pinout Tables (Module 4)

11/20/00

1.8

Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.

Updated minimums in Table 13 and added notes to Table 14.

Added to note 2 to Absolute Maximum Ratings.

Changed speed grade -8 numbers for T

SHCKO32

, T

REG

, T

BCCS

, and T

ICKOF

Changed all minimum hold times to 0.4 under Global Clock Setup and Hold for
LVTTL Standard, with DLL.

Revised maximum T

DLLPW

in -6 speed grade for DLL Timing Parameters.

Changed GCLK0 to BA22 for FG860 package in Table 46.

2/12/01

1.9

Revised footnote for Table 14.

Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.

Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.

Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.

Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.

4/2/01

2.0

Updated numerous values in

Virtex-E Switching Characteristics

tables.

Converted data sheet to modularized format. See the

Virtex-E Data Sheet

section.

10/25/01

2.1

Updated the

Virtex-E Device/Package Combinations and Maximum I/O

table to

show XCV3200E in the FG1156 package.

11/09/01

2.2

Minor edits.

07/17/02

2.3

Data sheet designation upgraded from Preliminary to Production.

Date

Version

Revision

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Architectural Description

Virtex-E Array

The Virtex-E user-programmable gate array, shown in

Figure 1

, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks (IOBs).

CLBs provide the functional elements for constructing
logic

IOBs provide the interface between the package pins
and the CLBs

CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlockTM that also provides local
routing resources to connect the CLB to the GRM.

The VersaRingTM I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.

The Virtex-E architecture also includes the following circuits
that connect to the GRM.

Dedicated block memories of 4096 bits each

Clock DLLs for clock-distribution delay compensation
and clock domain control

3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources

Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.

Input/Output Block

The Virtex-E IOB,

Figure 2

, features SelectI/O+ inputs and

outputs that support a wide variety of I/O signalling stan-
dards, see

Table 1

The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.

VirtexTM-E 1.8 V
Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

Production Product Specification

Figure 1: Virtex-E Architecture Overview

DLLDLL

IOBs

VersaRing

ds022_01_121099

CLBs

BRAMs

CLBs

BRAMs

CLBs

DLLDLL

Figure 2: Virtex-E Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

T
TCE

D
CE

PAD

Programmable

Delay

Weak

Keeper

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.

The output buffer and all of the IOB control signals have
independent polarity controls.

All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to V

CCO

with

the exception of LVCMOS18, LVCMOS25, GTL, GTL+,
LVDS, and LVPECL.

Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but I/Os can optionally be pulled up.

The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.

All Virtex-E IOBs support IEEE 1149.1-compatible bound-
ary scan testing.

Input Path

The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.

An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V

REF

. The need to supply V

REF

imposes

constraints on which standards can be used in close prox-
imity to each other. See

I/O Banking

There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 100 k

Output Path

The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.

Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.

In most signalling standards, the output High voltage
depends on an externally supplied V

CCO

voltage. The need

to supply V

CCO

imposes constraints on which standards

can be used in close proximity to each other. See

I/O Bank-

ing

An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.

Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate V

REF

voltage must be

provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.

I/O Banking

Some of the I/O standards described above require V

CCO

and/or V

REF

voltages. These voltages are externally sup-

plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.

Table 1: Supported I/O Standards

I/O

Standard

Output

CCO

Input

CCO

Input

REF

Board

Termination

Voltage (V

)

LVTTL

3.3

N/A

LVCMOS2

2.5

N/A

LVCMOS18

1.8

N/A

SSTL3 I & II

3.3

N/A

1.50

SSTL2 I & II

2.5

N/A

1.25

GTL

N/A

0.80

1.20

GTL+

N/A

1.0

1.50

HSTL I

1.5

N/A

0.75

HSTL III & IV

1.5

N/A

0.90

1.50

CTT

3.3

N/A

1.50

AGP-2X

3.3

N/A

1.32

N/A

PCI33_3 3.3

3.3

N/A

PCI66_3 3.3

3.3

N/A

BLVDS & LVDS

2.5

N/A

LVPECL

3.3

N/A

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in

Figure 3

. Each bank has

multiple V

CCO

pins, all of which must be connected to the

same voltage. This voltage is determined by the output
standards in use.

Within a bank, output standards can be mixed only if they
use the same V

CCO

. Compatible standards are shown in

Table 2

. GTL and GTL+ appear under all voltages because

their open-drain outputs do not depend on V

CCO

Some input standards require a user-supplied threshold
voltage, V

REF

. In this case, certain user-I/O pins are auto-

matically configured as inputs for the V

REF

voltage. Approx-

imately one in six of the I/O pins in the bank assume this
role.

The V

REF

pins within a bank are interconnected internally

and consequently only one V

REF

voltage can be used within

each bank. All V

REF

pins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Within a bank, inputs that require V

REF

can be mixed with

those that do not. However, only one V

REF

voltage can be

used within a bank.

In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
V

CCO

rather than V

CCINT

. For these standards, only input

and output buffers that have the same V

CCO

can be mixed

together.

The V

CCO

and V

REF

pins for each bank appear in the device

pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.

Within a given package, the number of V

REF

and V

CCO

pins

can vary depending on the size of device. In larger devices,
more I/O pins convert to V

REF

pins. Since these are always

a super set of the V

REF

pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger
device if necessary. All the V

REF

pins for the largest device

anticipated must be connected to the V

REF

voltage, and not

used for I/O.

In smaller devices, some V

CCO

pins used in larger devices

do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the V

CCO

voltage to permit migration to a larger device if

necessary.

Configurable Logic Blocks

The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in

Figure 4

Figure 5

shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.

Look-Up Tables

Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.

The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.

Figure 3: Virtex-E I/O Banks

Table 2: Compatible Output Standards

CCO

Compatible Standards

3.3 V

PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+, LVPECL

2.5 V

SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,

BLVDS, LVDS

1.8 V

LVCMOS18, GTL, GTL+

1.5 V

HSTL I, HSTL III, HSTL IV, GTL, GTL+

ds022_03_121799

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5

Bank 4

VirtexE

Device

Bank 7

Bank 6

Bank 2

Bank 3

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Storage Elements

The storage elements in the Virtex-E slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by

the function generators within the slice or directly from slice
inputs, bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR

Figure 4: 2-Slice Virtex-E CLB

Carry &

Control

Carry &

Control

Carry &

Control

Carry &

Control

LUT

CIN

COUT

Slice 1

Slice 0

LUT

ds022_04_121799

Figure 5: Detailed View of Virtex-E Slice

F5IN

CLK

G4
G3
G2
G1

F4
F3
F2
F1

CIN

ds022_05_092000

COUT

D
CE

WSO

WSH

BY DG

I3
I2
I1
I0

LUT

I3
I2
I1
I0

LUT

INIT

REV

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to oper-
ate asynchronously. All of the control signals are indepen-
dently invertible, and are shared by the two flip-flops within
the slice.

Additional Logic

The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.

Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.

Each CLB has four direct feedthrough paths, two per slice.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.

Arithmetic Logic

Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex-E CLB
supports two separate carry chains, one per Slice. The
height of the carry chains is two bits per CLB.

The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation. The dedicated carry path can also be used
to cascade function generators for implementing wide logic
functions.

BUFTs

Each Virtex-E CLB contains two 3-state drivers (BUFTs)
that can drive on-chip busses. See

Dedicated Routing

Each Virtex-E BUFT has an independent 3-state control pin
and an independent input pin.

Block SelectRAM

Virtex-E FPGAs incorporate large block SelectRAM memo-
ries. These complement the Distributed SelectRAM memo-
ries that provide shallow RAM structures implemented in
CLBs.

Block SelectRAM memory blocks are organized in columns,
starting at the left (column 0) and right outside edges and
inserted every 12 CLB columns (see notes for smaller
devices). Each memory block is four CLBs high, and each
memory column extends the full height of the chip, immedi-
ately adjacent (to the right, except for column 0) of the CLB
column locations indicated in

Table 3

Table 4

shows the amount of block SelectRAM memory that

is available in each Virtex-E device.

As illustrated in

Figure 6

, each block SelectRAM cell is a

fully synchronous dual-ported (True Dual Port) 4096-bit
RAM with independent control signals for each port. The
data widths of the two ports can be configured indepen-
dently, providing built-in bus-width conversion.

Table 3: CLB/Block RAM Column Locations

XCV

Device

/Col.

0 12 24

36 48

108

120

138

156

50E

Columns 0, 6, 18, & 24

100E

Columns 0, 12, 18, & 30

200E

Columns 0, 12, 30, & 42

300E

400E

600E

1000E

1600E

2000E

2600E

3200E

Table 4: Virtex-E Block SelectRAM Amounts

Virtex-E Device

# of Blocks

Block SelectRAM Bits

XCV50E

65,536

XCV100E

81,920

XCV200E

114,688

XCV300E

131,072

XCV400E

163,840

XCV600E

294,912

XCV1000E

393,216

XCV1600E

144

589,824

XCV2000E

160

655,360

XCV2600E

184

753,664

XCV3200E

208

851,968

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Table 5

shows the depth and width aspect ratios for the

block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAMs. Refer to
XAPP130 for block SelectRAM timing waveforms.

Programmable Routing Matrix

It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization mini-
mizes long-path delays, and consequently, yields the best
system performance.

The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.

Local Routing

The VersaBlock provides local routing resources (see

Figure 7

), providing three types of connections:

Interconnections among the LUTs, flip-flops, and GRM

Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay

Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM.

General Purpose Routing

Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. General-purpose routing resources are located in
horizontal and vertical routing channels associated with the
CLB rows and columns and are as follows:

Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.

24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.

72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.

12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.

I/O Routing

Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.

Figure 6: Dual-Port Block SelectRAM

Table 5: Block SelectRAM Port Aspect Ratios

Width

Depth

ADDR Bus

Data Bus

4096

ADDR<11:0>

DATA<0>

2048

ADDR<10:0>

DATA<1:0>

1024

ADDR<9:0>

DATA<3:0>

512

ADDR<8:0>

DATA<7:0>

256

ADDR<7:0>

DATA<15:0>

WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]

WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_06_121699

Figure 7: Virtex-E Local Routing

XCVE_ds_007

CLB

GRM

Adjacent

GRM

To Adjacent
GRM

Direct
Connection
To Adjacent
CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Dedicated Routing

Some classes of signal require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedi-
cated routing resources are provided for two classes of signal.

Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in

Figure 8

Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.Global Clock Distribution
Network

DLL Location

Clock Routing

Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.

The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.

The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.

Global Clock Distribution

Virtex-E provides high-speed, low-skew clock distribution
through the global routing resources described above. A
typical clock distribution net is shown in

Figure 9

Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
global nets that in turn drive any clock pin.

Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the gen-
eral purpose routing.

Digital Delay-Locked Loops

There are eight DLLs (Delay-Locked Loops) per device,
with four located at the top and four at the bottom,

Figure 10

. The DLLs can be used to eliminate skew

between the clock input pad and the internal clock input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges arrive
at internal flip-flops synchronized with clock edges arriving
at the input.

In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.

Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes

CLB

buft_c.eps

Tri-State

Lines

Figure 9: Global Clock Distribution Network

Gl
ob
al

Clo

k Sp

Global Clock Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

Global Clock Rows

XCVE_009

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to de-skew a board level clock among multiple
devices.

To guarantee that the system clock is operating correctly
prior to the FPGA starting up after configuration, the DLL
can delay the completion of the configuration process until
after it has achieved lock. For more information about DLL
functionality, see the Design Consideration section of the
data sheet.

Boundary Scan

Virtex-E devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-
tion/readback of the device.

The JTAG input pins (TDI, TMS, TCK) do not have a V

CCO

requirement and operate with either 2.5 V or 3.3 V input sig-
nalling levels. The output pin (TDO) is sourced from the
V

CCO

in bank 2, and for proper operation of LVTTL 3.3 V lev-

els, the bank should be supplied with 3.3 V.

Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections, provided the user
design or application is turned off.

Table 6

lists the boundary-scan instructions supported in

Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.

Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.

In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.

Figure 11

is a diagram of the Virtex-E Series boundary scan

logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.

Figure 10: DLL Locations

XCVE_0010

DLLDLL

Primary DLLs

Secondar

y DLLs

Secondar

y DLLs

DLLDLL

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Instruction Set

The Virtex-E series boundary-scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in

Table 6

Figure 11: Virtex-E Family Boundary Scan Logic

IOB

M
U

BYPASS

IOB

TDO

TDI

IOB

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE

CLOCK DATA

DATAOUT

UPDATE

EXTEST

X9016

INSTRUCTION REGISTER

Table 6: Boundary Scan Instructions

Boundary-Scan

Command

Binary

Code(4:0)

Description

EXTEST

00000

Enables boundary-scan
EXTEST operation

SAMPLE/
PRELOAD

00001

Enables boundary-scan
SAMPLE/PRELOAD
operation

USER1

00010

Access user-defined
register 1

USER2

00011

Access user-defined
register 2

CFG_OUT

00100

Access the
configuration bus for
read operations.

CFG_IN

00101

Access the
configuration bus for
write operations.

INTEST

00111

Enables boundary-scan
INTEST operation

USERCODE

01000

Enables shifting out
USER code

IDCODE

01001

Enables shifting out of
ID Code

HIGHZ

01010

3-states output pins
while enabling the
Bypass Register

JSTART

01100

Clock the start-up
sequence when
StartupClk is TCK

BYPASS

11111

Enables BYPASS

RESERVED

All other

codes

Xilinx reserved
instructions

Table 6: Boundary Scan Instructions (Continued)

Boundary-Scan

Command

Binary

Code(4:0)

Description

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Data Registers

The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out, and 3-State Control. Non-IOB pins have
appropriate partial bit population if input-only or output-only.
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins.

The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.

The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.

Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).

Bit Sequence

The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.

From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the boundary scan
data-register bits are ordered as shown in

Figure 12

BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.

Identification Registers

The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the family code (05 for Virtex-E family)

a = the number of CLB rows (ranges from 16 for

XCV50E to 104 for XCV3200E)

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see

Table 7

) is embedded in the bitstream during bit-

stream generation and is valid only after configuration.

Note:

Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.

If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.

Figure 12: Boundary Scan Bit Sequence

Bit 0 ( TDO end)
Bit 1
Bit 2

Right half of top-edge IOBs (Right to Left)

GCLK2
GCLK3

Left half of top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

M1
M0
M2

Left half of bottom-edge IOBs (Left to Right)

GCLK1
GCLK0

Right half of bottom-edge IOBs (Left to Right)

DONE
PROG

Right-edge IOBs (Bottom to Top)

CCLK

(TDI end)

990602001

Table 7: IDCODEs Assigned to Virtex-E FPGAs

FPGA

IDCODE

XCV50E

v0A10093h

XCV100E

v0A14093h

XCV200E

v0A1C093h

XCV300E

v0A20093h

XCV400E

v0A28093h

XCV600E

v0A30093h

XCV1000E

v0A40093h

XCV1600E

v0A48093h

XCV2000E

v0A50093h

XCV2600E

v0A5C093h

XCV3200E

v0A68093h

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Development System

Virtex-E FPGAs are supported by the Xilinx Foundation and
Alliance Series CAE tools. The basic methodology for
Virtex-E design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.

The Xilinx development system is integrated under the
Xilinx Design Manager (XDMTM) software, providing design-
ers with a common user interface regardless of their choice
of entry and verification tools. The XDM software simplifies
the selection of implementation options with pull-down
menus and on-line help.

Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is gener-
ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex-E design.
RPMs, for example, are schematic-based macros with relative
location constraints to guide their placement. They help
ensure optimal implementation of common functions.

For HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.

Synopsys (FPGA Compiler, FPGA Express)

Exemplar (Spectrum)

Synplicity (Synplify)

For schematic design entry, the Xilinx FPGA Foundation
and Alliance development system provides interfaces to the
following schematic-capture design environments.

Mentor Graphics V8 (Design Architect, QuickSim II)

Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.

Virtex-E FPGAs are supported by a unified library of stan-
dard functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit accumu-
lators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.

The "soft macro" portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predetermined parti-
tioning and placement information that permits optimal

implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.

The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are auto-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
tions and the desired performance. Finally, the router inter-
connects the blocks.

The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floor planning.

The implementation software incorporates Timing Wizard

timing-driven placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.

Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tai-
lored to user-generated specifications. Specific timing infor-
mation for individual nets is unnecessary.

Design Verification

In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.

The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
TRCE

static timing analyzer.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

For in-circuit debugging, an optional download and read-
back cable is available. This cable connects the FPGA in the
target system to a PC or workstation. After downloading the
design into the FPGA, the designer can single-step the

logic, readback the contents of the flip-flops, and so observe
the internal logic state. Simple modifications can be down-
loaded into the system in a matter of minutes.

Configuration

Virtex-E devices are configured by loading configuration
data into the internal configuration memory. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.

Some of the pins used for configuration are dedicated pins,
while others can be re-used as general purpose inputs and
outputs once configuration is complete.

The following are dedicated pins:

Mode pins (M2, M1, M0)

Configuration clock pin (CCLK)

PROGRAM pin

DONE pin

Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or can be generated
externally and provided to the FPGA as an input. The
PROGRAM pin must be pulled High prior to reconfiguration.

Note that some configuration pins can act as outputs. For
correct operation, these pins require a V

CCO

of 3.3 V or

2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they

operate as LVCMOS. All affected pins fall in banks 2 or 3.
The configuration pins needed for SelectMap (CS, Write)
are located in bank 1.

Configuration Modes

Virtex-E supports the following four configuration modes.

Slave-serial mode

Master-serial mode

SelectMAP mode

Boundary-scan mode (JTAG)

The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in

Table 8

Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected. However, it is recom-
mended to drive the configuration mode pins externally.

Table 8: Configuration Codes

Configuration Mode

CCLK Direction

Data Width

Serial D

out

Configuration Pull-ups

Master-serial mode

Out

Yes

Boundary-scan mode

N/A

SelectMAP mode

Slave-serial mode

Yes

Master-serial mode

Out

Yes

Boundary-scan mode

N/A

Yes

SelectMAP mode

Yes

Slave-serial mode

Yes

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Table 9

lists the total number of bits required to configure

each device.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.

For more detailed information on serial PROMs, see the
PROM data sheet at

http://www.xilinx.com/bvdocs/publi-

cations/ds026.pdf

Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
data on the DOUT pin changes on the rising edge of CCLK.

The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.

Figure 13

shows a full master/slave system. A Virtex-E

device in slave-serial mode should be connected as shown
in the right-most device.

Slave-serial mode is selected by applying <111> or <011> to
the mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left uncon-
nected. However, it is recommended to drive the configura-
tion mode pins externally.

Figure 14

shows slave-serial

mode programming switching characteristics.

Table 10

provides more detail about the characteristics

shown in

Figure 14

. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

Table 9: Virtex-E Bitstream Lengths

Device

# of Configuration Bits

XCV50E

630,048

XCV100E

863,840

XCV200E

1,442,016

XCV300E

1, 875,648

XCV400E

2,693,440

XCV600E

3,961,632

XCV1000E

6,587,520

XCV1600E

8,308,992

XCV2000E

10,159,648

XCV2600E

12,922,336

XCV3200E

16,283,712

Table 10: Master/Slave Serial Mode Programming Switching

Description

Figure

References

Symbol

Values

Units

CCLK

DIN setup/hold, slave mode

1/2

DCC

CCD

5.0 / 0.0

ns, min

DIN setup/hold, master mode

1/2

DSCK

CKDS

5.0 / 0.0

ns, min

DOUT

CCO

12.0

ns, max

High time

CCH

5.0

ns, min

Low time

CCL

5.0

ns, min

Maximum Frequency

MHz, max

Frequency Tolerance, master mode with respect to nominal

+45% 30%

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.

The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK, which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.

The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.

On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.

In a full master/slave system (

Figure 13

), the left-most

device operates in master-serial mode. The remaining
devices operate in slave-serial mode. The SPROM RESET
pin is driven by INIT, and the CE input is driven by DONE.
There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.

The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in

Figure 15

Figure 13: Master/Slave Serial Mode Circuit Diagram

VIRTEX-E

MASTER

SERIAL

VIRTEX-E,

XC4000XL,

SLAVE

XC1701L

PROGRAM

M0 M1

DOUT

CCLK

CLK

3.3V

DATA

CEO

RESET/OE

DONE

DIN

INIT

DONE

PROGRAM

CCLK

DIN

DOUT

M0 M1

(Low Reset Option Used)

4.7 K

XCVE_ds_013

N/C

Figure 14: Slave-Serial Mode Programming Switching Characteristics

4 T

CCH

3 T

CCO

5 T

CCL

2 T

CCD

1 T

DCC

DIN

CCLK

DOUT

(Output)

X5379_a

Figure 15: Serial Configuration Flowchart

Apply Power

Set PROGRAM = High

Release INIT

If used to delay
configuration

Load a Configuration Bit

High

Low

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

ds009_15_111799

Configuration Completed

End of

Bitstream?

Yes

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

INIT?

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Figure 16

shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0).

Table 10

shows the timing infor-

mation for

Figure 16

At power-up, V

must rise from 1.0 V to V

Min in less

than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until V

is valid.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.

An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.

After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.

Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.

Multiple Virtex-E FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See

Table 11

for SelectMAP Write Timing

Characteristics.

Write

Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in

Figure 17

Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise, an abort is
initiated, as described below.

Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.

At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.

Repeat steps 2 and 3 until all the data has been sent.

De-assert CS and WRITE.

Figure 16: Master-Serial Mode Programming Switching Characteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

1 TDSCK

TCKDS

DS022_44_071201

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

A flowchart for the write operation is shown in

Figure 18

Note that if CCLK is slower than f

CCNH

, the FPGA never

asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.

Abort

During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.

To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in

Figure 19

Table 11: SelectMAP Write Timing Characteristics

Description

Symbol

Units

CCLK

0-7

Setup/Hold 1/2

SMDCC

SMCCD

5.0 / 1.7

ns, min

CS Setup/Hold

3/4

SMCSCC

SMCCCS

7.0 / 1.7

ns, min

WRITE Setup/Hold

5/6

SMCCW

SMWCC

7.0 / 1.7

ns, min

BUSY Propagation Delay

SMCKBY

12.0

ns, max

Maximum Frequency

MHz, max

Maximum Frequency with no handshake

CCNH

MHz, max

Figure 17: Write Operations

DS022_45_071702

CCLK

No Write

Write

No Write

Write

DATA[0:7]

WRITE

BUSY

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Boundary-Scan Mode

In the boundary-scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the

PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.

Figure 18: SelectMAP Flowchart for Write Operations

Apply Power

Release INIT

If used to delay
configuration

On first FPGA

PROGRAM

from Low

to High

Set WRITE = Low

Enter Data Source

Set CS = Low

On first FPGA

Set CS = High

Apply Configuration Byte

INIT?

High

Low

Yes

Busy?

Low

High

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

If no errors,

later FPGAs enter start-up phase

releasing DONE.

If no errors,

first FPGAs enter start-up phase

releasing DONE.

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

For any other FPGAs

ds003_17_090602

Repeat Sequence A

Configuration Completed

Sequence A

End of Data?

Yes

Figure 19: SelectMAP Write Abort Waveforms

CCLK

WRITE

Abort

DATA[0:7]

BUSY

DS022_46_071702

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.

The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).

Load the CFG_IN instruction into the boundary-scan
instruction register (IR).

Enter the Shift-DR (SDR) state.

Shift a configuration bitstream into TDI.

Return to Run-Test-Idle (RTI).

Load the JSTART instruction into IR.

Enter the SDR state.

Clock TCK through the startup sequence.

Return to RTI.

Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.

Configuration Sequence

The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.

Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.

The power-up timing of configuration signals is shown in

Figure 20

The corresponding timing characteristics are listed in

Table 12

Delaying Configuration

INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.

One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits

Figure 20: Power-Up Timing Configuration Signals

VALI

PROGRAM

Vcc

CCLK OUTPUT or INPUT

M0, M1, M2

(Required)

TPL

TICCK

ds022_020_071201

TPOR

INIT

Table 12: Power-up Timing Characteristics

Description

Symbol

Value

Units

Power-on Reset

POR

2.0

ms, max

Program Latency

100.0

s, max

CCLK (output) Delay

ICCK

0.5

s, min

4.0

s, max

Program Pulse Width

PROGRAM

300

ns, min

Notes:
1.

POR

delay is the initialization time required after V

CCINT

and

CCO

in Bank 2 reach the recommended operating voltage.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

the internal storage elements to begin changing state in
response to the logic and the user clock.

The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.

Readback

The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-

bility is used for real-time debugging. For more detailed
information, see application note XAPP138 "Virtex FPGA
Series Configuration and Readback".

Design Considerations

This section contains more detailed design information on
the following features.

Delay-Locked Loop . . . see

page 19

BlockRAM . . . see

page 24

SelectI/O . . . see

page 31

Using DLLs

The Virtex-E FPGA series provides up to eight fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.

Introduction

As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Virtex-E series
of devices resolve this potential problem by providing up to
eight fully digital dedicated on-chip DLL circuits, which pro-
vide zero propagation delay and low clock skew between
output clock signals distributed throughout the device.

Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network min-
imizes clock skews due to loading differences. By monitor-
ing a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the indi-
vidual clock loads within the device.

In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.

Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at 100
MHz. This technique can simplify board design because the
clock path on the board no longer distributes such a

high-speed signal. A multiplied clock also provides design-
ers the option of time-domain-multiplexing, using one circuit
twice per clock cycle, consuming less area than two copies
of the same circuit. Two DLLs in can be connected in series
to increase the effective clock multiplication factor to four.

The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.

In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.

By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.

Library DLL Symbols

Figure 21

shows the simplified Xilinx library DLL macro

symbol, BUFGDLL. This macro delivers a quick and effi-
cient way to provide a system clock with zero propagation
delay throughout the device.

Figure 22

and

Figure 23

show

the two library DLL primitives. These symbols provide
access to the complete set of DLL features when imple-
menting more complex applications.

Figure 21: Simplified DLL Macro Symbol BUFGDLL

0ns

ds022_25_121099

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

BUFGDLL Pin Descriptions

Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL applica-
tion as shown in

Figure 24

This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock divi-
sion features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL prim-
itives described in the following sections.

Source Clock Input -- I

The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUF-
GDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUF-

GDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.

Clock Output -- O

The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.

The output clock has a 50-50 duty cycle unless you deacti-
vate the duty cycle correction property.

CLKDLL Primitive Pin Descriptions

The library CLKDLL primitives provide access to the com-
plete set of DLL features needed when implementing more
complex applications with the DLL.

Source Clock Input -- CLKIN

The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.

Feedback Clock Input -- CLKFB

The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feed-
back clock input can also be provided through one of the fol-
lowing pins.

IBUFG - Global Clock Input Pad

IO_LVDS_DLL - the pin adjacent to IBUFG

If an IBUFG sources the CLKFB pin, the following special
rules apply.

An external input port must source the signal that drives
the IBUFG I pin.

The CLK2X output must feedback to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.

That signal must directly drive only OBUFs and nothing
else.

These rules enable the software determine which DLL clock
output sources the CLKFB pin.

Reset Input -- RST

When the reset pin RST activates the LOCKED signal deac-
tivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to

Figure 22: Standard DLL Symbol CLKDLL

Figure 23: High Frequency DLL Symbol CLKDLLHF

Figure 24: BUFGDLL Schematic

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_26_121099

CLKDLL

CLK0
CLK180

CLKDV

LOCKED

CLKIN
CLKFB

RST

ds022_027_121099

CLKDLLHF

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_28_121099

CLKDLL

BUFG

IBUFG

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
de-skew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.

2x Clock Output -- CLK2X

The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.

Clock Divide Output -- CLKDV

The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.

This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.

1x Clock Outputs -- CLK[0|90|180|270]

The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in

Table 13

The timing diagrams in

Figure 25

illustrate the DLL clock

output characteristics.

The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.

The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).

Locked Output -- LOCKED

To achieve lock, the DLL might need to sample several thou-
sand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.

To guarantee that the system clock is established prior to
the device "waking up," the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.

Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.

Table 13: Relationship of Phase-Shifted Output Clock
to Period Shift

Phase (degrees)

Period Shift (percent)

25%

180

50%

270

75%

Figure 25: DLL Output Characteristics

ds022_29_121099

CLKIN

CLK2X

CLK0

CLK90

CLK180

CLK270

CLKDV

CLKDV_DIVIDE=2

DUTY_CYCLE_CORRECTION=FALSE

CLK0

CLK90

CLK180

CLK270

DUTY_CYCLE_CORRECTION=TRUE

90 180 270

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

DLL Properties

Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).

Duty Cycle Correction Property

The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol.

Clock Divide Property

The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.

Startup Delay Property

This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device con-
figuration DONE signal waits until the DLL locks before
going to High.

Virtex-E DLL Location Constraints

As shown in

Figure 26

, there are four additional DLLs in the

Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identi-
fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.

The LOC property uses the following form:

LOC = DLL0P

Design Factors

Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.

Input Clock

The output clock signal of a DLL, essentially a delayed ver-
sion of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the qual-
ity of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.

In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscilla-
tors produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns -- orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.

Input Clock Changes

Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and out-
put clock.

It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100

µs to keep device cooling to a minimum. The clock

should be stopped during a Low phase, and when restored
the full High period should be seen. During this time,
LOCKED stays High and remains High when the clock is
restored.

When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.

In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control.

Output Clocks

As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bot-
tom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.

Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.

Figure 26: Virtex Series DLLs

x132_14_100799

B
R
A

DLL-3P

DLL-1P

DLL-3S

DLL-1S

DLL-2S

DLL-0S

DLL-2P

DLL-0P

Bottom Right
Half Edge

B
R
A

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Useful Application Examples

The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Standard Usage

The circuit shown in

Figure 27

resembles the BUFGDLL

macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.

Board Level De-skew of Multiple Non-Virtex-E
Devices

The circuit shown in

Figure 28

can be used to de-skew a

system clock between a Virtex-E chip and other non-Vir-
tex-E chips on the same board. This application is com-
monly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.

Board-level de-skew is not required for low-fanout clock net-
works. It is recommended for systems that have fanout lim-
itations on the clock network, or if the clock distribution chip
cannot handle the load.

The dll_mirror_1 files in the

xapp132.zip

file show the

VHDL and Verilog implementation of this circuit.

De-Skew of Clock and Its 2x Multiple

The circuit shown in

Figure 29

implements a 2x clock multi-

plier and also uses the CLK0 clock output with a zero ns
skew between registers on the same chip. Alternatively, a
clock divider circuit can be implemented using similar con-
nections.

Figure 27: Standard DLL Implementation

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_028_121099

CLKDLL

BUFG

IBUFG

IBUF

OBUF

Figure 28: DLL De-skew of Board Level Clock

Figure 29: DLL De-skew of Clock and 2x Multiple

ds022_029_121099

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL

OBUF

IBUFG

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL

BUFG

IBUFG

Non-Virtex-E Chip

Other Non_Virtex-E Chips

Virtex-E Device

CLK0
CLK90
CLK180
CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_030_121099

CLKDLL

BUFG

IBUFG

IBUF

OBUF

BUFG

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.

The dll_2x files in the

xapp132.zip

file show the VHDL and

Verilog implementation of this circuit.

Virtex-E 4x Clock

Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in

Figure 30

. Virtex-E devices, like the Virtex

devices, have four clock networks that are available for inter-
nal de-skewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal de-skewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.

The dll_4xe files in the xapp132.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Using Block SelectRAM+ Features

The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. The block SelectRAM+ memory offers

new capabilities allowing the FPGA designer to simplify
designs.

Operating Modes

VIrtex-E block SelectRAM+ memory supports two operating
modes:

Read Through

Write Back

Read Through (one clock edge)

The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on whether a faster clock-to-out versus
set-up time is desired. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.

Write Back (one clock edge)

The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.

Block SelectRAM+ Characteristics

All inputs are registered with the port clock and have a
set-up to clock timing specification.

All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.

The block SelectRAMs are true SRAM memories and
do not have a combinatorial path from the address to
the output. The LUT SelectRAM+ cells in the CLBs are
still available with this function.

The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.

A write operation requires only one clock edge.

A read operation requires only one clock edge.

The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port does
not change until the port executes another read or write
operation.

Library Primitives

Figure 31

and

Figure 32

show the two generic library block

SelectRAM+ primitives.

Table 14

describes all of the avail-

able primitives for synthesis and simulation.

Figure 30: DLL Generation of 4x Clock in Virtex-E

Devices

ds022_031_041901

RST

CLKFB

CLKIN

CLKDLL-S

LOCKED

CLKDV

INV

BUFG

OBUF

IBUFG

CLK2X

CLK0

CLK90

CLK180
CLK270

RST

CLKFB

CLKIN

CLKDLL-P

LOCKED

CLKDV

CLK2X

CLK0

CLK90

CLK180
CLK270

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Port Signals

Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.

Table 15

describes the depth and width aspect ratios for the

block SelectRAM+ memory.

Clock--CLK[A|B]

Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time refer-
enced to the CLK pin.

Enable--EN[A|B]

The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the mem-
ory cells.

Write Enable--WE[A|B]

Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the con-
tents of the memory cells referenced by the address bus
reflect on the data out bus.

Reset--RST[A|B]

The reset pin forces the data output bus latches to zero syn-
chronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.

Address Bus--ADDR[A|B]<#:0>

The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in

Table 15

Data In Bus--DI[A|B]<#:0>

The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in

Table 15

Figure 31: Dual-Port Block SelectRAM+ Memory

Figure 32: Single-Port Block SelectRAM+ Memory

Table 14: Available Library Primitives

Primitive

Port A Width

Port B Width

RAMB4_S1

RAMB4_S1_S1

RAMB4_S1_S2

RAMB4_S1_S4

RAMB4_S1_S8

RAMB4_S1_S16

N/A

RAMB4_S2

RAMB4_S2_S2

RAMB4_S2_S4

RAMB4_S2_S8

RAMB4_S2_S16

N/A

RAMB4_S4

RAMB4_S4_S4

RAMB4_S4_S8

RAMB4_S4_S16

N/A

RAMB4_S8

RAMB4_S8_S8

RAMB4_S8_S16

N/A

RAMB4_S16

RAMB4_S16_S16

N/A

WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]

WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_032_121399

ds022_033_121399

DO[#:0]

RST

CLK

ADDR[#:0]

DI[#:0]

RAMB4_S#

Table 15: Block SelectRAM+ Port Aspect Ratios

Width

Depth

ADDR Bus

Data Bus

4096

ADDR<11:0>

DATA<0>

2048

ADDR<10:0>

DATA<1:0>

1024

ADDR<9:0>

DATA<3:0>

512

ADDR<8:0>

DATA<7:0>

256

ADDR<7:0>

DATA<15:0>

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Data Output Bus--DO[A|B]<#:0>

The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in

Table 15

Inverting Control Pins

The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.

Address Mapping

Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port.

The physical RAM location addressed for a particular width
are described in the following formula (of interest only when
the two ports use different aspect ratios).

Start = ((ADDR

port

+1) * Width

port

) 1

End = ADDR

port

* Width

port

Table 16

shows low order address mapping for each port

width.

Creating Larger RAM Structures

The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing delays.
This achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.

Location Constraints

Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC proper-
ties to transfer easily from array to array.

The LOC properties use the following form.

LOC = RAMB4_R#C#

RAMB4_R0C0 is the upper left RAMB4 location on the
device.

Conflict Resolution

The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and mem-
ory cell write conflict resolution.

If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.

If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-

The write succeeds

The data out on the writing port accurately reflects
the data written.

The data out on the reading port is invalid.

Conflicts do not cause any physical damage.

Single Port Timing

Figure 33

shows a timing diagram for a single port of a block

SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.

At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.

At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors the
DI bus. The DI bus is written to the memory location 0x0F.

At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.

At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low

Table 16: Port Address Mapping

Port

Width

Port

Addresses

4095...

1
5

1
4

1
3

1
2

1
1

1
0

0
9

0
8

0
7

0
6

0
5

0
4

0
3

0
2

0
1

0
0

2047...

1023...

511...

255...

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

indicating that the block SelectRAM+ memory is now dis-
abled. The DO bus retains the last value.

Dual Port Timing

Figure 34

shows a timing diagram for a true dual-port

read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter T

BCCS

, (clock-to-clock set-up) is shown on this

diagram. The parameter, T

BCCS

is violated once in the dia-

gram. All other timing parameters are identical to the single
port version shown in

Figure 33

BCCS

is only of importance when the address of both ports

are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,

the contents of the memory are correct, but the read port
has invalid data.

At the first rising edge of the CLKA, memory location 0x00 is
to be written with the value 0xAAAA and is mirrored on the
DOA bus. The last operation of Port B was a read to the
same memory location 0x00. The DOB bus of Port B does
not change with the new value on Port A, and retains the
last read value. A short time later, Port B executes another
read to memory location 0x00, and the DOB bus now
reflects the new memory value written by Port A.

At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the T

BCCS

parameter and

the DOB reflects the new memory values written by Port A.

Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory

ds022_0343_121399

CLK

BPWH

BACK

ADDR

DDDD

MEM (00)

CCCC

MEM (7E)

CCCC

BBBB

2222

DIN

DOUT

RST

DISABLED

READ

WRITE

READ

DISABLED

BDCK

BECK

BWCK

BCKO

BPWL

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

At the third rising edge of CLKA, the T

BCCS

parameter is

violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x0F is invalid.

At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.

At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the T

BCCS

parameter to the

previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.

Initialization

The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in

Table 17

. Any initial-

ization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.

Initialization in VHDL and Synopsys

The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not

presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.

Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory

ds022_035_121399

CLK_A

PORT A

PORT B

ADDR_A

AAAA

9999

AAAA

0000

1111

2222

AAAA

9999

AAAA

UNKNOWN

EN_A

WE_A

DI_A

DO_A

1111

2222

FFFF

BBBB

1111

AAAA

MEM (00)

9999

2222

FFFF

BBBB

UNKNOWN

CLK_B

ADDR_B

EN_B

WE_B

DI_B

DO_B

BCCS

VIOLATION

BCCS

Table 17: RAM Initialization Properties

Property

Memory Cells

INIT_00

255 to 0

INIT_01

511 to 256

INIT_02

767 to 512

INIT_03

1023 to 768

INIT_04

1279 to 1024

INIT_05

1535 to 1280

INIT_06

1791 to 2047

INIT_07

2047 to 1792

INIT_08

2303 to 2048

INIT_09

2559 to 2304

INIT_0a

2815 to 2560

INIT_0b

3071 to 2816

INIT_0c

3327 to 3072

INIT_0d

3583 to 3328

INIT_0e

3839 to 3584

INIT_0f

4095 to 3840

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Initialization in Verilog and Synopsys

The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a def-
param to pass the initialization. The Synopsys FPGA com-
piler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.

Design Examples

Creating a 32-bit Single-Port RAM

The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown in

Figure 35

Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (V

), and the LSB of the

address bus of Port B to 0 (GND), allows a 32-bit wide sin-
gle port RAM to be created.

Creating Two Single-Port RAMs

The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into
two single port memories of 2K bits each as shown in

Figure 36

In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
Port A to 1 (V

) for the upper 2K bits and the MSB of Port

B to 0 (GND) for the lower 2K bits.

Block Memory Generation

The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.

Figure 35: Single Port 128 x 32 RAM

WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]

WEA
ENA
RSTA
CLKA
ADDRA[7:0]
DIA[15:0]

ADDR[6:0], V

CLK

RST

CLK

RST

DI[31:16]

ADDR[6:0], GND

DI[15:0]

DOA[15:0]

DO[31:16]

DO[15:0]

DOB[15:0]

RAMB4_S16_S16

ds022_036_121399

Figure 36: 512 x 4 RAM and 128 x 16 RAM

WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]

WEA
ENA
RSTA
CLKA
ADDRA[9:0]
DIA[3:0]

, ADDR1[8:0]

DI1[3:0]

WE1

EN1

RST1
CLK1

WE2

EN2

RST2
CLK2

GND, ADDR2[6:0]

DI2[15:0]

DOA[3:0]

DO1[3:0]

DO2[15:0]

DOB[15:0]

RAMB4_S4_S16

ds022_037_121399

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

VHDL Initialization Example

library IEEE;

use IEEE.std_logic_1164.all;

entity MYMEM is

port (CLK, WE:in std_logic;

ADDR: in std_logic_vector(8 downto 0);

DIN: in std_logic_vector(7 downto 0);

DOUT: out std_logic_vector(7 downto 0));

end MYMEM;

architecture BEHAVE of MYMEM is

signal logic0, logic1: std_logic;

component RAMB4_S8

--synopsys translate_off

generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,

INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255

downto 0)

:= X"0000000000000000000000000000000000000000000000000000000000000000");

--synopsys translate_on

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

--synopsys dc_script_begin

--set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

--set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

--synopsys dc_script_end

begin

logic0 <='0';

logic1 <='1';

ram0: RAMB4_S8

--synopsys translate_off

generic map (

INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",

INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")

--synopsys translate_on

port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);

end BEHAVE;

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Verilog Initialization Example

module MYMEM (CLK, WE, ADDR, DIN, DOUT);

input CLK, WE;

input [8:0] ADDR;

input [7:0] DIN;

output [7:0] DOUT;

wire logic0, logic1;

//synopsys dc_script_begin

//set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

//set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

//synopsys dc_script_end

assign logic0 = 1'b0;

assign logic1 = 1'b1;

RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),

.DO(DOUT));

//synopsys translate_off

defparam ram0.INIT_00 =

256h'0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;

defparam ram0.INIT_01 =

256h'FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;

//synopsys translate_on

endmodule

Using SelectI/O

The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/OTM to pro-
vide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including pro-
grammable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify sys-
tem level design.

Introduction

As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high perfor-
mance I/O becomes more important.

While chip-to-chip delays have an increasingly substantial
impact on overall system speed, the task of achieving the
desired system performance becomes more difficult with
the proliferation of low-voltage I/O standards. SelectI/O, the
revolutionary input/output resources of Virtex-E devices,
resolve this potential problem by providing a highly config-
urable, high-performance alternative to the I/O resources of
more conventional programmable devices. Virtex-E SelectI/O
features combine the flexibility and time-to-market advan-
tages of programmable logic with the high performance pre-
viously available only with ASICs and custom ICs.

Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the sup-
port of a wide variety of applications, from general purpose
standard applications to high-speed low-voltage memory
busses.

SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL out-
put buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak "keeper" circuit ideal for
use in external bussing applications.

Each Input/Output Block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.

The input buffer has an optional delay element used to guar-
antee a zero hold time requirement for input signals regis-
tered within the IOB.

The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (V

REF

) and output

source voltage (V

CCO

), along with a convenient banking

system that simplifies board design.

By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, sys-
tem-level design and board design can be greatly simplified
and improved.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Fundamentals

Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.

The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards

The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in

Table 18

, each buffer type can

support a variety of voltage requirements.

Overview of Supported I/O Standards

This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.

While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:

http://www.jedec.org

LVTTL -- Low-Voltage TTL

The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3V output source voltage (V

CCO

), but

does not require the use of a reference voltage (V

REF

) or a

termination voltage (V

LVCMOS2 -- Low-Voltage CMOS for 2.5 Volts

The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard
(JESD 8.-5) used for general purpose 2.5V applications.
This standard requires a 2.5V output source voltage
(V

CCO

), but does not require the use of a reference voltage

REF

) or a board termination voltage (V

LVCMOS18

-- 1.8 V Low Voltage CMOS

This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (V

REF

) or a board termination voltage

) is not required.

PCI -- Peripheral Component Interface

The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (V

REF

) or a board termination voltage (V

), how-

ever, it does require a 3.3V output source voltage (V

CCO

GTL -- Gunning Transceiver Logic Terminated

The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation for this stan-
dard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.

GTL+ -- Gunning Transceiver Logic Plus

The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.

HSTL -- High-Speed Transceiver Logic

The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This

Table 18: Virtex-E Supported I/O Standards

I/O Standard

Output

CCO

Input
V

CCO

Input

REF

Board

Termination

Voltage

)

LVTTL

3.3

N/A

LVCMOS2

2.5

N/A

LVCMOS18

1.8

N/A

SSTL3 I & II

3.3

N/A

1.50

SSTL2 I & II

2.5

N/A

1.25

GTL

N/A

0.80

1.20

GTL+

N/A

1.0

1.50

HSTL I

1.5

N/A

0.75

HSTL III & IV

1.5

N/A

0.90

1.50

CTT

3.3

N/A

1.50

AGP-2X

3.3

N/A

1.32

N/A

PCI33_3 3.3

3.3

N/A

PCI66_3 3.3

3.3

N/A

BLVDS & LVDS

2.5

N/A

LVPECL

3.3

N/A

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.

SSTL3 -- Stub Series Terminated Logic for 3.3V

The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.

SSTL2 -- Stub Series Terminated Logic for 2.5V

The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. SelectI/O devices support both classes for
the SSTL2 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.

CTT -- Center Tap Terminated

The Center Tap Terminated, or CTT standard is a 3.3V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.

AGP-2X -- Advanced Graphics Port

The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.

LVDS

-- Low Voltage Differential Signal

LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350mV. The use
of a reference voltage (V

REF

) or a board termination voltage

) is not required. LVDS requires the use of two pins per

input or output. LVDS requires external resistor termination.

BLVDS

-- Bus LVDS

This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termi-
nation is different than the one for standard LVDS.

LVPECL

-- Low Voltage Positive Emitter Coupled

Logic

LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
The use of a reference voltage (V

REF

) or a board termina-

tion voltage (V

) is not required. The LVPECL standard

requires external resistor termination.

Library Symbols

The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O fea-
tures. Most of these symbols represent variations of the five
generic SelectI/O symbols.

IBUF (input buffer)

IBUFG (global clock input buffer)

OBUF (output buffer)

OBUFT (3-state output buffer)

IOBUF (input/output buffer)

IBUF

Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in

Figure 37

. The extension

to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.

The following list details the variations of the IBUF symbol:

IBUF

IBUF_LVCMOS2

IBUF_PCI33_3

IBUF_PCI66_3

IBUF_GTL

IBUF_GTLP

IBUF_HSTL_I

IBUF_HSTL_III

IBUF_HSTL_IV

IBUF_SSTL3_I

IBUF_SSTL3_II

IBUF_SSTL2_I

IBUF_SSTL2_II

IBUF_CTT

IBUF_AGP

IBUF_LVCMOS18

IBUF_LVDS

IBUF_LVPECL

When the IBUF symbol supports an I/O standard that
requires a V

REF

, the IBUF automatically configures as a dif-

ferential amplifier input buffer. The V

REF

voltage must be

supplied on the V

REF

pins. In the case of LVDS, LVPECL,

and BLVDS, V

REF

is not required.

Figure 37: Input Buffer (IBUF) Symbols

IBUF

x133_01_111699

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

The voltage reference signal is "banked" within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V

REF

banks internally. See

Figure 38

for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a V

REF

input. After placing a differential

amplifier input signal within a given V

REF

bank, the same

external source must drive all I/O pins configured as a V

REF

input.

IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below.

Table 19

summarizes the

Virtex-E input standards compatibility requirements.

An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.

When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.

IBUFG

Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG should only drive a CLKDLL,

CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG
symbol appears in

Figure 39

The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.

The following list details variations of the IBUFG symbol.

IBUFG

IBUFG_LVCMOS2

IBUFG_PCI33_3

IBUFG_PCI66_3

IBUFG_GTL

IBUFG_GTLP

IBUFG_HSTL_I

IBUFG_HSTL_III

IBUFG_HSTL_IV

IBUFG_SSTL3_I

IBUFG_SSTL3_II

IBUFG_SSTL2_I

IBUFG_SSTL2_II

IBUFG_CTT

IBUFG_AGP

IBUFG_LVCMOS18

IBUFG_LVDS

IBUFG_LVPECL

When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automati-
cally configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
require an external reference voltage input V

REF

The voltage reference signal is "banked" within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V

REF

banks internally. See

Figure 38

for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a V

REF

input. After placing a differential

amplifier input signal within a given V

REF

bank, the same

external source must drive all I/O pins configured as a V

REF

input.

IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.

As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol

Table 19: Xilinx Input Standards Compatibility
Requirements

Rule 1

Standards with the same input V

CCO

, output V

CCO

and V

REF

can be placed within the same bank.

Figure 38: Virtex-E I/O Banks

ds022_42_012100

Bank 0

GCLK3

GCLK2

GCLK1

GCLK0

Bank 1

Bank 5

Bank 4

Virtex-E

Device

Bank 7

Bank 6

Bank 2

Bank 3

Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)

Symbol

IBUFG

x133_03_111699

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.

Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.

OBUF

An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in

Figure 40

The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.

The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.

LVTTL output buffers have selectable drive strengths.

The format for LVTTL OBUF symbol names is as follows:

OBUF_<slew_rate>_<drive_strength>

where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).

The following list details variations of the OBUF symbol.

OBUF

OBUF_S_2

OBUF_S_4

OBUF_S_6

OBUF_S_8

OBUF_S_12

OBUF_S_16

OBUF_S_24

OBUF_F_2

OBUF_F_4

OBUF_F_6

OBUF_F_8

OBUF_F_12

OBUF_F_16

OBUF_F_24

OBUF_LVCMOS2

OBUF_PCI33_3

OBUF_PCI66_3

OBUF_GTL

OBUF_GTLP

OBUF_HSTL_I

OBUF_HSTL_III

OBUF_HSTL_IV

OBUF_SSTL3_I

OBUF_SSTL3_II

OBUF_SSTL2_I

OBUF_SSTL2_II

OBUF_CTT

OBUF_AGP

OBUF_LVCMOS18

OBUF_LVDS

OBUF_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four V

CCO

banks.

OBUF placement restrictions require that within a given
V

CCO

bank each OBUF share the same output source drive

voltage. Input buffers of any type and output buffers that do
not require V

CCO

can be placed within any V

CCO

bank.

Table 20

summarizes the Virtex-E output compatibility

requirements. The LOC property can specify a location for
the OBUF.

OBUFT

The generic 3-state output buffer OBUFT (see

Figure 41

)

typically implements 3-state outputs or bidirectional I/O.

The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.

The LVTTL OBUFT additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.

Figure 40: Virtex-E Output Buffer (OBUF) Symbol

OBUF

x133_04_111699

Table 20: Output Standards Compatibility
Requirements

Rule 1

Only outputs with standards that share compatible
V

CCO

can be used within the same bank.

Rule 2

There are no placement restrictions for outputs
with standards that do not require a V

CCO

Compatible Standards

3.3

LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3

2.5

SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+

1.5

HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

LVTTL 3-state output buffers have selectable drive
strengths.

The format for LVTTL OBUFT symbol names is as follows:

OBUFT_<slew_rate>_<drive_strength>

where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).

The following list details variations of the OBUFT symbol.

OBUFT

OBUFT_S_2

OBUFT_S_4

OBUFT_S_6

OBUFT_S_8

OBUFT_S_12

OBUFT_S_16

OBUFT_S_24

OBUFT_F_2

OBUFT_F_4

OBUFT_F_6

OBUFT_F_8

OBUFT_F_12

OBUFT_F_16

OBUFT_F_24

OBUFT_LVCMOS2

OBUFT_PCI33_3

OBUFT_PCI66_3

OBUFT_GTL

OBUFT_GTLP

OBUFT_HSTL_I

OBUFT_HSTL_III

OBUFT_HSTL_IV

OBUFT_SSTL3_I

OBUFT_SSTL3_II

OBUFT_SSTL2_I

OBUFT_SSTL2_II

OBUFT_CTT

OBUFT_AGP

OBUFT_LVCMOS18

OBUFT_LVDS

OBUFT_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V

CCO

banks.

The SelectI/O OBUFT placement restrictions require that
within a given V

CCO

bank each OBUFT share the same out-

put source drive voltage. Input buffers of any type and out-
put buffers that do not require V

CCO

can be placed within

the same V

CCO

bank.

The LOC property can specify a location for the OBUFT.

3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak "keeper" circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PUL-
LUP, PULLDOWN, or KEEPER).

The weak "keeper" circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a V

REF

have automatic place-

ment of a V

REF

in the bank with an OBUFT configured with

a weak "keeper" circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak "keeper" typically implement a bidirectional I/O.
In this case the IBUF (and the corresponding V

REF

) are

explicitly placed.

The LOC property can specify a location for the OBUFT.

IOBUF

Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in

Figure 42

The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.

The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.

LVTTL bidirectional buffers have selectable output drive
strengths.

The format for LVTTL IOBUF symbol names is as follows:

IOBUF_<slew_rate>_<drive_strength>

where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).

Figure 41: 3-State Output Buffer Symbol (OBUFT)

OBUFT

x133_05_111699

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

The following list details variations of the IOBUF symbol.

IOBUF

IOBUF_S_2

IOBUF_S_4

IOBUF_S_6

IOBUF_S_8

IOBUF_S_12

IOBUF_S_16

IOBUF_S_24

IOBUF_F_2

IOBUF_F_4

IOBUF_F_6

IOBUF_F_8

IOBUF_F_12

IOBUF_F_16

IOBUF_F_24

IOBUF_LVCMOS2

IOBUF_PCI33_3

IOBUF_PCI66_3

IOBUF_GTL

IOBUF_GTLP

IOBUF_HSTL_I

IOBUF_HSTL_III

IOBUF_HSTL_IV

IOBUF_SSTL3_I

IOBUF_SSTL3_II

IOBUF_SSTL2_I

IOBUF_SSTL2_II

IOBUF_CTT

IOBUF_AGP

IOBUF_LVCMOS18

IOBUF_LVDS

IOBUF_LVPECL

When the IOBUF symbol used supports an I/O standard
that requires a differential amplifier input, the IOBUF auto-
matically configures with a differential amplifier input buffer.

The low-voltage I/O standards with a differential amplifier
input require an external reference voltage input V

REF

The voltage reference signal is "banked" within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V

REF

banks internally. See

Figure 38,

page 34

for a representation of the Virtex-E I/O banks.

Within each bank approximately one of every six I/O pins is
automatically configured as a V

REF

input. After placing a dif-

ferential amplifier input signal within a given V

REF

bank, the

same external source must drive all I/O pins configured as a
V

REF

input.

IOBUF placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard.

The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V

CCO

banks.

Additional restrictions on the Virtex-E SelectI/O IOBUF
placement require that within a given V

CCO

bank each

IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require V

CCO

can be placed within the same V

CCO

bank.

The LOC property can specify a location for the IOBUF.

An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.

In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, acti-
vate the delay element with the DELAY=TRUE property.

SelectI/O Properties

Access to some of the SelectI/O features (for example, loca-
tion constraints, input delay, output drive strength, and slew
rate) is available through properties associated with these
features.

Input Delay Properties

An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to over-
ride this default.

In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to pro-
vide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.

Figure 42: Input/Output Buffer Symbol (IOBUF)

IOBUF

x133_06_111699

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

IOB Flip-Flop/Latch Property

The Virtex-E series I/O Block (IOB) includes an optional
register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advan-
tage of these registers when the following option for the Map
program is specified.

map pr b <filename>

Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.

Location Constraints

Specify the location of each SelectI/O symbol with the loca-
tion constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.

The LOC properties use the following form:

LOC=A42

LOC=P37

Output Slew Rate Property

As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buff-
ers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively pro-
gramed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.

SLEW=SLOW

SLEW=FAST

Output Drive Strength Property

The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.

DRIVE=2

DRIVE=4

DRIVE=6

DRIVE=8

DRIVE=12 (Default)

DRIVE=16

DRIVE=24

Design Considerations

Reference Voltage (V

REF

) Pins

Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (V

REF

). Provide the

REF

as an external signal to the device.

The voltage reference signal is "banked" within the device on
a half-edge basis such that for all packages there are eight
independent V

REF

banks internally. See

Figure 38

for a rep-

resentation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically con-
figured as a V

REF

input. After placing a differential amplifier

input signal within a given V

REF

bank, the same external

source must drive all I/O pins configured as a V

REF

input.

Within each V

REF

bank, any input buffers that require a

REF

signal must be of the same type. Output buffers of any

type and input buffers can be placed without requiring a ref-
erence voltage within the same V

REF

bank.

Output Drive Source Voltage (V

CCO

) Pins

Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
voltage (V

CCO

). As a result each device can often have to

support multiple output drive source voltages.

The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V

CCO

banks.

Output buffers within a given V

CCO

bank must share the

same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
V

CCO

voltage for Input V

CCO

voltage.

Transmission Line Effects

The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.

Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.

Termination Techniques

A variety of termination techniques reduce the impact of
transmission line effects.

The following are output termination techniques:

None

Series

Parallel (Shunt)

Series and Parallel (Series-Shunt)

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Input termination techniques include the following.

None

Parallel (Shunt)

These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in

Figure 43

Simultaneous Switching Guidelines

Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.

Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.

Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.

Table 21

provides guidelines for the maximum number of

simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce. See

Table 22

for the number of effective output power/ground pairs

for each Virtex-E device and package combination.

Figure 43: Overview of Standard Input and Output

Termination Methods

x133_07_111699

Unterminated

Double Parallel Terminated

Series-Parallel Terminated Output

Driving a Parallel Terminated Input

REF

Series Terminated Output Driving

a Parallel Terminated Input

REF

Unterminated Output Driving

a Parallel Terminated Input

REF

Series Terminated Output

REF

Z=50

Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair

Standard

Package

BGA, CS, FGA

PQ, TQ

LVTTL Slow Slew Rate, 2 mA drive

LVTTL Slow Slew Rate, 4 mA drive

LVTTL Slow Slew Rate, 6 mA drive

LVTTL Slow Slew Rate, 8 mA drive

LVTTL Slow Slew Rate, 12 mA drive

LVTTL Slow Slew Rate, 16 mA drive

LVTTL Slow Slew Rate, 24 mA drive

LVTTL Fast Slew Rate, 2 mA drive

LVTTL Fast Slew Rate, 4 mA drive

LVTTL Fast Slew Rate, 6 mA drive

LVTTL Fast Slew Rate, 8 mA drive

LVTTL Fast Slew Rate, 12 mA drive

LVTTL Fast Slew Rate, 16 mA drive

LVTTL Fast Slew Rate, 24 mA drive

LVCMOS

PCI

GTL

GTL+

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

HSTL Class I

HSTL Class III

HSTL Class IV

SSTL2 Class I

SSTL2 Class II

SSTL3 Class I

SSTL3 Class II

CTT

AGP

Note: This analysis assumes a 35 pF load for each output.

Table 22: Virtex-E Equivalent Power/Ground Pairs

Pkg/Part

XCV100E

XCV200E

XCV300E

XCV400E

XCV600E

XCV1000E

XCV1600E

XCV2000E

CS144

PQ240

HQ240

BG352

BG432

BG560

FG256

(1)

FG456

FG676

FG680

(2)

FG860

FG900

FG1156

104

120

Notes:
1.

Virtex-E devices in FG256 packages have more V

CCO

than Virtex series devices.

FG680 numbers are preliminary.

Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued)

Standard

Package

BGA, CS, FGA

PQ, TQ

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Application Examples

Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.

This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.

Termination Examples

Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.

The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.

GTL

A sample circuit illustrating a valid termination technique for
GTL is shown in

Figure 44

Table 23

lists DC voltage specifications.

GTL+

A sample circuit illustrating a valid termination technique for
GTL+ appears in

Figure 45

. DC voltage specifications

appear in

Table 24

Figure 44: Terminated GTL

Table 23: GTL Voltage Specifications

Parameter

Min

Typ

Max

CCO

N/A

REF

= N

× V

0.74

0.8

0.86

1.14

1.2

1.26

= V

REF

+ 0.05

0.79

0.85

= V

REF

0.05

0.75

0.81

0.2

0.4

at V

(mA)

at V

(mA) at 0.4V

at V

(mA) at 0.2V

Notes:
1.

N must be greater than or equal to 0.653 and less than or
equal to 0.68.

REF

= 0.8V

= 1.2V

CCO

= N/A

Z = 50

GTL

x133_08_111699

= 1.2V

Figure 45: Terminated GTL+

Table 24: GTL+ Voltage Specifications

Parameter

Min

Typ

Max

CCO

REF

= N

× V

0.88

1.0

1.12

1.35

1.5

1.65

= V

REF

+ 0.1

0.98

1.1

= V

REF

0.1

0.9

1.02

0.3

0.45

0.6

at V

(mA)

at V

(mA) at 0.6V

at V

(mA) at 0.3V

Notes:
1.

N must be greater than or equal to 0.653 and less than or
equal to 0.68.

REF

= 1.0V

= 1.5V

CCO

= N/A

Z = 50

GTL+

x133_09_012400

= 1.5V

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

HSTL

A sample circuit illustrating a valid termination technique for
HSTL_I appears in

Figure 46

. A sample circuit illustrating a

valid termination technique for HSTL_III appears in

Figure 47

A sample circuit illustrating a valid termination technique for
HSTL_IV appears in

Figure 48

Table 25: HSTL Class I Voltage Specification

Parameter

Min

Typ

Max

CCO

1.40

1.50

1.60

REF

0.68

0.75

0.90

CCO

× 0.5

REF

+ 0.1

REF

0.1

CCO

0.4

at V

(mA)

-8

at V

(mA)

Figure 46: Terminated HSTL Class I

Table 26: HSTL Class III Voltage Specification

Parameter

Min

Typ

Max

CCO

1.40

1.50

1.60

REF

(1)

0.90

CCO

REF

+ 0.1

REF

0.1

CCO

0.4

at V

(mA)

-8

at V

(mA)

Note: Per EIA/JESD8-6, "The value of V

REF

is to be selected

by the user to provide optimum noise margin in the use
conditions specified by the user."

REF

= 0.75V

CCO

= 1.5V

Z = 50

HSTL Class I

x133_10_111699

Figure 47: Terminated HSTL Class III

Table 27: HSTL Class IV Voltage Specification

Parameter

Min

Typ

Max

CCO

1.40

1.50

1.60

REF

0.90

CCO

REF

+ 0.1

REF

0.1

CCO

0.4

at V

(mA)

-8

at V

(mA)

Note: Per EIA/JESD8-6, "The value of V

REF

is to be selected

by the user to provide optimum noise margin in the use
conditions specified by the user.

Figure 48: Terminated HSTL Class IV

REF

= 0.9V

= 1.5V

CCO

= 1.5V

Z = 50

HSTL Class III

x133_11_111699

Z = 50

HSTL Class IV

x133_12_111699

REF

= 0.9V

= 1.5V

CCO

= 1.5V

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

SSTL3_I

A sample circuit illustrating a valid termination technique for
SSTL3_I appears in

Figure 49

. DC voltage specifications

appear in

Table 28

SSTL3_II

A sample circuit illustrating a valid termination technique for
SSTL3_II appears in

Figure 50

. DC voltage specifications

appear in

Table 29

SSTL2_I

A sample circuit illustrating a valid termination technique for
SSTL2_I appears in

Figure 51

. DC voltage specifications

appear in

Table 30

Figure 49: Terminated SSTL3 Class I

Table 28: SSTL3_I Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

= 0.45

× V

CCO

1.3

1.5

1.7

= V

REF

1.3

1.5

1.7

= V

REF

+ 0.2

1.5

1.7

3.9

(1)

= V

REF

0.2

-0.3

(2)

1.3

1.5

= V

REF

+ 0.6

1.9

= V

REF

0.6

1.1

at V

(mA)

-8

at V

(mA)

Notes:
1.

maximum is V

CCO

+ 0.3

minimum does not conform to the formula

Figure 50: Terminated SSTL3 Class II

Z = 50

SSTL3 Class I

x133_13_111699

REF

= 1.5V

CCO

= 3.3V

Z = 50

SSTL3 Class II

x133_14_111699

REF

= 1.5V

CCO

= 3.3V

Table 29: SSTL3_II Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

= 0.45

× V

CCO

1.3

1.5

1.7

= V

REF

1.3

1.5

1.7

= V

REF

+ 0.2

1.5

1.7

3.9

(1)

= V

REF

0.2

-0.3

(2)

1.3

1.5

= V

REF

+ 0.8

2.1

= V

REF

0.8

0.9

at V

(mA)

-16

at V

(mA)

Notes:
1.

maximum is V

CCO

+ 0.3

minimum does not conform to the formula

Figure 51: Terminated SSTL2 Class I

Table 30: SSTL2_I Voltage Specifications

Parameter

Min

Typ

Max

CCO

2.3

2.5

2.7

REF

= 0.5

× V

CCO

1.15

1.25

1.35

= V

REF

+ N

(1)

1.11

1.25

1.39

= V

REF

+ 0.18

1.33

1.43

3.0

(2)

= V

REF

0.18

-0.3

(3)

1.07

1.17

= V

REF

+ 0.61

1.76

= V

REF

0.61

0.74

at V

(mA)

-7.6

at V

(mA)

7.6

Notes:
1.

N must be greater than or equal to -0.04 and less than or
equal to 0.04.

maximum is V

CCO

+ 0.3.

minimum does not conform to the formula.

Z = 50

SSTL2 Class I

xap133_15_011000

REF

= 1.25V

CCO

= 2.5V

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

SSTL2_II

A sample circuit illustrating a valid termination technique for
SSTL2_II appears in

Figure 52

. DC voltage specifications

appear in

Table 31

CTT

A sample circuit illustrating a valid termination technique for
CTT appear in

Figure 53

. DC voltage specifications appear

Table 32

PCI33_3 & PCI66_3

PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in

Table 33

Figure 52: Terminated SSTL2 Class II

Table 31: SSTL2_II Voltage Specifications

Parameter

Min

Typ

Max

CCO

2.3

2.5

2.7

REF

= 0.5

× V

CCO

1.15

1.25

1.35

= V

REF

+ N

(1)

1.11

1.25

1.39

= V

REF

+ 0.18

1.33

1.43

3.0

(2)

= V

REF

0.18

-0.3

(3)

1.07

1.17

= V

REF

+ 0.8

1.95

= V

REF

0.8

0.55

at V

(mA)

-15.2

at V

(mA)

15.2

Notes:
1.

N must be greater than or equal to -0.04 and less than or
equal to 0.04.

maximum is V

CCO

+ 0.3.

minimum does not conform to the formula.

Figure 53: Terminated CTT

Z = 50

SSTL2 Class II

x133_16_111699

REF

= 1.25V

CCO

= 2.5V

REF

= 1.5V

CCO

= 3.3V

Z = 50

CTT

x133_17_111699

Table 32: CTT Voltage Specifications

Parameter

Min

Typ

Max

CCO

2.05

(1)

3.3

3.6

REF

1.35

1.5

1.65

1.35

1.5

1.65

= V

REF

+ 0.2

1.55

1.7

= V

REF

0.2

1.3

1.45

= V

REF

+ 0.4

1.75

1.9

= V

REF

0.4

1.1

1.25

at V

(mA)

-8

at V

(mA)

Notes:
1.

Timing delays are calculated based on V

CCO

min of 3.0V.

Table 33: PCI33_3 and PCI66_3 Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

= 0.5

× V

CCO

1.5

1.65

CCO

+ 0.5

= 0.3

× V

CCO

-0.5

0.99

1.08

= 0.9

× V

CCO

2.7

= 0.1

× V

CCO

0.36

at V

(mA)

Note 1

at V

(mA)

Note 1

Notes:
1.

Tested according to the relevant specification.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

LVTTL

LVTTL requires no termination. DC voltage specifications
appears in

Table 34

LVCMOS2

LVCMOS2 requires no termination. DC voltage specifica-
tions appear in

Table 35

LVCMOS18

LVCMOS18 does not require termination.

Table 36

lists DC

voltage specifications.

AGP-2X

The specification for the AGP-2X standard does not docu-
ment a recommended termination technique. DC voltage
specifications appear in

Table 37

Table 34: LVTTL Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

2.0

3.6

-0.5

0.8

2.4

0.4

at V

(mA)

-24

at V

(mA)

Notes:
1.

Note: V

and V

for lower drive currents sample tested.

Table 35: LVCMOS2 Voltage Specifications

Parameter

Min

Typ

Max

CCO

2.3

2.5

2.7

REF

1.7

3.6

-0.5

0.7

1.9

0.4

at V

(mA)

-12

at V

(mA)

Table 36: LVCMOS18 Voltage Specifications

Parameter

Min

Typ

Max

CCO

1.70

1.80

1.90

REF

0.65 x V

CCO

1.95

0.5

0.2 x V

CCO

0.4

at V

(mA)

at V

(mA)

Table 37: AGP-2X Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

= N

× V

CCO

(1)

1.17

1.32

1.48

= V

REF

+ 0.2

1.37

1.52

= V

REF

0.2

1.12

1.28

= 0.9

× V

CCO

2.7

3.0

= 0.1

× V

CCO

0.33

0.36

at V

(mA)

Note 2

at V

(mA)

Note 2

Notes:
1.

N must be greater than or equal to 0.39 and less than or
equal to 0.41.

Tested according to the relevant specification.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

LVDS

Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in

Figure 54

. A sample circuit illustrating a

valid termination for receiving LVDS signals appears in

Figure 55

Table 38

lists DC voltage specifications. Further

information on the specific termination resistor packs shown
can be found on

Table 40

LVPECL

Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination technique for transmitting LVPECL signals
appears in

Figure 56

. A sample circuit illustrating a valid ter-

mination for receiving LVPECL signals appears in

Figure 57

Table 39

lists DC voltage specifications. Further

information on the specific termination resistor packs shown
can be found on

Table 40

Figure 54: Transmitting LVDS Signal Circuit

Figure 55: Receiving LVDS Signal Circuit

Table 38: LVDS Voltage Specifications

Parameter

Min

Typ

Max

CCO

2.375

2.5

2.625

ICM

(2)

0.2

1.25

2.2

OCM

(1)

1.125

1.25

1.375

IDIFF

(1)

0.1

0.35

ODIFF

(1)

0.25

0.35

0.45

(1)

1.25

(1)

1.25

Notes:
1.

Measured with a 100

resistor across Q and Q.

Measured with a differential input voltage =

+/- 350 mV.

x133_19_122799

Z0 = 50

Virtex-E

FPGA

to LVDS Receiver

RDIV
140

165

2.5V

CCO

= 2.5V

LVDS

Output

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-LV4F12

x133_29_122799

Z0 = 50

LVDS_IN

Z0 = 50

100

DATA

Receive

from

LVDS

Driver

VIRTEX-E

FPGA

Table 39: LVPECL Voltage Specifications

Parameter

Min

Typ

Max

CCO

3.0

3.3

3.6

REF

1.49

2.72

0.86

2.125

1.8

1.57

Notes:
1.

For more detailed information, see

LVPECL DC

Specifications

Figure 56: Transmitting LVPECL Signal Circuit

Figure 57: Receiving LVPECL Signal Circuit

x133_20_122799

Z0 = 50 LVPECL_OUT

LVPECL_OUT

Z0 = 50

Virtex-E

FPGA

to LVPECL Receiver

RDIV
187

100

3.3V

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-PC4F12

x133_21_122799

Z0 = 50

LVPECL_IN

Z0 = 50

100

DATA

Receive

from

LVPECL

Driver

VIRTEX-E

FPGA

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Termination Resistor Packs

Resistor packs are available with the values and the config-
uration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at

http://www.bourns.com

LVDS Design Guide

The SelectI/O library elements have been expanded for Vir-
tex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog librar-
ies. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.

Creating LVDS Global Clock Input Buffers

Global clock input buffers can be combined with adjacent
IOBs to form LVDS clock input buffers. P-side is the GCLK-
PAD location; N-side is the adjacent IO_LVDS_DLL site.

HDL Instantiation

Only one global clock input buffer is required to be instanti-
ated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.

In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the out-
put of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_external),

.O(clk_internal));

Location constraints

All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.

NET clk_external LOC = GCLKPAD3;

GCLKPAD3 can also be replaced with the package pin
name such as D17 for the BG432 package.

Table 40: Bourns LVDS/LVPECL Resistor Packs

Part Number

I/O Standard

Term.

for:

Pairs/

Pack

Pins

CAT16

-LV2F6

LVDS

Driver

CAT16

-LV4F12

LVDS

Driver

CAT16

-PC2F6

LVPECL

Driver

CAT16

-PC4F12

LVPECL

Driver

CAT16

-PT2F2

LVDS/LVPECL

Receiver

CAT16

-PT4F4

LVDS/LVPECL

Receiver

Figure 58: LVDS elements

IBUF_LVDS

OBUF_LVDS

IOBUF_LVDS

OBUFT_LVDS

IBUFG_LVDS

x133_22_122299

Table 41: Global Clock Input Buffer Pair Locations

Pkg

GCLK 3

GCLK 2

GCLK 1

GCLK 0

CS144

PQ240

P213

P215

P210 P209

P89

P87

P92

P93

HQ240

P213

P215

P210 P209

P89

P87

P92

P93

BG352

D14

A15

B14

A13

AF14

AD14

AE13

AC13

BG432

D17

C17

A16

B16

AK16

AL17

AL16

AH15

BG560

A17

C18

D17

E17

AJ17

AM18

AL17

AM17

FG256

FG456

C11

B11

A11

D11

Yll

AA11

W12

U12

FG676

E13

B13

C13

F14

AB13

AF13

AA14

AC14

FG680

A20

C22

D21

A19

AU22

AT22

AW19

AT21

FG860

C22

A22

B22

D22

AY22

AW21

BA22

AW20

FG900

C15

A15

E15

E16

AK16

AH16

AJ16

AF16

FG1156

E17

C17

D17

J18

Al19

AL17

AH18

AM18

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Optional N-side

Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_p_external, O=>clk_internal);

gclk0_n : IBUFG_LVDS port map

(I=>clk_n_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_p_external),

.O(clk_internal));

IBUFG_LVDS gclk0_n (.I(clk_n_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.

NET clk_p_external LOC = GCLKPAD3;

NET clk_n_external LOC = C17;

GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.

Creating LVDS Input Buffers

An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.

HDL Instantiation

Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.

VHDL Instantiation

data0_p : IBUF_LVDS port map (I=>data(0),

O=>data_int(0));

Verilog Instantiation

IBUF_LVDS data0_p (.I(data[0]),

.O(data_int[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the .ucf or .ncf file.

NET data<0> LOC = D28; # IO_L0P

Optional N-side

Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.

VHDL Instantiation

data0_p : IBUF_LVDS port map

(I=>data_p(0), O=>data_int(0));

data0_n : IBUF_LVDS port map

(I=>data_n(0), O=>open);

Verilog Instantiation

IBUF_LVDS data0_p (.I(data_p[0]),

.O(data_int[0]));

IBUF_LVDS data0_n (.I(data_n[0]), .O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the .ucf or .ncf file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Adding an Input Register

All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.

To improve design coding times VHDL and Verilog synthesis
macro libraries available to explicitly create these structures.
The input library macros are listed in

Table 42

. The I and IB

inputs to the macros are the external net connections.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Creating LVDS Output Buffers

LVDS output buffers can be placed in a wide number of IOB
locations. The exact locations are dependent on the pack-
age used. The Virtex-E package information lists the possi-
ble locations as IO_L#P for the P-side and IO_L#N for the
N-side, where # is the pair number.

HDL Instantiation

Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N loca-
tions. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.

VHDL Instantiation

data0_p : OBUF_LVDS port map

(I=>data_int(0), O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n : OBUF_LVDS port map

(I=>data_n_int(0), O=>data_n(0));

Verilog Instantiation

OBUF_LVDS data0_p (.I(data_int[0]),

.O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUF_LVDS data0_n (.I(data_n_int[0]),

.O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Outputs

If the outputs are synchronous (registered in the IOB) then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device.

The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
some point in the product lifetime, then only the common
pairs for all packages should be used.

Adding an Output Register

All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the soft-
ware.

To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in

Table 43

. The O and OB inputs to the macros are the exter-

nal net connections.

Table 42: Input Library Macros

Name

Inputs

Outputs

IBUFDS_FD_LVDS

I, IB, C

IBUFDS_FDE_LVDS

I, IB, CE, C

IBUFDS_FDC_LVDS

I, IB, C, CLR

IBUFDS_FDCE_LVDS

I, IB, CE, C, CLR

IBUFDS_FDP_LVDS

I, IB, C, PRE

IBUFDS_FDPE_LVDS

I, IB, CE, C, PRE

IBUFDS_FDR_LVDS

I, IB, C, R

IBUFDS_FDRE_LVDS

I, IB, CE, C, R

IBUFDS_FDS_LVDS

I, IB, C, S

IBUFDS_FDSE_LVDS

I, IB, CE, C, S

IBUFDS_LD_LVDS

I, IB, G

IBUFDS_LDE_LVDS

I, IB, GE, G

IBUFDS_LDC_LVDS

I, IB, G, CLR

IBUFDS_LDCE_LVDS

I, IB, GE, G, CLR

IBUFDS_LDP_LVDS

I, IB, G, PRE

IBUFDS_LDPE_LVDS

I, IB, GE, G, PRE

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Creating LVDS Output 3-State Buffers

LVDS output 3-state buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.

HDL Instantiation

Both output 3-state buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one High and one
Low). If 3-state registers are used, they must be initialized to
the same state. Failure to follow these rules leads to DRC
errors in the software.

VHDL Instantiation

data0_p: OBUFT_LVDS port map

(I=>data_int(0), T=>data_tri,

O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n: OBUFT_LVDS port map

(I=>data_n_int(0), T=>data_tri,

O=>data_n(0));

Verilog Instantiation

OBUFT_LVDS data0_p (.I(data_int[0]),

.T(data_tri), .O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUFT_LVDS data0_n (.I(data_n_int[0]),

.T(data_tri), .O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous 3-State Outputs

If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or COLUMN in the device. This applies for either the
3-state pin or the data out pin.

LVDS pairs that can be used as asynchronous outputs are
listed in the Virtex-E pinout tables. Some pairs are marked
as "asynchronous capable" for all devices in that package,
and others are marked as available only for that device in
the package. If the device size might be changed at some
point in the product lifetime, then only the common pairs for
all packages should be used.

Adding Output and 3-State Registers

Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The 3-state (T), 3-state clock enable
(CE), clock pin (C), output clock enable (CE) and set/reset
(CLR/PRE or S/R) pins must connect to the same source.
Failure to do this leads to a DRC error in the software.

Table 43: Output Library Macros

Name

Inputs

Outputs

OBUFDS_FD_LVDS

D, C

O, OB

OBUFDS_FDE_LVDS

DD, CE, C

O, OB

OBUFDS_FDC_LVDS

D, C, CLR

O, OB

OBUFDS_FDCE_LVDS

D, CE, C, CLR

O, OB

OBUFDS_FDP_LVDS

D, C, PRE

O, OB

OBUFDS_FDPE_LVDS

D, CE, C, PRE

O, OB

OBUFDS_FDR_LVDS

D, C, R

O, OB

OBUFDS_FDRE_LVDS

D, CE, C, R

O, OB

OBUFDS_FDS_LVDS

D, C, S

O, OB

OBUFDS_FDSE_LVDS

D, CE, C, S

O, OB

OBUFDS_LD_LVDS

D, G

O, OB

OBUFDS_LDE_LVDS

D, GE, G

O, OB

OBUFDS_LDC_LVDS

D, G, CLR

O, OB

OBUFDS_LDCE_LVDS

D, GE, G, CLR

O, OB

OBUFDS_LDP_LVDS

D, G, PRE

O, OB

OBUFDS_LDPE_LVDS

D, GE, G, PRE

O, OB

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The input library macros are listed below.
The 3-state is configured to be 3-stated at GSR and when
the PRE,CLR,S or R is asserted and shares it's clock
enable with the output register. If this is not desirable then
the library can be updated by the user for the desired func-
tionality. The O and OB inputs to the macros are the exter-
nal net connections.

Creating a LVDS Bidirectional Buffer

LVDS bidirectional buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.

HDL Instantiation

Both bidirectional buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the fol-
lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one HIGH and one
LOW). If 3-state registers are used, they must be initialized
to the same state. Failure to follow these rules leads to DRC
errors in the software.

VHDL Instantiation

data0_p: IOBUF_LVDS port map

(I=>data_out(0), T=>data_tri,

IO=>data_p(0), O=>data_int(0));

data0_inv: INV port map

(I=>data_out(0), O=>data_n_out(0));

data0_n : IOBUF_LVDS port map

(I=>data_n_out(0), T=>data_tri,

IO=>data_n(0), O=>open);

Verilog Instantiation

IOBUF_LVDS data0_p(.I(data_out[0]),

.T(data_tri), .IO(data_p[0]),

.O(data_int[0]);

INV data0_inv (.I(data_out[0],

.O(data_n_out[0]);

IOBUF_LVDS

data0_n(.I(data_n_out[0]),.T(data_tri),.

IO(data_n[0]).O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the .ucf or .ncf file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Bidirectional
Buffers

If the output side of the bidirectional buffers are synchro-
nous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asyn-
chronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.

The LVDS pairs that can be used as asynchronous bidirec-
tional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product's lifetime, then only the com-
mon pairs for all packages should be used.

Adding Output and 3-State Registers

All LVDS buffers can have an output and input registers in
the IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.

The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the "map
-pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b"
is both inputs and outputs. To improve design coding times
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirec-
tional I/O library macros are listed in

Table 44

. The 3-state is

configured to be 3-stated at GSR and when the PRE,CLR,S
or R is asserted and shares its clock enable with the output
and input register. If this is not desirable then the library can
be updated be the user for the desired functionality. The I/O
and IOB inputs to the macros are the external net connec-
tions.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 2 of 4

www.xilinx.com

DS022-2 (v2.6) November 19, 2002

1-800-255-7778

Production Product Specification

Revision History

The following table shows the revision history for this document.

Table 44: Bidirectional I/O Library Macros

Name

Inputs

Bidirectional

Outputs

IOBUFDS_FD_LVDS

D, T, C

IO, IOB

IOBUFDS_FDE_LVDS

D, T, CE, C

IO, IOB

IOBUFDS_FDC_LVDS

D, T, C, CLR

IO, IOB

IOBUFDS_FDCE_LVDS

D, T, CE, C, CLR

IO, IOB

IOBUFDS_FDP_LVDS

D, T, C, PRE

IO, IOB

IOBUFDS_FDPE_LVDS

D, T, CE, C, PRE

IO, IOB

IOBUFDS_FDR_LVDS

D, T, C, R

IO, IOB

IOBUFDS_FDRE_LVDS

D, T, CE, C, R

IO, IOB

IOBUFDS_FDS_LVDS

D, T, C, S

IO, IOB

IOBUFDS_FDSE_LVDS

D, T, CE, C, S

IO, IOB

IOBUFDS_LD_LVDS

D, T, G

IO, IOB

IOBUFDS_LDE_LVDS

D, T, GE, G

IO, IOB

IOBUFDS_LDC_LVDS

D, T, G, CLR

IO, IOB

IOBUFDS_LDCE_LVDS

D, T, GE, G, CLR

IO, IOB

IOBUFDS_LDP_LVDS

D, T, G, PRE

IO, IOB

IOBUFDS_LDPE_LVDS

D, T, GE, G, PRE

IO, IOB

Date

Version

Revision

12/7/99

1.0

Initial Xilinx release.

1/10/00

1.1

Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.

1/28/00

1.2

Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T

BYP

values, buffered Hex Line info, p. 8, I/O Timing

Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.

2/29/00

1.3

Updated pinout tables, V

page 20, and corrected Figure 20.

5/23/00

1.4

Correction to table on p. 22.

7/10/00

1.5

Numerous minor edits.

Data sheet upgraded to Preliminary.

Preview -8 numbers added to Virtex-E Electrical Characteristics tables.

8/1/00

1.6

Reformatted entire document to follow new style guidelines.

Changed speed grade values in tables on pages 35-37.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-2 (v2.6) November 19, 2002

www.xilinx.com

Module 2 of 4

Production Product Specification

1-800-255-7778

Virtex-E Data Sheet

The Virtex-E Data Sheet contains the following modules:

DS022-1, Virtex-E 1.8V FPGAs:

Introduction and Ordering Information (Module 1)

DS022-2, Virtex-E 1.8V FPGAs:

Functional Description (Module 2)

DS022-3, Virtex-E 1.8V FPGAs:

DC and Switching Characteristics (Module 3)

DS022-4, Virtex-E 1.8V FPGAs:

Pinout Tables (Module 4)

9/20/00

1.7

Min values added to Virtex-E Electrical Characteristics tables.

XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).

Corrected user I/O count for XCV100E device in Table 1 (Module 1).

Changed several pins to "No Connect in the XCV100E" and removed duplicate V

CCINT

pins in Table ~ (Module 4).

Changed pin J10 to "No connect in XCV600E" in Table 74 (Module 4).

Changed pin J30 to "VREF option only in the XCV600E" in Table 74 (Module 4).

Corrected pair 18 in Table 75 (Module 4) to be "AO in the XCV1000E, XCV1600E".

11/20/00

1.8

Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.

Updated minimums in Table 13 and added notes to Table 14.

Added to note 2 to Absolute Maximum Ratings.

Changed speed grade -8 numbers for T

SHCKO32

, T

REG

, T

BCCS

, and T

ICKOF

Changed all minimum hold times to 0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.

Revised maximum T

DLLPW

in -6 speed grade for DLL Timing Parameters.

Changed GCLK0 to BA22 for FG860 package in Table 46.

2/12/01

1.9

Revised footnote for Table 14.

Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.

Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.

Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.

Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.

4/02/01

2.0

Updated numerous values in

Virtex-E Switching Characteristics

tables.

Converted data sheet to modularized format. See the

Virtex-E Data Sheet

section.

4/19/01

2.1

Modified

Figure 30

"DLL Generation of 4x Clock in Virtex-E Devices."

07/23/01

2.2

Made minor edits to text under

Configuration

Added CLB column locations for XCV2600E anbd XCV3200E devices in

Table 3

11/09/01

2.3

Added warning under

Configuration

section that attempting to load an incorrect

bitstream causes configuration to fail and can damage the device.

07/17/02

2.4

Data sheet designation upgraded from Preliminary to Production.

09/10/02

2.5

Added clarification to the

Input/Output Block

Configuration

Boundary-Scan Mode

and

Block SelectRAM

sections. Revised

Figure 18

Table 11

, and

Table 36

11/19/02

2.6

Added clarification in the

Boundary Scan

section.

Removed last sentence regarding deactivation of duty-cycle correction in

Duty Cycle

Correction Property

section.

Date

Version

Revision

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Virtex-E Electrical Characteristics

Definition of Terms

Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:

Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.

Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.

Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.

All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.

Table 1

correlates the current status of each Virtex-E device

with a corresponding speed file designation.

All specifications are subject to change without notice.

VirtexTM-E 1.8 V
Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

Production Product Specification

Table 1: Virtex-E Device Speed Grade Designations

Device

Speed Grade Designations

Advance

Preliminary

Production

XCV50E

8, 7, 6

XCV100E

8, 7, 6

XCV200E

8, 7, 6

XCV300E

8, 7, 6

XCV400E

8, 7, 6

XCV600E

8, 7, 6

XCV1000E

8, 7, 6

XCV1600E

8, 7, 6

XCV2000E

8, 7, 6

XCV2600E

8, 7, 6

XCV3200E

8, 7, 6

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

DC Characteristics

Absolute Maximum Ratings

Recommended Operating Conditions

Symbol

Description

(1)

Units

CCINT

Internal Supply voltage relative to GND

0.5 to 2.0

CCO

Supply voltage relative to GND

0.5 to 4.0

REF

Input Reference Voltage

0.5 to 4.0

(3)

Input voltage relative to GND

0.5 to V

CCO

+0.5

Voltage applied to 3-state output

0.5 to 4.0

Longest Supply Voltage Rise Time from 0 V - 1.71 V

STG

Storage temperature (ambient)

65 to +150

°C

Junction temperature

(2)

Plastic packages

+125

°C

Notes:
1.

Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.

For soldering guidelines and thermal considerations, see the device packaging information on

www.xilinx.com

Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the
device is not PCI compliant.

Symbol

Description

Min

Max

Units

CCINT

Internal Supply voltage relative to GND, T

= 0

°C to +85 °C

Commercial

1.8 5%

1.8 + 5%

Internal Supply voltage relative to GND, T

= 40

°C to +100 °C

Industrial

1.8 5%

1.8 + 5%

CCO

Supply voltage relative to GND, T

= 0

°C to +85 °C

Commercial

1.2

3.6

Supply voltage relative to GND, T

= 40

°C to +100 °C

Industrial

1.2

3.6

Input signal transition time

250

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Device

Min

Max

Units

DRINT

Data Retention V

CCINT

Voltage

(below which configuration data might be lost)

All

1.5

DRIO

Data Retention V

CCO

Voltage

(below which configuration data might be lost)

All

1.2

CCINTQ

Quiescent V

CCINT

supply current (Note 1)

XCV50E

200

XCV100E

200

XCV200E

300

XCV300E

300

XCV400E

300

XCV600E

400

XCV1000E

500

XCV1600E

500

XCV2000E

500

XCV2600E

500

XCV3200E

500

CCOQ

Quiescent V

CCO

supply current (Note 1)

XCV50E

XCV100E

XCV200E

XCV300E

XCV400E

XCV600E

XCV1000E

XCV1600E

XCV2000E

XCV2600E

XCV3200E

Input or output leakage current

All

+10

µA

Input capacitance (sample tested)

BGA, PQ, HQ, packages

All

RPU

Pad pull-up (when selected) @ V

= 0 V, V

CCO

= 3.3 V (sample tested)

All

Note 2

0.25

RPD

Pad pull-down (when selected) @ V

= 3.6 V (sample tested)

Note 2

0.25

Notes:
1.

With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.

Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device

from 0V. The fastest ramp rate is 0V to nominal voltage in 2 ms, and the slowest allowed

ramp rate is 0V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158 on

www.xilinx.com

DC Input and Output Levels

Values for V

and V

are recommended input voltages. Values for I

and I

are guaranteed over the recommended

operating conditions at the V

and V

test points. Only selected standards are tested. These are chosen to ensure that

all standards meet their specifications. The selected standards are tested at minimum V

CCO

with the respective V

and

voltage levels shown. Other standards are sample tested.

Product (Commercial Grade)

Description

(2)

Current Requirement

(3)

XCV50E - XCV600E

Minimum required current supply

500 mA

XCV812E - XCV2000E

Minimum required current supply

1 A

XCV2600E - XCV3200E

Minimum required current supply

1.2 A

Virtex-E Family, Industrial Grade

Minimum required current supply

2 A

Notes:
1.

Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.

Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.

Larger currents might result if ramp rates are forced to be faster.

Input/Output

Standard

V, Min

V, Max

V, Min

V, Max

V, Min

LVTTL

(1)

0.5

0.8

2.0

3.6

0.4

2.4

LVCMOS2

0.5

0.7

1.7

2.7

0.4

1.9

LVCMOS18

0.5

35% V

CCO

65% V

CCO

1.95

0.4

CCO

0.4

PCI, 3.3 V

0.5

30% V

CCO

50% V

CCO

+ 0.5

10% V

CCO

90% V

CCO

Note 2

GTL

0.5

REF

0.05

REF

+ 0.05

3.6

0.4

n/a

GTL+

0.5

REF

0.1

REF

+ 0.1

3.6

0.6

n/a

HSTL I

(3)

0.5

REF

0.1

REF

+ 0.1

3.6

0.4

CCO

0.4

HSTL III

0.5

REF

0.1

REF

+ 0.1

3.6

0.4

CCO

0.4

HSTL IV

0.5

REF

0.1

REF

+ 0.1

3.6

0.4

CCO

0.4

SSTL3 I

0.5

REF

0.2

REF

+ 0.2

3.6

REF

0.6

REF

+ 0.6

SSTL3 II

0.5

REF

0.2

REF

+ 0.2

3.6

REF

0.8

REF

+ 0.8

SSTL2 I

0.5

REF

0.2

REF

+ 0.2

3.6

REF

0.61

REF

+ 0.61

7.6

SSTL2 II

0.5

REF

0.2

REF

+ 0.2

3.6

REF

0.80

REF

+ 0.80

15.2

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

LVDS DC Specifications

LVPECL DC Specifications

These values are valid at the output of the source termination pack shown under

LVPECL

, with a 100

differential load only.

The V

levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode

ranges. The following table summarizes the DC output specifications of LVPECL.

CTT

0.5

REF

0.2

REF

+ 0.2

3.6

REF

0.4

REF

+ 0.4

AGP

0.5

REF

0.2

REF

+ 0.2

3.6

10% V

CCO

90% V

CCO

Note 2

Notes:
1.

and V

for lower drive currents are sample tested.

Tested according to the relevant specifications.

DC input and output levels for HSTL18 (HSTL I/O standard with V

CCO

of 1.8 V) are provided in an HSTL white paper on

www.xilinx.com

DC Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply Voltage

CCO

2.375

2.5

2.625

Output High Voltage for Q and Q

= 100

across Q and Q signals

1.25

1.425

1.6

Output Low Voltage for Q and Q

= 100

across Q and Q signals

0.9

1.075

1.25

Differential Output Voltage (Q Q),

Q = High (Q Q), Q = High

ODIFF

= 100

across Q and Q signals

250

350

450

Output Common-Mode Voltage

OCM

= 100

across Q and Q signals

1.125

1.25

1.375

Differential Input Voltage (Q Q),

Q = High (Q Q), Q = High

IDIFF

Common-mode input voltage = 1.25 V

100

350

Input Common-Mode Voltage

ICM

Differential input voltage =

±350 mV

0.2

1.25

2.2

Note: Refer to the Design Consideration section for termination schematics.

Input/Output

Standard

V, Min

V, Max

V, Min

V, Max

V, Min

DC Parameter

Min

Max

Min

Max

Min

Max

Units

CCO

3.0

3.3

3.6

1.8

2.11

1.92

2.28

2.13

2.41

0.96

1.27

1.06

1.43

1.30

1.57

1.49

2.72

1.49

2.72

1.49

2.72

0.86

2.125

0.86

2.125

0.86

2.125

Differential Input Voltage

0.3

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Virtex-E Switching Characteristics

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All
timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Virtex-E devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for LVTTL levels in

Table 2

. For other standards, adjust the delays with the

values shown in

IOB Input Switching Characteristics Standard Adjustments, page 8

Table 2: IOB Input Switching Characteristics

Speed Grade

(1)

Units

Description

(2)

Symbol

Device

Min

-8

-7

-6

Propagation Delays

Pad to I output, no delay

IOPI

All

0.43

0.8

0.8 ns,

max

Pad to I output, with delay

IOPID

XCV50E

0.51

1.0

1.0 ns,

max

XCV100E

0.51

1.0

1.0 ns,

max

XCV200E

0.51

1.0

1.0 ns,

max

XCV300E

0.51

1.0

1.0 ns,

max

XCV400E

0.51

1.0

1.0 ns,

max

XCV600E

0.51

1.0

1.0 ns,

max

XCV1000E

0.55

1.1

1.1 ns,

max

XCV1600E

0.55

1.1

1.1 ns,

max

XCV2000E

0.55

1.1

1.1 ns,

max

XCV2600E

0.55

1.1

1.1 ns,

max

XCV3200E

0.55

1.1

1.1 ns,

max

Pad to output IQ via transparent
latch, no delay

IOPLI

All

0.8

1.4

1.5

1.6 ns,

max

Pad to output IQ via transparent
latch, with delay

IOPLID

XCV50E

1.31

2.9

3.0

3.1 ns,

max

XCV100E

1.31

2.9

3.0

3.1 ns,

max

XCV200E

1.39

3.1

3.2

3.3 ns,

max

XCV300E

1.39

3.1

3.2

3.3 ns,

max

XCV400E

1.43

3.2

3.3

3.4 ns,

max

XCV600E

1.55

3.5

3.6

3.7 ns,

max

XCV1000E

1.55

3.5

3.6

3.7 ns,

max

XCV1600E

1.59

3.6

3.7

3.8 ns,

max

XCV2000E

1.59

3.6

3.7

3.8 ns,

max

XCV2600E

1.59

3.6

3.7

3.8 ns,

max

XCV3200E

1.59

3.6

3.7

3.8 ns,

max

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Sequential Delays

Clock CLK

Minimum Pulse Width, High

All

0.56

1.2

1.3

1.4

ns, min

Minimum Pulse Width, Low

0.56

1.2

1.3

1.4

ns, min

Clock CLK to output IQ

IOCKIQ

0.18

0.4

0.7

ns, max

Setup and Hold Times with respect to Clock at IOB Input
Register

Pad, no delay

IOPICK

IOICKP

All

0.69 / 0

1.3 / 0

1.4 / 0

1.5 / 0

ns, min

Pad, with delay

IOPICKD

IOICKPD

XCV50E

1.25 / 0

2.8 / 0

2.9 / 0

ns, min

XCV100E

1.25 / 0

2.8 / 0

2.9 / 0

ns, min

XCV200E

1.33 / 0

3.0 / 0

3.1 / 0

ns, min

XCV300E

1.33 / 0

3.0 / 0

3.1 / 0

ns, min

XCV400E

1.37 / 0

3.1 / 0

3.2 / 0

ns, min

XCV600E

1.49 / 0

3.4 / 0

3.5 / 0

ns, min

XCV1000E

1.49 / 0

3.4 / 0

3.5 / 0

ns, min

XCV1600E

1.53 / 0

3.5 / 0

3.6 / 0

ns, min

XCV2000E

1.53 / 0

3.5 / 0

3.6 / 0

ns, min

XCV2600E

1.53 / 0

3.5 / 0

3.6 / 0

ns, min

XCV3200E

1.53 / 0

3.5 / 0

3.6 / 0

ns, min

ICE input

IOICECK

IOCKICE

All

0.28 /

0.0

0.55 /

0.01

0.7 /
0.01

ns, min

SR input (IFF, synchronous)

IOSRCKI

All

0.38

0.8

0.9

1.0 ns,

min

Set/Reset Delays

SR input to IQ (asynchronous)

IOSRIQ

All

0.54

1.1

1.2

1.4 ns,

max

GSR to output IQ

GSRQ

All

3.88

7.6

8.5

9.7 ns,

max

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see

Table 4

Table 2: IOB Input Switching Characteristics (Continued)

Speed Grade

(1)

Units

Description

(2)

Symbol

Device

Min

-8

-7

-6

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

IOB Input Switching Characteristics Standard Adjustments

Speed Grade

(1)

Units

Description

Symbol

Standard

Min

-8

-7

-6

Data Input Delay Adjustments

Standard-specific data input delay
adjustments

ILVTTL

LVTTL

0.0

0.0 ns

ILVCMOS2

LVCMOS2

0.02

0.0

0.0 ns

ILVCMOS18

LVCMOS18

0.12

+0.20

ILVDS

LVDS

0.00

+0.15

ILVPECL

LVPECL

0.00

+0.15

IPCI33_3

PCI, 33 MHz, 3.3 V

0.05

+0.08

IPCI66_3

PCI, 66 MHz, 3.3 V

0.05

0.11

IGTL

GTL

+0.10

+0.14

IGTLPLUS

GTL+

+0.06

+0.14

IHSTL

HSTL

+0.02

+0.04

ISSTL2

SSTL2

0.04

+0.04

ISSTL3

SSTL3

0.02

+0.04

ICTT

CTT

+0.01

+0.10

IAGP

AGP

0.03

+0.04

Notes:
1.

Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see

Table 4

Figure 1: Virtex-E Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

T
TCE

D
CE

PAD

Programmable

Delay

Weak

Keeper

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

IOB Output Switching Characteristics,

Figure 1

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in

IOB Output Switching Characteristics Standard Adjustments, page 10

Speed Grade

(1)

Units

Description

(2)

Symbol

Min

-8

-7

-6

Propagation Delays

O input to Pad

IOOP

1.04

2.5

2.7

2.9 ns,

max

O input to Pad via transparent latch

IOOLP

1.24

2.9

3.1

3.4 ns,

max

3-State Delays

T input to Pad high-impedance (Note 2)

IOTHZ

0.73

1.5

1.7

1.9 ns,

max

T input to valid data on Pad

IOTON

1.13

2.7

2.9

3.1 ns,

max

T input to Pad high-impedance via transparent
latch (Note 2)

IOTLPHZ

0.86

1.8

2.0

2.2 ns,

max

T input to valid data on Pad via transparent latch

IOTLPON

1.26

3.0

3.2

3.4 ns,

max

GTS to Pad high impedance (Note 2)

GTS

1.94

4.1

4.6

4.9 ns,

max

Sequential Delays

Clock CLK

Minimum Pulse Width, High

0.56

1.2

1.3

1.4

ns, min

Minimum Pulse Width, Low

0.56

1.2

1.3

1.4

ns, min

Clock CLK to Pad

IOCKP

0.97

2.4

2.8

2.9 ns,

max

Clock CLK to Pad high-impedance (synchronous)
(Note 2)

IOCKHZ

0.77

1.6

2.0

2.2 ns,

max

Clock CLK to valid data on Pad (synchronous)

IOCKON

1.17

2.8

3.2

3.4 ns,

max

Setup and Hold Times before/after Clock CLK

O input

IOOCK

/ T

IOCKO

0.43 / 0

0.9 / 0

1.0 / 0

1.1 / 0

ns, min

OCE input

IOOCECK

/ T

IOCKOCE

0.28 / 0

0.55 / 0.01

0.7 / 0

ns, min

SR input (OFF)

IOSRCKO

/ T

IOCKOSR

0.40 / 0

0.8 / 0

0.9 / 0

1.0 / 0

ns, min

3-State Setup Times, T input

IOTCK

/ T

IOCKT

0.26 / 0

0.51 / 0

0.6 / 0

0.7 / 0

ns, min

3-State Setup Times, TCE input

IOTCECK

/ T

IOCKTCE

0.30 / 0

0.6 / 0

0.7 / 0

0.8 / 0

ns, min

3-State Setup Times, SR input (TFF)

IOSRCKT

/ T

IOCKTSR

0.38 / 0

0.8 / 0

0.9 / 0

1.0 / 0

ns, min

Set/Reset Delays

SR input to Pad (asynchronous)

IOSRP

1.30

3.1

3.3

3.5 ns,

max

SR input to Pad high-impedance (asynchronous)
(Note 2)

IOSRHZ

1.08

2.2

2.4

2.7 ns,

max

SR input to valid data on Pad (asynchronous)

IOSRON

1.48

3.4

3.7

3.9 ns,

max

GSR to Pad

IOGSRQ

3.88

7.6

8.5

9.7 ns,

max

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

3-state turn-off delays should not be adjusted.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.

Speed Grade

Units

Description

Symbol

Standard

Min

-8

-7

-6

Output Delay Adjustments

Standard-specific adjustments for output
delays terminating at pads (based on
standard capacitive load, Csl)

OLVTTL_S2

LVTTL, Slow, 2 mA

4.2

+14.7

OLVTTL_S4

4 mA

2.5

+7.5

OLVTTL_S6

6 mA

1.8

+4.8

OLVTTL_S8

8 mA

1.2

+3.0

OLVTTL_S12

12 mA

1.0

+1.9

OLVTTL_S16

16 mA

0.9

+1.7

OLVTTL_S24

24 mA

0.8

+1.3

OLVTTL_F2

LVTTL, Fast, 2 mA

1.9

+13.1

OLVTTL_F4

4 mA

0.7

+5.3

OLVTTL_F6

6 mA

0.20

+3.1

OLVTTL_F8

8 mA

0.10

+1.0

OLVTTL_F12

12 mA

0.0

OLVTTL_F16

16 mA

0.10

0.05

OLVTTL_F24

24 mA

0.10

0.20

OLVCMOS_2

LVCMOS2

0.10

+0.09

OLVCMOS_18

LVCMOS18

0.10

+0.7

+0.7 ns

OLVDS

LVDS

0.39

1.2

1.2 ns

OLVPECL

LVPECL

0.20

0.41

OPCI33_3

PCI, 33 MHz, 3.3 V

0.50

+2.3

OPCI66_3

PCI, 66 MHz, 3.3 V

0.10

0.41

OGTL

GTL

0.6

+0.49

OGTLP

GTL+

0.7

+0.8

+0.8 ns

OHSTL_I

HSTL I

0.10

0.51

OHSTL_III

HSTL III

0.10

0.91

OHSTL_IV

HSTL IV

0.20

1.01

OSSTL2_I

SSTL2 I

0.10

0.51

OSSTL2_II

SSTL2 II

0.20

0.91

OSSTL3_I

SSTL3 I

0.20

0.51

OSSTL3_II

SSTL3 II

0.30

1.01

OCTT

CTT

0.0

0.61

OAGP

AGP

0.1

0.91

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Calculation of T

ioop

as a Function of Capacitance

ioop

is the propagation delay from the O Input of the IOB to

the pad. The values for T

ioop

are based on the standard

capacitive load (C

) for each I/O standard as listed in

Table 3

For other capacitive loads, use the formulas below to calcu-
late the corresponding T

ioop

= T

ioop

+ T

opadjust

load

) * fl

where:

opadjust

is reported above in the Output Delay

Adjustment section.

load

is the capacitive load for the design.

Table 3: Constants for Use in Calculation of T

ioop

Standard

Csl (pF)

fl (ns/pF)

LVTTL Fast Slew Rate, 2mA drive

0.41

LVTTL Fast Slew Rate, 4mA drive

0.20

LVTTL Fast Slew Rate, 6mA drive

0.13

LVTTL Fast Slew Rate, 8mA drive

0.079

LVTTL Fast Slew Rate, 12mA drive

0.044

LVTTL Fast Slew Rate, 16mA drive

0.043

LVTTL Fast Slew Rate, 24mA drive

0.033

LVTTL Slow Slew Rate, 2mA drive

0.41

LVTTL Slow Slew Rate, 4mA drive

0.20

LVTTL Slow Slew Rate, 6mA drive

0.10

LVTTL Slow Slew Rate, 8mA drive

0.086

LVTTL Slow Slew Rate, 12mA drive

0.058

LVTTL Slow Slew Rate, 16mA drive

0.050

LVTTL Slow Slew Rate, 24mA drive

0.048

LVCMOS2

0.041

LVCMOS18

0.050

PCI 33 MHZ 3.3 V

0.050

PCI 66 MHz 3.3 V

0.033

GTL

0.014

GTL+

0.017

HSTL Class I

0.022

HSTL Class III

0.016

HSTL Class IV

0.014

SSTL2 Class I

0.028

SSTL2 Class II

0.016

SSTL3 Class I

0.029

SSTL3 Class II

0.016

CTT

0.035

AGP

0.037

Notes:
1.

I/O parameter measurements are made with the capacitance
values shown above. See the application examples (in
Module 2 of this data sheet) for appropriate terminations.

I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.

Table 4: Delay Measurement Methodology

Standard

Meas.

Point

REF

(Typ)

LVTTL

1.4

LVCMOS2

2.5

1.125

PCI33_3

Per PCI Spec

PCI66_3

Per PCI Spec

GTL

REF

0.2

REF

+0.2

REF

0.80

GTL+

REF

0.2

REF

+0.2

REF

1.0

HSTL Class I

REF

0.5

REF

+0.5

REF

0.75

HSTL Class III

REF

0.5

REF

+0.5

REF

0.90

HSTL Class IV

REF

0.5

REF

+0.5

REF

0.90

SSTL3 I & II

REF

1.0

REF

+1.0

REF

1.5

SSTL2 I & II

REF

0.75

REF

+0.75

REF

1.25

CTT

REF

0.2

REF

+0.2

REF

1.5

AGP

REF

(0.2xV

CCO

)

REF

(0.2xV

CCO

)

REF

Per

AGP

Spec

LVDS

1.2

0.125

1.2 + 0.125

1.2

LVPECL

1.6

0.3

1.6 + 0.3

1.6

Notes:
1.

Input waveform switches between V

and V

Measurements are made at V

REF

(Typ), Maximum, and

Minimum. Worst-case values are reported.
I/O parameter measurements are made with the
capacitance values shown in

Table 3

. See the application

examples (in Module 2 of this data sheet) for appropriate
terminations.

I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Clock Distribution Switching Characteristics

I/O Standard Global Clock Input Adjustments

Speed Grade

Units

Description

Symbol

Min

-8

-7

-6

GCLK IOB and Buffer

Global Clock PAD to output.

GPIO

0.38

0.7

ns, max

Global Clock Buffer I input to O output

GIO

0.11

0.20

0.45

0.50

ns, max

Description

Symbol

(1)

Standard

Speed Grade

Units

Min

-8

-7

-6

Data Input Delay Adjustments

Standard-specific global clock
input delay adjustments

GPLVTTL

LVTTL

0.0

ns, max

GPLVCMOS2

LVCMOS2

0.02

0.0

ns, max

GPLVCMOS18

LVCMOS18

0.12

0.20

ns, max

GLVDS

LVDS

0.23

0.38

ns, max

GLVPECL

LVPECL

0.23

0.38

ns, max

GPPCI33_3

PCI, 33 MHz, 3.3 V

0.05

0.08

ns, max

GPPCI66_3

PCI, 66 MHz, 3.3 V

0.05

0.11

ns, max

GPGTL

GTL

0.20

0.37

ns, max

GPGTLP

GTL+

0.20

0.37

ns, max

GPHSTL

HSTL

0.18

0.27

ns, max

GPSSTL2

SSTL2

0.21

0.27

ns, max

GPSSTL3

SSTL3

0.18

0.27

ns, max

GPCTT

CTT

0.22

0.33

ns, max

GPAGP

AGP

0.21

0.27

ns, max

Notes:
1.

Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see

Table 4

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

CLB Switching Characteristics

Delays originating at F/G inputs vary slightly according to the input used, see

Figure 2

. The values listed below are

worst-case. Precise values are provided by the timing analyzer.

Speed Grade

(1)

Units

Description

Symbol

Min

-8

-7

-6

Combinatorial Delays

4-input function: F/G inputs to X/Y outputs

ILO

0.19

0.40

0.42

0.47

ns, max

5-input function: F/G inputs to F5 output

IF5

0.36

0.76

0.8

0.9 ns,

max

5-input function: F/G inputs to X output

IF5X

0.35

0.74

0.8

0.9 ns,

max

6-input function: F/G inputs to Y output via F6 MUX

IF6Y

0.35

0.74

0.9

1.0 ns,

max

6-input function: F5IN input to Y output

F5INY

0.04

0.11

0.20

0.22

ns, max

Incremental delay routing through transparent latch to
XQ/YQ outputs

IFNCTL

0.27

0.63

0.7

0.8 ns,

max

BY input to YB output

BYYB

0.19

0.38

0.46

0.51

ns, max

Sequential Delays

FF Clock CLK to XQ/YQ outputs

CKO

0.34

0.78

0.9

1.0 ns,

max

Latch Clock CLK to XQ/YQ outputs

CKLO

0.40

0.77

0.9

1.0 ns,

max

Setup and Hold Times before/after Clock CLK

4-input function: F/G Inputs

ICK

CKI

0.39 / 0

0.9 / 0

1.0 / 0

1.1 / 0

ns, min

5-input function: F/G inputs

IF5CK

CKIF5

0.55 / 0

1.3 / 0

1.4 / 0

1.5 / 0

ns, min

6-input function: F5IN input

F5INCK

CKF5IN

0.27 / 0

0.6 / 0

0.8 / 0

ns, min

6-input function: F/G inputs via F6 MUX

IF6CK

CKIF6

0.58 / 0

1.3 / 0

1.5 / 0

1.6 / 0

ns, min

BX/BY inputs

DICK

CKDI

0.25 / 0

0.6 / 0

0.7 / 0

0.8 / 0

ns, min

CE input

CECK

CKCE

0.28 / 0

0.55 / 0

0.7 / 0

ns, min

SR/BY inputs (synchronous)

RCK /

CKR

0.24 / 0

0.46 / 0

0.52 / 0

0.6 / 0

ns, min

Clock CLK

Minimum Pulse Width, High

0.56

1.2

1.3

1.4 ns,

min

Minimum Pulse Width, Low

0.56

1.2

1.3

1.4 ns,

min

Set/Reset

Minimum Pulse Width, SR/BY inputs

RPW

0.94

1.9

2.1

2.4 ns,

min

Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)

0.39

0.8

0.9

1.0

ns, max

Toggle Frequency (MHz) (for export control)

TOG

416

400

357

MHz

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

CLB Arithmetic Switching Characteristics

Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.

Speed

Grade

(1)

Units

Description

Symbol

Min

-8

-7

-6

Combinatorial Delays

F operand inputs to X via XOR

OPX

0.32

0.68

0.8

ns, max

F operand input to XB output

OPXB

0.35

0.65

0.8

0.9

ns, max

F operand input to Y via XOR

OPY

0.59

1.07

1.4

1.5

ns, max

F operand input to YB output

OPYB

0.48

0.89

1.1

1.3

ns, max

F operand input to COUT output

OPCYF

0.37

0.71

0.9

1.0

ns, max

G operand inputs to Y via XOR

OPGY

0.34

0.72

0.8

0.9

ns, max

G operand input to YB output

OPGYB

0.47

0.78

1.2

1.3

ns, max

G operand input to COUT output

OPCYG

0.36

0.60

0.9

1.0

ns, max

BX initialization input to COUT

BXCY

0.19

0.36

0.51

0.57

ns, max

CIN input to X output via XOR

CINX

0.27

0.50

0.6

0.7

ns, max

CIN input to XB

CINXB

0.02

0.04

0.07

0.08

ns, max

CIN input to Y via XOR

CINY

0.26

0.45

0.7

ns, max

CIN input to YB

CINYB

0.16

0.28

0.38

0.43

ns, max

CIN input to COUT output

BYP

0.05

0.10

0.14

0.15

ns, max

Multiplier Operation

F1/2 operand inputs to XB output via AND

FANDXB

0.10

0.30

0.35

0.39

ns, max

F1/2 operand inputs to YB output via AND

FANDYB

0.28

0.56

0.7

0.8

ns, max

F1/2 operand inputs to COUT output via AND

FANDCY

0.17

0.38

0.46

0.51

ns, max

G1/2 operand inputs to YB output via AND

GANDYB

0.20

0.46

0.55

0.7

ns, max

G1/2 operand inputs to COUT output via AND

GANDCY

0.09

0.28

0.30

0.34

ns, max

Setup and Hold Times before/after Clock CLK

CIN input to FFX

CCKX

CKCX

0.47 / 0

1.0 / 0

1.2 / 0

1.3 / 0

ns, min

CIN input to FFY

CCKY

CKCY

0.49 / 0

0.92 / 0

1.2 / 0

1.3 / 0

ns, min

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

CLB Distributed RAM Switching Characteristics

Speed Grade

(1)

Units

Description

Symbol

Min

-8

-7

-6

Sequential Delays

Clock CLK to X/Y outputs (WE active) 16 x 1 mode

SHCKO16

0.67

1.38

1.5

1.7

ns, max

Clock CLK to X/Y outputs (WE active) 32 x 1 mode

SHCKO32

0.84

1.66

1.9

2.1

ns, max

Shift-Register Mode

Clock CLK to X/Y outputs

REG

1.25

2.39

2.9

3.2

ns, max

Setup and Hold Times before/after Clock CLK

F/G address inputs

0.19 / 0

0.38 / 0

0.42 / 0

0.47 / 0

ns, min

BX/BY data inputs (DIN)

0.44 / 0

0.87 / 0

0.97 / 0

1.09 / 0

ns, min

SR input (WE)

0.29 / 0

0.57 / 0

0.7 / 0

0.8 / 0

ns, min

Clock CLK

Minimum Pulse Width, High

WPH

0.96

1.9

2.1

2.4 ns,

min

Minimum Pulse Width, Low

WPL

0.96

1.9

2.1

2.4 ns,

min

Minimum clock period to meet address write cycle time

1.92

3.8

4.2

4.8 ns,

min

Shift-Register Mode

Minimum Pulse Width, High

SRPH

1.0

1.9

2.1

2.4 ns,

min

Minimum Pulse Width, Low

SRPL

1.0

1.9

2.1

2.4 ns,

min

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

Figure 3: Dual-Port Block SelectRAM

WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]

WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_06_121699

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Block RAM Switching Characteristics

TBUF Switching Characteristics

JTAG Test Access Port Switching Characteristics

Speed Grade

(1)

Units

Description

Symbol

Min

-8

-7

-6

Sequential Delays

Clock CLK to DOUT output

BCKO

0.63

2.46

3.1

3.5

ns, max

Setup and Hold Times before Clock CLK

ADDR inputs

BACK

BCKA

0.42 / 0

0.9 / 0

1.0 / 0

1.1 / 0

ns, min

DIN inputs

BDCK

BCKD

0.42 / 0

0.9 / 0

1.0 / 0

1.1 / 0

ns, min

EN input

BECK

BCKE

0.97 / 0

2.0 / 0

2.2 / 0

2.5 / 0

ns, min

RST input

BRCK

BCKR

0.9 / 0

1.8 / 0

2.1 / 0

2.3 / 0

ns, min

WEN input

BWCK

BCKW

0.86 / 0

1.7 / 0

2.0 / 0

2.2 / 0

ns, min

Clock CLK

Minimum Pulse Width, High

BPWH

0.6

1.2

1.35

1.5 ns,

min

Minimum Pulse Width, Low

BPWL

0.6

1.2

1.35

1.5 ns,

min

CLKA -> CLKB setup time for different ports

BCCS

1.2

2.4

2.7

3.0

ns, min

Notes:
1.

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

Speed Grade

Units

Description

Symbol

Min

-8

-7

-6

Combinatorial Delays

IN input to OUT output

0.0

0 .0

ns, max

TRI input to OUT output high-impedance

OFF

0.05

0.092

0.10

0.11

ns, max

TRI input to valid data on OUT output

0.05

0.092

0.10

0.11

ns, max

Description

Symbol

Value

Units

TMS and TDI Setup times before TCK

TAPTK

4.0

ns, min

TMS and TDI Hold times after TCK

TCKTAP

2.0

ns, min

Output delay from clock TCK to output TDO

TCKTDO

11.0

ns, max

Maximum TCK clock frequency

TCK

MHz, max

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Virtex-E Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL

Description

(1)

Symbol

Device

Speed Grade

(2, 3)

Units

Min

-8

-7

-6

LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL. For data output with different standards,
adjust the delays with the values shown in

IOB

Output Switching Characteristics Standard
Adjustments, page 10

ICKOFDLL

XCV50E

1.0

3.1

XCV100E

1.0

3.1

XCV200E

1.0

3.1

XCV300E

1.0

3.1

XCV400E

1.0

3.1

XCV600E

1.0

3.1

XCV1000E

1.0

3.1

XCV1600E

1.0

3.1

XCV2000E

1.0

3.1

XCV2600E

1.0

3.1

XCV3200E

1.0

3.1

Notes:
1.

Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.

Output timing is measured at 50% V

threshold with 35 pF external capacitive load. For other I/O standards and different loads, see

Table 3

and

Table 4

DLL output jitter is already included in the timing calculation.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL

Description

(1)

Symbol

Device

Speed Grade

(2)

Units

Min

-8

-7

-6

LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DLL. For data output with different standards,
adjust the delays with the values shown in

IOB

Output Switching Characteristics Standard
Adjustments, page 10

ICKOF

XCV50E

1.5

4.2

4.4

4.6

XCV100E

1.5

4.2

4.4

4.6

XCV200E

1.5

4.3

4.5

4.7

XCV300E

1.5

4.3

4.5

4.7

XCV400E

1.5

4.4

4.6

4.8

XCV600E

1.6

4.5

4.7

4.9

XCV1000E

1.7

4.6

4.8

5.0

XCV1600E

1.8

4.7

4.9

5.1

XCV2000E

1.8

4.8

5.0

5.2

XCV2600E

2.0

5.0

5.2

5.4

XCV3200E

2.2

5.2

5.4

5.6

Notes:
1.

Output timing is measured at 50% V

threshold with 35 pF external capacitive load. For other I/O standards and different loads, see

Table 3

and

Table 4

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Virtex-E Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted

Global Clock Set-Up and Hold for LVTTL Standard, with DLL

Description

(1)

Symbol

Device

Speed Grade

(2, 3)

Units

Min

-8

-7

-6

Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards,
adjust the setup time delay by the values shown in

IOB Input

Switching Characteristics Standard Adjustments, page 8

No Delay

PSDLL

PHDLL

XCV50E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

Global Clock and IFF, with DLL

XCV100E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV200E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV300E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV400E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV600E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV1000E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV1600E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV2000E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV2600E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

XCV3200E

1.5 / 0.4

1.6 / 0.4

1.7 / 0.4

Notes:
1.

IFF = Input Flip-Flop or Latch

Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.

DLL output jitter is already included in the timing calculation.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Global Clock Set-Up and Hold for LVTTL Standard, without DLL

Description

(1)

Symbol

Device

Speed Grade

(2, 3)

Units

Min

-8

-7

-6

Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard. For data input with different standards, adjust
the setup time delay by the values shown in

IOB Input Switching

Characteristics Standard Adjustments, page 8

Full Delay

PSFD

PHFD

XCV50E

1.8 / 0

Global Clock and IFF, without DLL

XCV100E

1.8 / 0

XCV200E

1.9 / 0

XCV300E

2.0 / 0

XCV400E

2.0 / 0

XCV600E

2.1 / 0

XCV1000E

2.3 / 0

XCV1600E

2.5 / 0

XCV2000E

2.5 / 0

XCV2600E

2.7 / 0

XCV3200E

2.8 / 0

Notes:
1.

IFF = Input Flip-Flop or Latch

A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

DLL Timing Parameters

All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.

Description

Symbol

CLKIN

Speed Grade

Units

-8

-7

-6

Min

Max

Min

Max

Min

Max

Input Clock Frequency (CLKDLLHF)

FCLKINHF

350

320

275

MHz

Input Clock Frequency (CLKDLL)

FCLKINLF

160

135

MHz

Input Clock Low/High Pulse Width

DLLPW

25 MHz

5.0

50 MHz

3.0

100 MHz

2.4

150 MHz

2.0

200 MHz

1.8

250 MHz

1.5

300 MHz

1.3

Figure 4: DLL Timing Waveforms

TCLKIN

TCLKIN + TIPTOL

Period Tolerance: the allowed input clock period change in nanoseconds.

Output Jitter: the difference between an ideal
reference clock edge and the actual design.

ds022_24_091200

Ideal Period

Actual Period

+ Jitter

+/- Jitter

+ Maximum
Phase Difference

Phase Offset and Maximum Phase Difference

+ Phase Offset

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

DLL Clock Tolerance, Jitter, and Phase Information

All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.

CLKDLLHF

CLKDLL

Units

Description

Symbol

CLKIN

Min

Max

Min

Max

Input Clock Period Tolerance

IPTOL

1.0

Input Clock Jitter Tolerance (Cycle to Cycle)

IJITCC

± 150

± 300

Time Required for DLL to Acquire Lock

(6)

LOCK

> 60 MHz

µs

50 - 60 MHz

µs

40 - 50 MHz

µs

30 - 40 MHz

µs

25 - 30 MHz

120

µs

Output Jitter (cycle-to-cycle) for any DLL Clock Output

(1)

OJITCC

± 60

Phase Offset between CLKIN and CLKO

(2)

PHIO

± 100

Phase Offset between Clock Outputs on the DLL

(3)

PHOO

± 140

Maximum Phase Difference between CLKIN and CLKO

(4)

PHIOM

± 160

Maximum Phase Difference between Clock Outputs on the DLL

(5)

PHOOM

± 200

Notes:
1.

Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.

Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.

Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.

Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).

Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).

Add 30% to the value for industrial grade parts.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 3 of 4

www.xilinx.com

DS022-3 (v2.9.2) March 14, 2003

1-800-255-7778

Production Product Specification

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

12/7/99

1.0

Initial Xilinx release.

1/10/00

1.1

Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.

1/28/00

1.2

Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T

BYP

values, buffered Hex Line info, p. 8, I/O Timing

Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.

2/29/00

1.3

Updated pinout tables, V

page 20, and corrected Figure 20.

5/23/00

1.4

Correction to table on p. 22.

7/10/00

1.5

Numerous minor edits.

Data sheet upgraded to Preliminary.

Preview -8 numbers added to Virtex-E Electrical Characteristics tables.

8/1/00

1.6

Reformatted entire document to follow new style guidelines.

Changed speed grade values in tables on pages 35-37.

9/20/00

1.7

Min values added to Virtex-E Electrical Characteristics tables.

XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).

Corrected user I/O count for XCV100E device in Table 1 (Module 1).

Changed several pins to "No Connect in the XCV100E" and removed duplicate V

CCINT

pins in Table ~ (Module 4).

Changed pin J10 to "No connect in XCV600E" in Table 74 (Module 4).

Changed pin J30 to "VREF option only in the XCV600E" in Table 74 (Module 4).

Corrected pair 18 in Table 75 (Module 4) to be "AO in the XCV1000E, XCV1600E".

11/20/00

1.8

Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.

Updated minimums in Table 13 and added notes to Table 14.

Added to note 2 to Absolute Maximum Ratings.

Changed speed grade -8 numbers for T

SHCKO32

, T

REG

, T

BCCS

, and T

ICKOF

Changed all minimum hold times to 0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.

Revised maximum T

DLLPW

in -6 speed grade for DLL Timing Parameters.

Changed GCLK0 to BA22 for FG860 package in Table 46.

2/12/01

1.9

Revised footnote for Table 14.

Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.

Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.

Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.

Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.

4/02/01

2.0

Updated numerous values in

Virtex-E Switching Characteristics

tables.

Converted data sheet to modularized format. See the

Virtex-E Data Sheet

section.

4/19/01

2.1

Updated values in

Virtex-E Switching Characteristics

tables.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-3 (v2.9.2) March 14, 2003

www.xilinx.com

Module 3 of 4

Production Product Specification

1-800-255-7778

Virtex-E Data Sheet

The Virtex-E Data Sheet contains the following modules:

DS022-1, Virtex-E 1.8V FPGAs:

Introduction and Ordering Information (Module 1)

DS022-2, Virtex-E 1.8V FPGAs:

Functional Description (Module 2)

DS022-3, Virtex-E 1.8V FPGAs:

DC and Switching Characteristics (Module 3)

DS022-4, Virtex-E 1.8V FPGAs:

Pinout Tables (Module 4)

07/23/01

2.2

Under

Absolute Maximum Ratings

, changed (T

SOL

) to 220

°C.

Changes made to SSTL symbol names in

IOB Input Switching Characteristics

Standard Adjustments

table.

07/26/01

2.3

Removed T

SOL

parameter and added footnote to

Absolute Maximum Ratings

table.

9/18/01

2.4

Reworded power supplies footnote to

Absolute Maximum Ratings

table.

10/25/01

2.5

Updated the speed grade designations used in data sheets, and added

Table 1

, which

shows the current speed grade designation for each device.

Added XCV2600E and XCV3200E values to

DC Characteristics Over Recommended

Operating Conditions

and

Power-On Power Supply Requirements

tables.

11/09/01

2.6

Updated the

Power-On Power Supply Requirements

table.

02/01/02

2.7

Updated footnotes to the

DC Input and Output Levels

and

DLL Clock Tolerance,

Jitter, and Phase Information

tables.

07/17/02

2.8

Data sheet designation upgraded from Preliminary to Production.

Removed mention of MIL-M-38510/605 specification.

Added link to XAPP158 from the

Power-On Power Supply Requirements

section.

09/10/02

2.9

Revised V

Absolute Maximum Ratings

table.

Added Clock CLK switching characteristics to

Table 2, "IOB Input Switching

Characteristics," on page 6

and

IOB Output Switching Characteristics, Figure 1

12/22/02

2.9.1

Added footnote regarding V

PCI compliance to

Absolute Maximum Ratings

table.

The fastest ramp rate is 0V to nominal voltage in 2 ms

03/14/03

2.9.2

Under

Power-On Power Supply Requirements

, the fastest ramp rate is no longer a

"suggested" rate.

Date

Version

Revision

http://www.xilinx.com/legal.htm

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

Virtex-E Pin Definitions

VirtexTM-E 1.8 V
Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

Production Product Specification

Pin Name

Dedicated Pin

Direction

Description

GCK0, GCK1,

GCK2, GCK3

Yes

Input

Clock input pins that connect to Global Clock Buffers.

M0, M1, M2

Yes

Input

Mode pins are used to specify the configuration mode.

CCLK

Yes

Input or

Output

The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After
configuration, it is input only, logic level = Don't Care.

PROGRAM

Yes

Input

Initiates a configuration sequence when asserted Low.

DONE

Yes

Bidirectional

Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.

INIT

Bidirectional

(Open-drain)

When Low, indicates that the configuration memory is being cleared.
The pin becomes a user I/O after configuration.

BUSY/DOUT

Output

In SelectMAP mode, BUSY controls the rate at which configuration
data is loaded. The pin becomes a user I/O after configuration unless
the SelectMAP port is retained.

In bit-serial modes, DOUT provides preamble and configuration data
to downstream devices in a daisy-chain. The pin becomes a user I/O
after configuration.

D0/DIN,

D1, D2,

D3, D4,

D5, D6,

Input or

Output

In SelectMAP mode, D0-7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.

In bit-serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.

WRITE

Input

In SelectMAP mode, the active-low Write Enable signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.

Input

In SelectMAP mode, the active-low Chip Select signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.

TDI, TDO,

TMS, TCK

Yes

Mixed

Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.

DXN, DXP

Yes

N/A

Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)

CCINT

Yes

Input

Power-supply pins for the internal core logic.

CCO

Yes

Input

Power-supply pins for the output drivers (subject to banking rules)

REF

Input

Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).

GND

Yes

Input

Ground

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

Pinout Differences Between Virtex and Virtex-E Families

The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions, listed in

Table 1

XCV200E Device, FG456 Package

The Virtex-E XCV200E has two I/O pins swapped with the
Virtex XCV200 to accommodate differential clock pairing.

XCV400E Device, FG676 Package

The Virtex-E XCV400E has two I/O pins swapped with the
Virtex XCV400 to accommodate differential clock pairing.

All Devices, PQ240 and HQ240 Packages

The Virtex devices in PQ240 and HQ240 packages do not
have V

CCO

banking, but Virtex-E devices do. To achieve

this, eight Virtex I/O pins (P232, P207, P176, P146, P116,
P85, P55, and P25) are now VCCO pins in the Virtex-E fam-
ily. This change also requires one Virtex I/O or VREF pin to
be swapped with a standard I/O pin.

Additionally, accommodating differential clock input pairs in
Virtex-E caused some IO_V

REF

differences in the XCV400E

and XCV600E devices only. Virtex IO_V

REF

pins P215 and

P87 are Virtex-E IO_V

REF

pins P216 and P86, respectively.

Virtex-E pins P215 and P87 are IO_DLL.

Table 1: Pinout Differences Summary

Part

Package

Pins

Virtex

Virtex-E

XCV200

FG456

E11, U11

I/O

No Connect

B11, AA11

No Connect

IO_LVDS_DLL

XCV400

FG676

D13, Y13

I/O

No Connect

B13, AF13

No Connect

IO_LVDS_DLL

XCV400/600

PQ240/HQ240

P215, P87

IO_V

REF

IO_LVDS_DLL

P216, P86

I/O

IO_V

REF

All

PQ240/HQ240

P232, P207, P176, P146, P116, P85, P55, and P25

I/O

CCO

P231

I/O

IO_V

REF

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

Low Voltage Differential Signals

The Virtex-E family incorporates low-voltage signalling
(LVDS and LVPECL). Two pins are utilized for these signals
to be connected to a Virtex-E device. These are known as
differential pin pairs. Each differential pin pair has a Positive
(P) and a Negative (N) pin. These pairs are labeled in the
following manner.

IO_L#[P/N]

where

L = LVDS or LVPECL pin
# = Pin Pair Number
P = Positive
N = Negative

I/O pins for differential signals can either be synchronous or
asynchronous, input or output. The pin pairs can be used for
synchronous input and output signals as well as asynchro-
nous input signals. However, only some of the low-voltage
pairs can be used for asynchronous output signals.

DIfferential signals require the pins of a pair to switch almost
simultaneously. If the signals driving the pins are from IOB
flip-flops, they are synchronous. If the signals driving the
pins are from internal logic, they are asynchronous.

Table 2

defines the names and function of the different types of
low-voltage pin pairs in the Virtex-E family.

Virtex-E Package Pinouts

The Virtex-E family of FPGAs is available in 12 popular
packages, including chip-scale, plastic and high heat-dissi-
pation quad flat packs, and ball grid and fine-pitch ball grid
arrays. Family members have footprint compatibility across
devices provided in the same package. The pinout tables in

this section indicate function, pin, and bank information for
each package/device combination. Following each pinout
table is an additional table summarizing information specific
to differential pin pairs for all devices provided in that pack-
age.

Table 2: LVDS Pin Pairs

Pin Name

Description

IO_L#[P/N]

Example: IO_L22N

Represents a general IO or a
synchronous input/output
differential signal. When used
as a differential signal, N
means Negative I/O and P
means Positive I/O.

IO_L#[P/N]_Y

Example: IO_L22N_Y

Represents a general IO or a
synchronous input/output
differential signal, or a
part-dependent asynchronous
output differential signal.

IO_L#[P/N]_YY

Example: O_L22N_YY

Represents a general IO or a
synchronous input/output
differential signal, or an
asynchronous output
differential signal.

IO_LVDS_DLL_L#[P/N]

Example:

IO_LVDS_DLL_L16N

Represents a general IO or a
synchronous input/output
differential signal, a differential
clock input signal, or a DLL
input. When used as a
differential clock input, this pin
is paired with the adjacent
GCK pin. The GCK pin is
always the positive input in the
differential clock input
configuration.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

CS144 Chip-Scale Package

XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in CS144 Chip-scale packages have footprint com-
patibility. In the CS144 package, bank pairs that share a
side are internally interconnected, permitting four choices
for V

CCO

. See

Table 3

Pins labeled I0_VREF can be used as either in all parts
unless device-dependent, as indicated in the footnotes. If
the pin is not used as V

REF

, it can be used as general I/O.

Immediately following

Table 4

, see

Table 5

is Differential

Pair information.

Table 3: I/O Bank Pairs and Shared Vcco Pins

Paired Banks

Shared V

CCO

Pins

Banks 0 & 1

A2, A13, D7

Banks 2 & 3

B12, G11, M13

Banks 4 & 5

N1, N7, N13

Banks 6 & 7

B2, G2, M2

Table 4: CS144 -- XCV50E, XCV100E, XCV200E

Bank

Pin Description

Pin #

GCK3

IO_VREF_L0N_YY

IO_L0P_YY

IO_L1N_YY

IO_L1P_YY

IO_LVDS_DLL_L2N

IO_VREF

GCK2

IO_LVDS_DLL_L2P

IO_L3N_YY

IO_L3P_YY

IO_L4N_YY

IO_VREF_L4P_YY

IO_WRITE_L5N_YY

C10

IO_CS_L5P_YY

D10

IO_VREF

A10

IO_VREF

B10

D12

F12

IO_DOUT_BUSY_L6P_YY

C11

IO_DIN_D0_L6N_YY

C12

IO_D1_L7N

E10

IO_VREF_L7P

D13

IO_L8N_YY

E13

IO_D2_L8P_YY

E12

IO_D3_L9N

F11

IO_VREF_L9P

F10

IO_L10P

F13

IO_VREF

C13

IO_VREF

D11

H13

K13

IO_L10N

G13

IO_VREF_L11N

H11

IO_D4_L11P

H12

IO_D5_L12N_YY

J13

IO_L12P_YY

H10

IO_VREF_L13N

J10

IO_D6_L13P

J11

IO_INIT_L14N_YY

L13

IO_D7_L14P_YY

K10

IO_VREF

K11

IO_VREF

K12

GCK0

M10

Table 4: CS144 -- XCV50E, XCV100E, XCV200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L15N_YY

M11

IO_L15P_YY

L11

IO_L16N_YY

IO_VREF_L16P_YY

N10

IO_L17N_YY

IO_L17P_YY

IO_LVDS_DLL_L18P

IO_VREF

L10

IO_VREF

N11

GCK1

IO_LVDS_DLL_L18N

IO_L19N_YY

IO_L19P_YY

IO_VREF_L20N_YY

IO_L20P_YY

IO_L21N_YY

IO_L21P_YY

IO_VREF

IO_L25P

IO_VREF_L25N

IO_L24P_YY

IO_L24N_YY

IO_L23P

IO_VREF_L23N

IO_VREF

IO_L22N_YY

IO_L22P_YY

Table 4: CS144 -- XCV50E, XCV100E, XCV200E

Bank

Pin Description

Pin #

IO_L26N

IO_L26P

IO_L27N

IO_VREF_L27P

IO_L28N_YY

IO_L28P_YY

IO_L29N

IO_VREF_L29P

IO_VREF

CCLK

B13

DONE

M12

PROGRAM

L12

TDI

A11

TCK

TDO

A12

TMS

VCCINT

G12

VCCINT

VCCO

Table 4: CS144 -- XCV50E, XCV100E, XCV200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

CS144 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.

VCCO

A13

VCCO

B12

VCCO

G11

VCCO

M13

VCCO

N13

VCCO

GND

B11

GND

E11

GND

G10

GND

J12

GND

N12

Notes:
1.

REF

or I/O option only in the XCV200E; otherwise, I/O

option only.

REF

or I/O option only in the XCV100E, 200E; otherwise,

I/O option only.

Table 4: CS144 -- XCV50E, XCV100E, XCV200E

Bank

Pin Description

Pin #

Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

IO_DLL_L18P

IO_DLL_L18N

IO_DLL_L2P

IO_DLL_L2N

IO LVDS

Total Pairs: 30, Asynchronous Output Pairs: 18

VREF

IO_LVDS_DLL

VREF

D10

C10

CS, WRITE

C11

C12

DIN, D0

D13

E10

D1, VREF

E12

E13

F10

F11

D3, VREF

F13

G13

H12

H11

D4, VREF

H10

J13

J11

J10

D6, VREF

K10

L13

INIT

L11

M11

N10

VREF

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

PQ240 Plastic Quad Flat-Pack Packages

XCV50E, XCV100E, XCV200E, XCV300E and XCV400E
devices in PQ240 Plastic Flat-pack packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V

REF

, it can be used as gen-

eral I/O. Immediately following

Table 6

, see

Table 7

for

Differential Pair information.

IO_LVDS_DLL

VREF

Note 1: AO in the XCV50E

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

P238

P237

IO_L0N_Y

P236

IO_VREF_L0P_Y

P235

IO_L1N_YY

P234

IO_L1P_YY

P231

IO_VREF

P230

P229

IO_VREF_L2N_YY

P228

IO_L2P_YY

P224

IO_L3N_YY

P223

IO_L3P_YY

Table 5: CS144 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E

Pair

Bank

Pin

Other

Functions

P222

P221

IO_L4N_Y

P220

IO_L4P_Y

P218

IO_VREF_L5N_Y

P217

IO_L5P_Y

P216

IO_VREF

P215

IO_LVDS_DLL_L6N

P213

GCK3

P210

GCK2

P209

IO_LVDS_DLL_L6P

P208

IO_VREF

P206

IO_L7N_Y

P205

IO_VREF_L7P_Y

P203

IO_L8N_Y

P202

IO_L8P_Y

P201

P200

IO_L9N_YY

P199

IO_L9P_YY

P195

IO_L10N_YY

P194

IO_VREF_L10P_YY

P193

P192

IO_L11N_YY

P191

IO_VREF_L11P_YY

P189

IO_L12N_YY

P188

IO_L12P_YY

P187

IO_VREF_L13N_Y

P186

IO_L13P_Y

P185

IO_WRITE_L14N_YY

P184

IO_CS_L14P_YY

P178

IO_DOUT_BUSY_L15P_YY

P177

IO_DIN_D0_L15N_YY

P175

IO_VREF

P174

IO_L16P_Y

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

P173

IO_L16N_Y

P171

IO_VREF_L17P_Y

P170

IO_L17N_Y

P169

P168

IO_VREF_L18P_Y

P167

IO_D1_L18N_Y

P163

IO_D2_L19P_YY

P162

IO_L19N_YY

P161

P160

IO_L20P_Y

P159

IO_L20N_Y

P157

IO_VREF_L21P_Y

P156

IO_D3_L21N_Y

P155

IO_L22P_Y

P154

IO_VREF_L22N_Y

P153

IO_L23P_YY

P152

IO_L23N_YY

P149

P147

IO_VREF

P145

IO_D4_L24P_Y

P144

IO_VREF_L24N_Y

P142

IO_L25P_Y

P141

IO_L25N_Y

P140

P139

IO_L26P_YY

P138

IO_D5_L26N_YY

P134

IO_D6_L27P_Y

P133

IO_VREF_L27N_Y

P132

P131

IO_L28P_Y

P130

IO_VREF_L28N_Y

P128

IO_L29P_Y

P127

IO_L29N_Y

P126

IO_VREF_L30P_Y

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

P125

IO_L30N_Y

P124

IO_D7_L31P_YY

P123

IO_INIT_L31N_YY

P118

IO_L32P_YY

P117

IO_L32N_YY

P115

IO_VREF

P114

IO_L33P_YY

P113

IO_L33N_YY

P111

IO_VREF_L34P_YY

P110

IO_L34N_YY

P109

P108

IO_VREF_L35P_YY

P107

IO_L35N_YY

P103

IO_L36P_YY

P102

IO_L36N_YY

P101

P100

IO_L37P_Y

P99

IO_L37N_Y

P97

IO_VREF_L38P_Y

P96

IO_L38N_Y

P95

IO_L39P_Y

P94

IO_VREF_L39N_Y

P93

IO_LVDS_DLL_L40P

P92

GCK0

P89

GCK1

P87

IO_LVDS_DLL_L40N

P86

IO_VREF

P84

IO_VREF_L41P_Y

P82

IO_L41N_Y

P81

P80

P79

IO_L42P_YY

P78

IO_L42N_YY

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

P74

IO_L43P_YY

P73

IO_VREF_L43N_YY

P72

P71

IO_L44P_YY

P70

IO_VREF_L44N_YY

P68

IO_L45P_YY

P67

IO_L45N_YY

P66

IO_VREF_L46P_Y

P65

IO_L46N_Y

P64

IO_L47P_YY

P63

IO_L47N_YY

P57

IO_L48N_YY

P56

IO_L48P_YY

P54

IO_VREF

P53

IO_L49N_Y

P52

IO_L49P_Y

P50

IO_VREF_L50N_Y

P49

IO_L50P_Y

P48

P47

IO_VREF_L51N_Y

P46

IO_L51P_Y

P42

IO_L52N_YY

P41

IO_L52P_YY

P40

P39

IO_L53N_Y

P38

IO_L53P_Y

P36

IO_VREF_L54N_Y

P35

IO_L54P_Y

P34

IO_L55N_Y

P33

IO_VREF_L55P_Y

P31

P28

IO_L56N_YY

P27

IO_L56P_YY

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

P26

IO_VREF

P24

IO_L57N_Y

P23

IO_VREF_L57P_Y

P21

IO_L58N_Y

P20

IO_L58P_Y

P19

P18

IO_L59N_YY

P17

IO_L59P_YY

P13

IO_L60N_Y

P12

IO_VREF_L60P_Y

P11

P10

IO_L61N_Y

IO_VREF_L61P_Y

IO_L62N_Y

IO_L62P_Y

IO_VREF_L63N_Y

IO_L63P_Y

P179

CCLK

P120

DONE

P60

P58

P62

P122

PROGRAM

P183

TDI

P239

TCK

P181

TDO

TMS

P225

VCCINT

P214

VCCINT

P198

VCCINT

P164

VCCINT

P148

VCCINT

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

P137

VCCINT

P104

VCCINT

P88

VCCINT

P77

VCCINT

P43

VCCINT

P32

VCCINT

P16

VCCINT

P240

VCCO

P232

VCCO

P226

VCCO

P212

VCCO

P207

VCCO

P197

VCCO

P180

VCCO

P176

VCCO

P165

VCCO

P150

VCCO

P146

VCCO

P136

VCCO

P121

VCCO

P116

VCCO

P105

VCCO

P90

VCCO

P85

VCCO

P76

VCCO

P61

VCCO

P55

VCCO

P44

VCCO

P30

VCCO

P25

VCCO

P15

VCCO

P233

GND

P227

GND

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

P219

GND

P211

GND

P204

GND

P196

GND

P190

GND

P182

GND

P172

GND

P166

GND

P158

GND

P151

GND

P143

GND

P135

GND

P129

GND

P119

GND

P112

GND

P106

GND

P98

GND

P91

GND

P83

GND

P75

GND

P69

GND

P59

GND

P51

GND

P45

GND

P37

GND

P29

GND

P22

GND

P14

GND

Notes:
1.

REF

or I/O option only in the XCV100E, 200E, 300E, 400E;

otherwise, I/O option only.

REF

or I/O option only in the XCV200E, 300E, 400E;

otherwise, I/O option only.

REF

or I/O option only in the XCV400E; otherwise, I/O

option only.

Table 6: PQ240 -- XCV50E, XCV100E, XCV200E,
XCV300E, XCV400E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

PQ240 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E

Pair

Bank

P Pin

N Pin

Other

Functions

Global Differential Clock

P92

P93

IO_DLL_L40P

P89

P87

IO_DLL_L40N

P210

P209

IO_DLL_L6P

P213

P215

IO_DLL_L6N

IO LVDS

Total Pairs: 64, Asynchronous Outputs Pairs: 27

P236

P237

VREF

P234

P235

P228

P229

VREF

P223

P224

P220

P221

P217

P218

VREF

P209

P215

IO_LVDS_DLL

P205

P206

VREF

P202

P203

P199

P200

P194

P195

VREF

P191

P192

VREF

P188

P189

P186

P187

VREF

P184

P185

P178

P177

DIN, D0

P174

P173

P171

P170

VREF

P168

P167

D1, VREF

P163

P162

P160

P159

P157

P156

D3, VREF

P155

P154

VREF

P153

P152

P145

P144

D4, VREF

P142

P141

P139

P138

P134

P133

VREF

P131

P130

VREF

P128

P127

P126

P125

VREF

P124

P123

INIT

P118

P117

P114

P113

P111

P110

VREF

P108

P107

VREF

P103

P102

P100

P99

P97

P96

VREF

P95

P94

VREF

P93

P87

IO_LVDS_DLL

P84

P82

VREF

P79

P78

P74

P73

VREF

P71

P70

VREF

P68

P67

P66

P65

VREF

P64

P63

Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E

Pair

Bank

P Pin

N Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

HQ240 High-Heat Quad Flat-Pack Packages

XCV600E and XCV1000E devices in High-heat dissipation
Quad Flat-pack packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V

REF

, it can be used as general I/O. Immedi-

ately following

Table 8

, see

Table 9

for Differential Pair infor-

mation.

P56

P57

P52

P53

P49

P50

VREF

P46

P47

VREF

P41

P42

P38

P39

P35

P36

VREF

P33

P34

VREF

P27

P28

P23

P24

VREF

P20

P21

P17

P18

P12

P13

VREF

P10

VREF

Notes:
1.

AO in the XCV50E.

AO in the XCV50E, 100E, 200E, 300E.

AO in the XCV50E, 200E, 300E, 400E.

AO in the XCV50E, 300E, 400E.

AO in the XCV100E, 200E, 400E.

AO in the XCV100E, 400E.

AO in the XCV50E, 200E, 400E.

AO in the XCV100E.

Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E

Pair

Bank

P Pin

N Pin

Other

Functions

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

P240

VCCO

P239

TCK

P238

P237

IO_L0N

P236

IO_VREF_L0P

P235

IO_L1N_YY

P234

IO_L1P_YY

P233

GND

P232

VCCO

P231

IO_VREF

P230

IO_VREF

P229

IO_VREF_L2N_YY

P228

IO_L2P_YY

P227

GND

P226

VCCO

P225

VCCINT

P224

IO_L3N_YY

P223

IO_L3P_YY

P222

IO_VREF

P221

IO_L4N_Y

P220

IO_L4P_Y

P219

GND

P218

IO_VREF_L5N_Y

P217

IO_L5P_Y

P216

IO_VREF

P215

IO_LVDS_DLL_L6N

P214

VCCINT

P213

GCK3

P212

VCCO

P211

GND

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

P210

GCK2

P209

IO_LVDS_DLL_L6P

P208

IO_VREF

P207

VCCO

P206

IO_L7N_Y

P205

IO_VREF_L7P_Y

P204

GND

P203

IO_L8N_Y

P202

IO_L8P_Y

P201

IO_VREF

P200

IO_L9N_YY

P199

IO_L9P_YY

P198

VCCINT

P197

VCCO

P196

GND

P195

IO_L10N_YY

P194

IO_VREF_L10P_YY

P193

IO_VREF

P192

IO_L11N_YY

P191

IO_VREF_L11P_YY

P190

GND

P189

IO_L12N_YY

P188

IO_L12P_YY

P187

IO_VREF_L13N

P186

IO_L13P

P185

IO_WRITE_L14N_YY

P184

IO_CS_L14P_YY

P183

TDI

P182

GND

P181

TDO

P180

VCCO

P179

CCLK

P178

IO_DOUT_BUSY_L15P_YY

P177

IO_DIN_D0_L15N_YY

P176

VCCO

P175

IO_VREF

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

P174

IO_L16P_Y

P173

IO_L16N_Y

P172

GND

P171

IO_VREF_L17P_Y

P170

IO_L17N_Y

P169

IO_VREF

P168

IO_VREF_L18P_Y

P167

IO_D1_L18N_Y

P166

GND

P165

VCCO

P164

VCCINT

P163

IO_D2_L19P_YY

P162

IO_L19N_YY

P161

IO_VREF

P160

IO_L20P_Y

P159

IO_L20N_Y

P158

GND

P157

IO_VREF_L21P_Y

P156

IO_D3_L21N_Y

P155

IO_L22P_Y

P154

IO_VREF_L22N_Y

P153

IO_L23P_YY

P152

IO_L23N_YY

P151

GND

P150

VCCO

P149

P148

VCCINT

P147

IO_VREF

P146

VCCO

P145

IO_D4_L24P_Y

P144

IO_VREF_L24N_Y

P143

GND

P142

IO_L25P_Y

P141

IO_L25N_Y

P140

IO_VREF

P139

IO_L26P_YY

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

P138

IO_D5_L26N_YY

P137

VCCINT

P136

VCCO

P135

GND

P134

IO_D6_L27P_Y

P133

IO_VREF_L27N_Y

P132

IO_VREF

P131

IO_L28P_Y

P130

IO_VREF_L28N_Y

P129

GND

P128

IO_L29P_Y

P127

IO_L29N_Y

P126

IO_VREF_L30P_Y

P125

IO_L30N_Y

P124

IO_D7_L31P_YY

P123

IO_INIT_L31N_YY

P122

PROGRAM

P121

VCCO

P120

DONE

P119

GND

P118

IO_L32P_YY

P117

IO_L32N_YY

P116

VCCO

P115

IO_VREF

P114

IO_L33P_YY

P113

IO_L33N_YY

P112

GND

P111

IO_VREF_L34P_YY

P110

IO_L34N_YY

P109

IO_VREF

P108

IO_VREF_L35P_YY

P107

IO_L35N_YY

P106

GND

P105

VCCO

P104

VCCINT

P103

IO_L36P_YY

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

P102

IO_L36N_YY

P101

IO_VREF

P100

IO_L37P_Y

P99

IO_L37N_Y

P98

GND

P97

IO_VREF_L38P_Y

P96

IO_L38N_Y

P95

IO_L39P

P94

IO_VREF_L39N

P93

IO_LVDS_DLL_L40P

P92

GCK0

P91

GND

P90

VCCO

P89

GCK1

P88

VCCINT

P87

IO_LVDS_DLL_L40N

P86

IO_VREF

P85

VCCO

P84

IO_VREF_L41P

P83

GND

P82

IO_L41N

P81

P80

IO_VREF

P79

IO_L42P_YY

P78

IO_L42N_YY

P77

VCCINT

P76

VCCO

P75

GND

P74

IO_L43P_YY

P73

IO_VREF_L43N_YY

P72

IO_VREF

P71

IO_L44P_YY

P70

IO_VREF_L44N_YY

P69

GND

P68

IO_L45P_YY

P67

IO_L45N_YY

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

P66

IO_VREF_L46P

P65

IO_L46N

P64

IO_L47P_YY

P63

IO_L47N_YY

P62

P61

VCCO

P60

P59

GND

P58

P57

IO_L48N_YY

P56

IO_L48P_YY

P55

VCCO

P54

IO_VREF

P53

IO_L49N_Y

P52

IO_L49P_Y

P51

GND

P50

IO_VREF_L50N_Y

P49

IO_L50P_Y

P48

IO_VREF

P47

IO_VREF_L51N_Y

P46

IO_L51P_Y

P45

GND

P44

VCCO

P43

VCCINT

P42

IO_L52N_YY

P41

IO_L52P_YY

P40

IO_VREF

P39

IO_L53N_Y

P38

IO_L53P_Y

P37

GND

P36

IO_VREF_L54N_Y

P35

IO_L54P_Y

P34

IO_L55N_Y

P33

IO_VREF_L55P_Y

P32

VCCINT

P31

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

P30

VCCO

P29

GND

P28

IO_L56N_YY

P27

IO_L56P_YY

P26

IO_VREF

P25

VCCO

P24

IO_L57N_Y

P23

IO_VREF_L57P_Y

P22

GND

P21

IO_L58N_Y

P20

IO_L58P_Y

P19

IO_VREF

P18

IO_L59N_YY

P17

IO_L59P_YY

P16

VCCINT

P15

VCCO

P14

GND

P13

IO_L60N_Y

P12

IO_VREF_L60P_Y

P11

IO_VREF

P10

IO_L61N_Y

IO_VREF_L61P_Y

GND

IO_L62N_Y

IO_L62P_Y

IO_VREF_L63N_Y

IO_L63P_Y

TMS

GND

Notes:
1.

REF

or I/O option only in the XCV1000E; otherwise, I/O

option only.

Table 8: HQ240 -- XCV600E, XCV1000E

Pin #

Pin Description

Bank

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

HQ240 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

P92

P93

IO _DLL_L40P

P89

P87

IO _DLL_L40N

P210

P209

IO _DLL_L6P

P213

P215

IO _DLL_L6N

IO LVDS

Total Pairs: 64, Asynchronous Output Pairs: 53

P236

P237

VREF

P234

P235

P228

P229

VREF

P223

P224

P220

P221

P217

P218

VREF

P209

P215

IO_LVDS_DLL

P205

P206

VREF

P202

P203

P199

P200

P194

P195

VREF

P191

P192

VREF

P188

P189

P186

P187

VREF

P184

P185

P178

P177

DIN, D0

P174

P173

P171

P170

VREF

P168

P167

P163

P162

P160

P159

P157

P156

P155

P154

VREF

P153

P152

P145

P144

D4, VREF

P142

P141

P139

P138

P134

P133

VREF

P131

P130

VREF

P128

P127

P126

P125

VREF

P124

P123

INIT

P118

P117

P114

P113

P111

P110

VREF

P108

P107

VREF

P103

P102

P100

P99

P97

P96

VREF

P95

P94

VREF

P93

P87

IO_LVDS_DLL

P84

P82

VREF

P79

P78

P74

P73

VREF

P71

P70

VREF

P68

P67

P66

P65

VREF

P64

P63

Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

BG352 Ball Grid Array Packages

XCV100E, XCV200E, and XCV300E devices in BG352 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V

REF

, it can be used as general I/O. Immedi-

ately following

Table 10

, see

Table 11

for Differential Pair

information.

P56

P57

P52

P53

P49

P50

VREF

P46

P47

VREF

P41

P42

P38

P39

P35

P36

VREF

P33

P34

VREF

P27

P28

P23

P24

VREF

P20

P21

P17

P18

P12

P13

VREF

P10

VREF

Note 1: AO in the XCV600E.

Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E

Pair

Bank

Pin

Other

Functions

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

D22

C23

B24

C22

IO_VREF_0_L0N_YY

D21

IO_L0P_YY

B23

A24

IO_L1N_YY

A23

IO_L1P_YY

D20

IO_VREF_0_L2N_YY

C21

IO_L2P_YY

B22

B21

C20

IO_L3N

B20

IO_L3P

A21

D18

IO_VREF_0_L4N_YY

C19

IO_L4P_YY

B19

IO_L5N_YY

D17

IO_L5P_YY

C18

B18

IO_L6N

C17

IO_L6P

A18

D16

IO_L7N_Y

B17

IO_L7P_Y

C16

IO_VREF_0_L8N_Y

A16

IO_L8P_Y

D15

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

C15

B15

IO_LVDS_DLL_L9N

A15

GCK3

D14

GCK2

B14

IO_LVDS_DLL_L9P

A13

B13

IO_L10N

C13

IO_L10P

A12

IO_L11N_Y

B12

IO_VREF_1_L11P_Y

C12

IO_L12N_Y

A11

IO_L12P_Y

B11

B10

IO_L13N

C11

IO_L13P

D11

IO_L14N_YY

IO_L14P_YY

C10

IO_L15N_YY

IO_VREF_1_L15P_YY

IO_L16N _Y

IO_L16P _Y

IO_L17N_YY

IO_VREF_1_L17P_YY

IO_L18N_YY

IO_L18P_YY

IO_L19N_YY

IO_VREF_1_L19P_YY

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_WRITE_L20N_YY

IO_CS_L20P_YY

IO_DOUT_BUSY_L21P_YY

IO_DIN_D0_L21N_YY

IO_VREF_2_L22P_YY

IO_L22N_YY

IO_L23P_YY

IO_L23N_YY

IO_VREF_2_L24P_Y

IO_L24N_Y

IO_L25P

IO_L25N

IO_VREF_2_L26P _Y

IO_D1_L26N _Y

IO_D2_L27P_YY

IO_L27N_YY

IO_L28P

IO_L28N

IO_L29P_YY

IO_L29N_YY

IO_VREF_2_L30P _Y

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_D3_L30N _Y

IO_L31P

IO_L31N

IO_L32P_YY

IO_L32N_YY

IO_L33P

IO_L33N

IO_D4_L34P _Y

IO_VREF_3_L34N _Y

IO_L35P_YY

IO_L35N_YY

IO_L36P

IO_L36N

IO_L37P_YY

IO_D5_L37N_YY

IO_D6_L38P _Y

IO_VREF_3_L38N _Y

IO_L39P _Y

IO_L39N _Y

AA1

IO_L40P_Y

AA2

IO_VREF_3_L40N_Y

IO_L41P_YY

AC1

IO_L41N_YY

AB2

AA3

IO_L42P_YY

AA4

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_VREF_3_L42N_YY

AC2

AB3

AD1

AB4

IO_D7_L43P_YY

AC3

IO_INIT_L43N_YY

AD2

IO_L44P_YY

AC5

IO_L44N_YY

AD4

AE3

AD5

AC6

IO_VREF_4_L45P_YY

AE4

IO_L45N_YY

AF3

AF4

IO_L46P_YY

AC7

IO_L46N_YY

AD6

IO_VREF_4_L47P_YY

AE5

IO_L47N_YY

AE6

AD7

AE7

IO_L48P

AF6

IO_L48N

AC9

AD8

IO_VREF_4_L49P_YY

AE8

IO_L49N_YY

AF7

IO_L50P_YY

AD9

IO_L50N_YY

AE9

AD10

IO_L51P

AF9

IO_L51N

AC11

AE10

IO_L52P_Y

AD11

IO_L52N_Y

AE11

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_VREF_4_L53P_Y

AC12

IO_L53N_Y

AD12

IO_L54P

AE12

IO_L54N

AF12

AD13

IO_LVDS_DLL_L55P

AC13

GCK0

AE13

GCK1

AF14

IO_LVDS_DLL_L55N

AD14

AF15

AE15

IO_L56P_Y

AD15

IO_VREF_5_L56N_Y

AC15

IO_L57P_Y

AE16

IO_L57N_Y

AE17

AD16

IO_L58P

AC16

IO_L58N

AF18

AE18

IO_L59P_YY

AD17

IO_L59N_YY

AC17

IO_L60P_YY

AD18

IO_VREF_5_L60N_YY

AC18

IO_L61P _Y

AF20

IO_L61N _Y

AE20

AD19

AC19

AF21

IO_L62P_YY

AE21

IO_VREF_5_L62N_YY

AD20

IO_L63P_YY

AF23

IO_L63N_YY

AE22

AD21

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_L64P_YY

AC21

IO_VREF_5_L64N_YY

AE23

AD22

AF24

AC22

IO_L65N_YY

AC24

IO_L65P_YY

AD25

AB24

AA23

AC25

IO_VREF_6_L66N_YY

AD26

IO_L66P_YY

AC26

Y23

IO_L67N_YY

AA24

IO_L67P_YY

AB25

IO_VREF_6_L68N_Y

AA25

IO_L68P_Y

Y24

Y25

AA26

IO_L69N

V23

IO_L69P

W24

W25

IO_VREF_6_L70N _Y

Y26

IO_L70P _Y

U23

IO_L71N_YY

V25

IO_L71P_YY

U24

V26

IO_L72N

T23

IO_L72P

U25

T24

IO_L73N_YY

T25

IO_L73P_YY

T26

IO_VREF_6_L74N _Y

R24

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L74P _Y

R25

IO_L75N

R26

IO_L75P

P24

P23

N26

IO_L76N_YY

N25

IO_L76P_YY

N24

M26

IO_L77N

M25

IO_L77P

M24

IO_L78N _Y

M23

IO_VREF_7_L78P _Y

L26

IO_L79N_YY

K25

IO_L79P_YY

L24

L23

IO_L80N

J26

IO_L80P

J25

K24

IO_L81N_YY

K23

IO_L81P_YY

H25

IO_L82N _Y

J23

IO_VREF_7_L82P _Y

G26

IO_L83N _Y

G25

IO_L83P _Y

H24

H23

F26

F25

IO_L84N_Y

G24

IO_VREF_7_L84P_Y

D26

IO_L85N_YY

E25

IO_L85P_YY

F24

F23

IO_L86N_YY

D25

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_VREF_7_L86P_YY

E24

C26

E23

D24

C25

TDI

TDO

CCLK

TCK

C24

TMS

D23

PROGRAM

AC4

DONE

AD3

DXN

AD23

DXP

AE24

AC23

AD24

AB23

VCCINT

A20

VCCINT

B16

VCCINT

C14

VCCINT

D12

VCCINT

D10

VCCINT

AC10

VCCINT

AF11

VCCINT

AE14

VCCINT

AF16

VCCINT

AE19

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCINT

V24

VCCINT

R23

VCCINT

P25

VCCINT

L25

VCCINT

J24

VCCO

D19

VCCO

B25

VCCO

A17

VCCO

D13

VCCO

A10

VCCO

AF10

VCCO

AE2

VCCO

AC8

VCCO

AF17

VCCO

AC20

VCCO

AC14

VCCO

AE25

VCCO

W23

VCCO

U26

VCCO

N23

VCCO

K26

VCCO

G23

GND

A26

GND

A25

GND

A22

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

GND

A19

GND

A14

GND

B26

GND

E26

GND

H26

GND

P26

GND

W26

GND

AB26

GND

AB1

GND

AE26

GND

AE1

GND

AF26

GND

AF25

GND

AF22

GND

AF19

GND

AF13

GND

AF8

GND

AF5

GND

AF2

GND

AF1

Notes:
1.

No Connect in

the XCV100E.

REF

or I/O option only in the XCV200E and XCV300E;

otherwise, I/O option only.

Table 10: BG352 -- XCV100E, XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

BG352 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A
check (

) in the AO column indicates that the pin pair can be

used as an asynchronous output for all devices provided in
this package. Pairs with a note number in the AO column
are device dependent. They can have asynchronous out-
puts if the pin pair are in the same CLB row and column in
the device. Numbers in this column refer to footnotes that
indicate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates alter-
native function(s) not available when the pair is used as a
differential pair or differential clock

Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

AE13

AC13

IO LVDS 55

AF14

AD14

IO LVDS 55

B14

A13

IO LVDS 9

D14

A15

IO LVDS 9

IO LVDS

Total Outputs: 87, Asynchronous Output Pairs: 43

B23

D21

VREF_0

D20

A23

B22

C21

VREF_0

A21

B20

B19

C19

VREF_0

C18

D17

A18

C17

C16

B17

D15

A16

VREF_0

A13

A15

GCLK LVDS 3/2

A12

C13

C12

B12

VREF_1

B11

A11

D11

C11

C10

VREF_1

DIN_D0

VREF_2

VREF_3

AA2

VREF_3

AC1

AB2

AA4

AC2

VREF_3

AC3

AD2

INIT

AC5

AD4

AE4

AF3

VREF_4

AC7

AD6

AE5

AE6

VREF_4

AF6

AC9

AE8

AF7

VREF_4

AD9

AE9

AF9

AC11

AD11

AE11

AC12

AD12

VREF_4

AE12

AF12

Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

BG432 Ball Grid Array Packages

XCV300E, XCV400E, and XCV600E devices in BG432 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V

REF

, it can be used as general I/O. Immedi-

ately following

Table 12

, see

Table 13

for Differential Pair

information.

AC13

AD14

GCLK LVDS 1/0

AD15

AC15

VREF_5

AE16

AE17

AC16

AF18

AD17

AC17

AD18

AC18

VREF_5

AF20

AE20

AE21

AD20

VREF_5

AF23

AE22

AC21

AE23

VREF_5

AD25

AC24

AC26

AD26

VREF_6

AB25

AA24

Y24

AA25

VREF_6

W24

V23

U23

Y26

VREF_6

U24

V25

U25

T23

T26

T25

R25

R24

VREF_6

P24

R26

N24

N25

M24

M25

L26

M23

VREF_7

L24

K25

J25

J26

H25

K23

G26

J23

VREF_7

H24

G25

D26

G24

VREF_7

F24

E25

E24

D25

VREF_7

Notes:
1.

AO in the XCV100E.

AO in the XCV200E.

Table 11: BG352 Differential Pin Pair Summary
XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

GCK3

D17

A22

A26

B20

C23

C28

IO_L0N_Y

B29

IO_L0P_Y

D27

IO_L1N_YY

B28

IO_L1P_YY

C27

IO_VREF_L2N_YY

D26

IO_L2P_YY

A28

IO_L3N_Y

B27

IO_L3P_Y

C26

IO_L4N_YY

D25

IO_L4P_YY

A27

IO_VREF_L5N_YY

D24

IO_L5P_YY

C25

IO_L6N_Y

B25

IO_L6P_Y

D23

IO_VREF_L7N_Y

C24

IO_L7P_Y

B24

IO_VREF_L8N_YY

D22

IO_L8P_YY

A24

IO_L9N_YY

C22

IO_L9P_YY

B22

IO_L10N_YY

C21

IO_L10P_YY

D20

IO_L11N_YY

B21

IO_L11P_YY

C20

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L12N_YY

A20

IO_L12P_YY

D19

IO_VREF_L13N_YY

B19

IO_L13P_YY

A19

IO_L14N_Y

B18

IO_L14P_Y

D18

IO_VREF_L15N_Y

C18

IO_L15P_Y

B17

IO_LVDS_DLL_L16N

C17

GCK2

A16

A12

B11

C16

IO_LVDS_DLL_L16P

B16

IO_L17N_Y

A15

IO_VREF_L17P_Y

B15

IO_L18N_Y

C15

IO_L18P_Y

D15

IO_L19N_YY

B14

IO_VREF_L19P_YY

A13

IO_L20N_YY

B13

IO_L20P_YY

D14

IO_L21N_YY

C13

IO_L21P_YY

B12

IO_L22N_YY

D13

IO_L22P_YY

C12

IO_L23N_YY

D12

IO_L23P_YY

C11

IO_L24N_YY

B10

IO_VREF_L24P_YY

C10

IO_L25N_Y

IO_VREF_L25P_Y

D10

IO_L26N_Y

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L26P_Y

IO_L27N_YY

IO_VREF_L27P_YY

IO_L28N_YY

IO_L28P_YY

IO_L29N_Y

IO_L29P_Y

IO_L30N_YY

IO_VREF_L30P_YY

IO_L31N_YY

IO_L31P_YY

IO_L32N_Y

IO_L32P_Y

IO_WRITE_L33N_YY

IO_CS_L33P_YY

IO_DOUT_BUSY_L34P_YY

IO_DIN_D0_L34N_YY

IO_L35P

IO_L35N

IO_L36P_Y

IO_L36N_Y

IO_VREF_L37P_Y

IO_L37N_Y

IO_L38P

IO_L38N

IO_L39P_Y

IO_L39N_Y

IO_VREF_L40P_YY

IO_L40N_YY

IO_L41P_Y

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L41N_Y

IO_VREF_L42P_Y

IO_L42N_Y

IO_VREF_L43P_YY

IO_D1_L43N_YY

IO_D2_L44P_YY

IO_L44N_YY

IO_L45P_Y

IO_L45N_Y

IO_L46P_Y

IO_L46N_Y

IO_L47P_Y

IO_L47N_Y

IO_VREF_L48P_YY

IO_D3_L48N_YY

IO_L49P_Y

IO_L49N_Y

IO_VREF_L50P_Y

IO_L50N_Y

IO_L51P_YY

IO_L51N_YY

AA2

AC2

AE2

IO_L52P_Y

IO_VREF_L52N_Y

IO_L53P_Y

IO_L53N_Y

IO_D4_L54P_YY

IO_VREF_L54N_YY

IO_L55P_Y

IO_L55N_Y

IO_L56P_Y

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L56N_Y

IO_L57P_Y

IO_L57N_Y

IO_L58P_YY

AA3

IO_D5_L58N_YY

AB1

IO_D6_L59P_YY

AB3

IO_VREF_L59N_YY

AB4

IO_L60P_Y

AD1

IO_VREF_L60N_Y

AC3

IO_L61P_Y

AC4

IO_L61N_Y

AD2

IO_L62P_YY

AD3

IO_VREF_L62N_YY

AD4

IO_L63P_Y

AF2

IO_L63N_Y

AE3

IO_L64P

AE4

IO_L64N

AG1

IO_L65P_Y

AG2

IO_VREF_L65N_Y

AF3

IO_L66P_Y

AF4

IO_L66N_Y

AH1

IO_L67P

AH2

IO_L67N

AG3

IO_D7_L68P_YY

AG4

IO_INIT_L68N_YY

AJ2

GCK0

AL16

AH10

AJ11

AK7

AL12

AL15

IO_L69P_YY

AJ4

IO_L69N_YY

AK3

IO_L70P_Y

AH5

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L70N_Y

AK4

IO_L71P_YY

AJ5

IO_L71N_YY

AH6

IO_VREF_L72P_YY

AL4

IO_L72N_YY

AK5

IO_L73P_Y

AJ6

IO_L73N_Y

AH7

IO_L74P_YY

AL5

IO_L74N_YY

AK6

IO_VREF_L75P_YY

AJ7

IO_L75N_YY

AL6

IO_L76P_Y

AH9

IO_L76N_Y

AJ8

IO_VREF_L77P_Y

AK8

IO_L77N_Y

AJ9

IO_VREF_L78P_YY

AL8

IO_L78N_YY

AK9

IO_L79P_YY

AK10

IO_L79N_YY

AL10

IO_L80P_YY

AH12

IO_L80N_YY

AK11

IO_L81P_YY

AJ12

IO_L81N_YY

AK12

IO_L82P_YY

AH13

IO_L82N_YY

AJ13

IO_VREF_L83P_YY

AL13

IO_L83N_YY

AK14

IO_L84P_Y

AH14

IO_L84N_Y

AJ14

IO_VREF_L85P_Y

AK15

IO_L85N_Y

AJ15

IO_LVDS_DLL_L86P

AH15

GCK1

AK16

AH20

AJ19

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

AJ23

AJ24

IO_LVDS_DLL_L86N

AL17

IO_L87P_Y

AK17

IO_VREF_L87N_Y

AJ17

IO_L88P_Y

AH17

IO_L88N_Y

AK18

IO_L89P_YY

AL19

IO_VREF_L89N_YY

AJ18

IO_L90P_YY

AH18

IO_L90N_YY

AL20

IO_L91P_YY

AK20

IO_L91N_YY

AH19

IO_L92P_YY

AJ20

IO_L92N_YY

AK21

IO_L93P_YY

AJ21

IO_L93N_YY

AL22

IO_L94P_YY

AJ22

IO_VREF_L94N_YY

AK23

IO_L95P_Y

AH22

IO_VREF_L95N_Y

AL24

IO_L96P_Y

AK24

IO_L96N_Y

AH23

IO_L97P_YY

AK25

IO_VREF_L97N_YY

AJ25

IO_L98P_YY

AL26

IO_L98N_YY

AK26

IO_L99P_Y

AH25

IO_L99N_Y

AL27

IO_L100P_YY

AJ26

IO_VREF_L100N_YY

AK27

IO_L101P_YY

AH26

IO_L101N_YY

AL28

IO_L102P_Y

AJ27

IO_L102N_Y

AK28

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

AA30

AC30

AD29

U31

W28

IO_L103N_YY

AJ30

IO_L103P_YY

AH30

IO_L104N

AG28

IO_L104P

AH31

IO_L105N_Y

AG29

IO_L105P_Y

AG30

IO_VREF_L106N_Y

AF28

IO_L106P_Y

AG31

IO_L107N

AF29

IO_L107P

AF30

IO_L108N_Y

AE28

IO_L108P_Y

AF31

IO_VREF_L109N_YY

AE30

IO_L109P_YY

AD28

IO_L110N_Y

AD30

IO_L110P_Y

AD31

IO_VREF_L111N_Y

AC28

IO_L111P_Y

AC29

IO_VREF_L112N_YY

AB28

IO_L112P_YY

AB29

IO_L113N_YY

AB31

IO_L113P_YY

AA29

IO_L114N_Y

Y28

IO_L114P_Y

Y29

IO_L115N_Y

Y30

IO_L115P_Y

Y31

IO_L116N_Y

W29

IO_L116P_Y

W30

IO_VREF_L117N_YY

V28

IO_L117P_YY

V29

IO_L118N_Y

V30

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L118P_Y

U29

IO_VREF_L119N_Y

U28

IO_L119P_Y

U30

T30

C30

H29

H31

L29

M31

R28

IO_L120N_YY

T31

IO_L120P_YY

R29

IO_L121N_Y

R30

IO_VREF_L121P_Y

R31

IO_L122N_Y

P29

IO_L122P_Y

P28

IO_L123N_YY

P30

IO_VREF_L123P_YY

N30

IO_L124N_Y

N28

IO_L124P_Y

N31

IO_L125N_Y

M29

IO_L125P_Y

M28

IO_L126N_Y

M30

IO_L126P_Y

L30

IO_L127N_YY

K31

IO_L127P_YY

K30

IO_L128N_YY

K28

IO_VREF_L128P_YY

J30

IO_L129N_Y

J29

IO_VREF_L129P_Y

J28

IO_L130N_Y

H30

IO_L130P_Y

G30

IO_L131N_YY

H28

IO_VREF_L131P_YY

F31

IO_L132N_Y

G29

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L132P_Y

G28

IO_L133N

E31

IO_L133P

E30

IO_L134N_Y

F29

IO_VREF_L134P_Y

F28

IO_L135N_Y

D31

IO_L135P_Y

D30

IO_L136N

E29

IO_L136P

E28

CCLK

DONE

AH4

DXN

AH27

DXP

AK29

AH28

AH29

AJ28

PROGRAM

AH3

TCK

D28

TDI

TDO

TMS

D29

VCCINT

A10

VCCINT

A17

VCCINT

B23

VCCINT

B26

VCCINT

C14

VCCINT

C19

VCCINT

F30

VCCINT

K29

VCCINT

N29

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VCCINT

T29

VCCINT

W31

VCCINT

AB2

VCCINT

AB30

VCCINT

AE29

VCCINT

AF1

VCCINT

AH8

VCCINT

AH24

VCCINT

AJ10

VCCINT

AJ16

VCCINT

AK22

VCCINT

AK13

VCCINT

AK19

VCCO

A21

VCCO

C29

VCCO

D21

VCCO

A11

VCCO

D11

VCCO

AA1

VCCO

AA4

VCCO

AJ3

VCCO

AH11

VCCO

AL1

VCCO

AL11

VCCO

AH21

VCCO

AL21

VCCO

AJ29

VCCO

AA28

VCCO

AA31

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCO

AL31

VCCO

A31

VCCO

L28

VCCO

L31

GND

A14

GND

A18

GND

A23

GND

A25

GND

A29

GND

A30

GND

B30

GND

B31

GND

C31

GND

D16

GND

G31

GND

J31

GND

P31

GND

T28

GND

V31

GND

AC1

GND

AC31

GND

AE1

GND

AE31

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

GND

AH16

GND

AJ1

GND

AJ31

GND

AK1

GND

AK2

GND

AK30

GND

AK31

GND

AL2

GND

AL3

GND

AL7

GND

AL9

GND

AL14

GND

AL18

GND

AL23

GND

AL25

GND

AL29

GND

AL30

Notes:
1.

REF

or I/O option only in the XCV600E; otherwise, I/O

option only.

REF

or I/O option only in the XCV400E, XCV600E;

otherwise, I/O option only.

Table 12: BG432 -- XCV300E, XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

BG432 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also Vir-
tex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E

Pair

Bank

Other

Functions

Global Differential Clock

AL16

AH15

IO_DLL_L86P

AK16

AL17

IO_DLL_L86N

A16

B16

IO_DLL_L16P

D17

C17

IO_DLL_L16N

IO LVDS

Total Outputs: 137, Asynchronous Output Pairs: 63

D27

B29

C27

B28

A28

D26

VREF

C26

B27

A27

D25

C25

D24

VREF

D23

B25

B24

C24

VREF

A24

D22

VREF

B22

C22

D20

C21

C20

B21

D19

A20

A19

B19

VREF

D18

B18

B17

C18

VREF

B16

C17

IO_LVDS_DLL

B15

A15

VREF

D15

C15

A13

B14

VREF

D14

B13

B12

C13

C12

D13

C11

D12

C10

B10

VREF

D10

VREF

CS, WRITE

DIN, D0, BUSY

VREF

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E

Pair

Bank

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VREF

AA3

AB1

AB3

AB4

VREF

AD1

AC3

VREF

AC4

AD2

AD3

AD4

VREF

AF2

AE3

AE4

AG1

AG2

AF3

VREF

AF4

AH1

AH2

AG3

AG4

AJ2

INIT

AJ4

AK3

AH5

AK4

AJ5

AH6

AL4

AK5

VREF

AJ6

AH7

AL5

AK6

AJ7

AL6

VREF

AH9

AJ8

AK8

AJ9

VREF

AL8

AK9

VREF

AK10

AL10

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E

Pair

Bank

Other

Functions

AH12

AK11

AJ12

AK12

AH13

AJ13

AL13

AK14

VREF

AH14

AJ14

AK15

AJ15

VREF

AH15

AL17

IO_LVDS_DLL

AK17

AJ17

VREF

AH17

AK18

AL19

AJ18

VREF

AH18

AL20

AK20

AH19

AJ20

AK21

AJ21

AL22

AJ22

AK23

VREF

AH22

AL24

VREF

AK24

AH23

AK25

AJ25

VREF

AL26

AK26

AH25

AL27

100

AJ26

AK27

VREF

101

AH26

AL28

102

AJ27

AK28

103

AH30

AJ30

104

AH31

AG28

105

AG30

AG29

106

AG31

AF28

VREF

107

AF30

AF29

108

AF31

AE28

109

AD28

AE30

VREF

110

AD31

AD30

111

AC29

AC28

VREF

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E

Pair

Bank

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

BG560 Ball Grid Array Packages

XCV1000E, XCV1600E, and XCV2000E devices in BG560
Ball Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V

REF

, it can be used as general I/O. Immedi-

ately following

Table 14

, see

Table 15

for Differential Pair

information.

112

AB29

AB28

VREF

113

AA29

AB31

114

Y29

Y28

115

Y31

Y30

116

W30

W29

117

V29

V28

VREF

118

U29

V30

119

U30

U28

VREF

120

R29

T31

121

R31

R30

VREF

122

P28

P29

123

N30

P30

VREF

124

N31

N28

125

M28

M29

126

L30

M30

127

K30

K31

128

J30

K28

VREF

129

J28

J29

VREF

130

G30

H30

131

F31

H28

VREF

132

G28

G29

133

E30

E31

134

F28

F29

VREF

135

D30

D31

136

E28

E29

Notes:
1.

AO in the XCV300E, 600E.

AO in the XCV300E.

AO in the XCV400E, 600E.

AO in the XCV300E, 400E.

AO in the XCV600E.

Table 13: BG432 Differential Pin Pair Summary
XCV300E, XCV400E, XC600E

Pair

Bank

Other

Functions

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

GCK3

A17

A27

B25

C28

C30

D30

IO_L0N

E28

IO_VREF_L0P

D29

IO_L1N_YY

D28

IO_L1P_YY

A31

IO_VREF_L2N_YY

E27

IO_L2P_YY

C29

IO_L3N_Y

B30

IO_L3P_Y

D27

IO_L4N_YY

E26

IO_L4P_YY

B29

IO_VREF_L5N_YY

D26

IO_L5P_YY

C27

IO_L6N_Y

E25

IO_VREF_L6P_Y

A28

IO_L7N_Y

D25

IO_L7P_Y

C26

IO_VREF_L8N_Y

E24

IO_L8P_Y

B26

IO_L9N_Y

C25

IO_L9P_Y

D24

IO_VREF_L10N_YY

E23

IO_L10P_YY

A25

IO_L11N_YY

D23

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L11P_YY

B24

IO_L12N_Y

E22

IO_L12P_Y

C23

IO_L13N_YY

A23

IO_L13P_YY

D22

IO_VREF_L14N_YY

E21

IO_L14P_YY

B22

IO_L15N_Y

D21

IO_L15P_Y

C21

IO_L16N_YY

B21

IO_L16P_YY

E20

IO_VREF_L17N_YY

D20

IO_L17P_YY

C20

IO_L18N_Y

B20

IO_L18P_Y

E19

IO_L19N_Y

D19

IO_L19P_Y

C19

IO_VREF_L20N_Y

A19

IO_L20P_Y

D18

IO_LVDS_DLL_L21N

C18

IO_VREF

E18

GCK2

D17

E11

IO_LVDS_DLL_L21P

E17

IO_VREF_L22N_Y

C17

IO_L22P_Y

B17

IO_L23N_Y

B16

IO_VREF_L23P_Y

D16

IO_L24N_Y

E16

IO_L24P_Y

C16

IO_L25N_Y

A15

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_L25P_Y

C15

IO_L26N_YY

D15

IO_VREF_L26P_YY

E15

IO_L27N_YY

C14

IO_L27P_YY

D14

IO_L28N_Y

A13

IO_L28P_Y

E14

IO_L29N_YY

C13

IO_VREF_L29P_YY

D13

IO_L30N_YY

C12

IO_L30P_YY

E13

IO_L31N_Y

A11

IO_L31P_Y

D12

IO_L32N_YY

B11

IO_L32P_YY

C11

IO_L33N_YY

B10

IO_VREF_L33P_YY

D11

IO_L34N_Y

C10

IO_L34P_Y

IO_L35N_Y

IO_VREF_L35P_Y

D10

IO_L36N_Y

IO_L36P_Y

IO_L37N_Y

E10

IO_VREF_L37P_Y

IO_L38N_YY

IO_VREF_L38P_YY

IO_L39N_YY

IO_L39P_YY

IO_L40N_Y

IO_L40P_Y

IO_L41N_YY

IO_VREF_L41P_YY

IO_L42N_YY

IO_L42P_YY

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L43N_Y

IO_VREF_L43P_Y

IO_WRITE_L44N_YY

IO_CS_L44P_YY

IO_DOUT_BUSY_L45P_YY

IO_DIN_D0_L45N_YY

IO_L46P_Y

IO_VREF_L46N_Y

IO_L47P_Y

IO_L47N_Y

IO_VREF_L48P_Y

IO_L48N_Y

IO_L49P_Y

IO_L49N_Y

IO_L50P_Y

IO_L50N_Y

IO_VREF_L51P_YY

IO_L51N_YY

IO_L52P_Y

IO_VREF_L52N_Y

IO_L53P_Y

IO_L53N_Y

IO_VREF_L54P_Y

IO_L54N_Y

IO_L55P_Y

IO_L55N_Y

IO_VREF_L56P_YY

IO_D1_L56N_YY

IO_D2_L57P_YY

IO_L57N_YY

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_L58P_Y

IO_L58N_Y

IO_L59P_Y

IO_L59N_Y

IO_VREF_L60P_Y

IO_L60N_Y

IO_L61P_Y

IO_L61N_Y

IO_L62P_Y

IO_L62N_Y

IO_VREF_L63P_YY

IO_D3_L63N_YY

IO_L64P_Y

IO_L64N_Y

IO_L65P_Y

IO_L65N_Y

IO_VREF_L66P_Y

IO_L66N_Y

IO_L67P_Y

IO_VREF_L67N_Y

IO_L68P_YY

IO_L68N_YY

AE3

AF3

AH3

AK3

IO_VREF_L69P_Y

IO_L69N_Y

IO_L70P_Y

IO_VREF_L70N_Y

IO_L71P_Y

IO_L71N_Y

IO_L72P_Y

IO_L72N_Y

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_D4_L73P_YY

IO_VREF_L73N_YY

IO_L74P_Y

IO_L74N_Y

IO_L75P_Y

AA1

IO_L75N_Y

IO_L76P_Y

AA3

IO_VREF_L76N_Y

AA4

IO_L77P_Y

AB3

IO_L77N_Y

AA5

IO_L78P_Y

AC1

IO_L78N_Y

AB4

IO_L79P_YY

AC3

IO_D5_L79N_YY

AB5

IO_D6_L80P_YY

AC4

IO_VREF_L80N_YY

AD3

IO_L81P_Y

AE1

IO_L81N_Y

AC5

IO_L82P_Y

AD4

IO_VREF_L82N_Y

AF1

IO_L83P_Y

AF2

IO_L83N_Y

AD5

IO_L84P_Y

AG2

IO_VREF_L84N_Y

AE4

IO_L85P_YY

AH1

IO_VREF_L85N_YY

AE5

IO_L86P_Y

AF4

IO_L86N_Y

AJ1

IO_L87P_Y

AJ2

IO_L87N_Y

AF5

IO_L88P_Y

AG4

IO_VREF_L88N_Y

AK2

IO_L89P_Y

AJ3

IO_L89N_Y

AG5

IO_L90P_Y

AL1

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_VREF_L90N_Y

AH4

IO_D7_L91P_YY

AJ4

IO_INIT_L91N_YY

AH5

GCK0

AL17

AJ8

AJ11

AK6

AK9

IO_L92P_YY

AL4

IO_L92N_YY

AJ6

IO_L93P_Y

AK5

IO_VREF_L93N_Y

AN3

IO_L94P_YY

AL5

IO_L94N_YY

AJ7

IO_VREF_L95P_YY

AM4

IO_L95N_YY

AM5

IO_L96P_Y

AK7

IO_L96N_Y

AL6

IO_L97P_YY

AM6

IO_L97N_YY

AN6

IO_VREF_L98P_YY

AL7

IO_L98N_YY

AJ9

IO_L99P_Y

AN7

IO_VREF_L99N_Y

AL8

IO_L100P_Y

AM8

IO_L100N_Y

AJ10

IO_VREF_L101P_Y

AL9

IO_L101N_Y

AM9

IO_L102P_Y

AK10

IO_L102N_Y

AN9

IO_VREF_L103P_YY

AL10

IO_L103N_YY

AM10

IO_L104P_YY

AL11

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L104N_YY

AJ12

IO_L105P_Y

AN11

IO_L105N_Y

AK12

IO_L106P_YY

AL12

IO_L106N_YY

AM12

IO_VREF_L107P_YY

AK13

IO_L107N_YY

AL13

IO_L108P_Y

AM13

IO_L108N_Y

AN13

IO_L109P_YY

AJ14

IO_L109N_YY

AK14

IO_VREF_L110P_YY

AM14

IO_L110N_YY

AN15

IO_L111P_Y

AJ15

IO_L111N_Y

AK15

IO_L112P_Y

AL15

IO_L112N_Y

AM16

IO_VREF_L113P_Y

AL16

IO_L113N_Y

AJ16

IO_L114P_Y

AK16

IO_VREF_L114N_Y

AN17

IO_LVDS_DLL_L115P

AM17

GCK1

AJ17

AL25

AL28

AL30

AN28

IO_LVDS_DLL_L115N

AM18

IO_VREF

AL18

IO_L116P_Y

AK18

IO_VREF_L116N_Y

AJ18

IO_L117P_Y

AN19

IO_L117N_Y

AL19

IO_L118P_Y

AK19

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_L118N_Y

AM20

IO_L119P_YY

AJ19

IO_VREF_L119N_YY

AL20

IO_L120P_YY

AN21

IO_L120N_YY

AL21

IO_L121P_Y

AJ20

IO_L121N_Y

AM22

IO_L122P_YY

AK21

IO_VREF_L122N_YY

AN23

IO_L123P_YY

AJ21

IO_L123N_YY

AM23

IO_L124P_Y

AK22

IO_L124N_Y

AM24

IO_L125P_YY

AL23

IO_L125N_YY

AJ22

IO_L126P_YY

AK23

IO_VREF_L126N_YY

AL24

IO_L127P_Y

AN26

IO_L127N_Y

AJ23

IO_L128P_Y

AK24

IO_VREF_L128N_Y

AM26

IO_L129P_Y

AM27

IO_L129N_Y

AJ24

IO_L130P_Y

AL26

IO_VREF_L130N_Y

AK25

IO_L131P_YY

AN29

IO_VREF_L131N_YY

AJ25

IO_L132P_YY

AK26

IO_L132N_YY

AM29

IO_L133P_Y

AM30

IO_L133N_Y

AJ26

IO_L134P_YY

AK27

IO_VREF_L134N_YY

AL29

IO_L135P_YY

AN31

IO_L135N_YY

AJ27

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L136P_Y

AM31

IO_VREF_L136N_Y

AK28

AE33

AF31

AJ32

AL33

IO_L137N_YY

AH29

IO_L137P_YY

AJ30

IO_L138N_Y

AK31

IO_VREF_L138P_Y

AH30

IO_L139N_Y

AG29

IO_L139P_Y

AJ31

IO_VREF_L140N_Y

AK32

IO_L140P_Y

AG30

IO_L141N_Y

AH31

IO_L141P_Y

AF29

IO_L142N_Y

AH32

IO_L142P_Y

AF30

IO_VREF_L143N_YY

AE29

IO_L143P_YY

AH33

IO_L144N_Y

AG33

IO_VREF_L144P_Y

AE30

IO_L145N_Y

AD29

IO_L145P_Y

AF32

IO_VREF_L146N_Y

AE31

IO_L146P_Y

AD30

IO_L147N_Y

AE32

IO_L147P_Y

AC29

IO_VREF_L148N_YY

AD31

IO_L148P_YY

AC30

IO_L149N_YY

AB29

IO_L149P_YY

AC31

IO_L150N_Y

AC33

IO_L150P_Y

AB30

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_L151N_Y

AB31

IO_L151P_Y

AA29

IO_VREF_L152N_Y

AA30

IO_L152P_Y

AA31

IO_L153N_Y

AA32

IO_L153P_Y

Y29

IO_L154N_Y

AA33

IO_L154P_Y

Y30

IO_VREF_L155N_YY

Y32

IO_L155P_YY

W29

IO_L156N_Y

W30

IO_L156P_Y

W31

IO_L157N_Y

W33

IO_L157P_Y

V30

IO_VREF_L158N_Y

V29

IO_L158P_Y

V31

IO_L159N_Y

V32

IO_VREF_L159P_Y

U33

U29

E30

F29

F33

G30

K30

IO_L160N_YY

U31

IO_L160P_YY

U32

IO_VREF_L161N_Y

T32

IO_L161P_Y

T30

IO_L162N_Y

T29

IO_VREF_L162P_Y

T31

IO_L163N_Y

R33

IO_L163P_Y

R31

IO_L164N_Y

R30

IO_L164P_Y

R29

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L165N_YY

P32

IO_VREF_L165P_YY

P31

IO_L166N_Y

P30

IO_L166P_Y

P29

IO_L167N_Y

M32

IO_L167P_Y

N31

IO_L168N_Y

N30

IO_VREF_L168P_Y

L33

IO_L169N_Y

M31

IO_L169P_Y

L32

IO_L170N_Y

M30

IO_L170P_Y

L31

IO_L171N_YY

M29

IO_L171P_YY

J33

IO_L172N_YY

L30

IO_VREF_L172P_YY

K31

IO_L173N_Y

L29

IO_L173P_Y

H33

IO_L174N_Y

J31

IO_VREF_L174P_Y

H32

IO_L175N_Y

K29

IO_L175P_Y

H31

IO_L176N_Y

J30

IO_VREF_L176P_Y

G32

IO_L177N_YY

J29

IO_VREF_L177P_YY

G31

IO_L178N_Y

E33

IO_L178P_Y

E32

IO_L179N_Y

H29

IO_L179P_Y

F31

IO_L180N_Y

D32

IO_VREF_L180P_Y

E31

IO_L181N_Y

G29

IO_L181P_Y

C33

IO_L182N_Y

F30

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

IO_VREF_L182P_Y

D31

CCLK

DONE

AJ5

DXN

AK29

DXP

AJ28

AJ29

AK30

AN32

PROGRAM

AM1

TCK

E29

TDI

TDO

TMS

B33

C31

AC2

AK4

AL3

VCCINT

A21

VCCINT

B12

VCCINT

B14

VCCINT

B18

VCCINT

B28

VCCINT

C22

VCCINT

C24

VCCINT

E12

VCCINT

H30

VCCINT

K32

VCCINT

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCINT

N29

VCCINT

N33

VCCINT

U30

VCCINT

Y31

VCCINT

AB2

VCCINT

AB32

VCCINT

AD2

VCCINT

AD32

VCCINT

AG3

VCCINT

AG31

VCCINT

AJ13

VCCINT

AK8

VCCINT

AK11

VCCINT

AK17

VCCINT

AK20

VCCINT

AL14

VCCINT

AL22

VCCINT

AL27

VCCINT

AN25

VCCO

A22

VCCO

A26

VCCO

A30

VCCO

B19

VCCO

B32

VCCO

A10

VCCO

A16

VCCO

B13

VCCO

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VCCO

AA2

VCCO

AD1

VCCO

AK1

VCCO

AL2

VCCO

AN4

VCCO

AN8

VCCO

AN12

VCCO

AM2

VCCO

AM15

VCCO

AL31

VCCO

AM21

VCCO

AN18

VCCO

AN24

VCCO

AN30

VCCO

W32

VCCO

AB33

VCCO

AF33

VCCO

AK33

VCCO

AM32

VCCO

C32

VCCO

D33

VCCO

K33

VCCO

N32

VCCO

T33

GND

A12

GND

A14

GND

A18

GND

A20

GND

A24

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

GND

A29

GND

A32

GND

A33

GND

B15

GND

B23

GND

B27

GND

B31

GND

F32

GND

G33

GND

J32

GND

M33

GND

P33

GND

R32

GND

V33

GND

Y33

GND

AB1

GND

AC32

GND

AD33

GND

AE2

GND

AG1

GND

AG32

GND

AH2

GND

AJ33

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

GND

AL32

GND

AM3

GND

AM7

GND

AM11

GND

AM19

GND

AM25

GND

AM28

GND

AM33

GND

AN1

GND

AN2

GND

AN5

GND

AN10

GND

AN14

GND

AN16

GND

AN20

GND

AN22

GND

AN27

GND

AN33

Notes:
1.

REF

or I/O option only in the XCV2000E; otherwise, I/O

option only.

REF

or I/O option only in the XCV1600E & 2000E;

otherwise, I/O option only.

REF

or I/O option only in the XCV1000E, 1600E, & 2000E;

otherwise, I/O option only.

REF

or I/O option only in the XCV600E, 1000E, 1600E, &

2000E; otherwise, I/O option only.

Table 14: BG560 -- XCV400E, XCV600E, XCV1000E,
XCV1600E, XCV2000E

Bank

Pin Description

Pin#

See Note

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

BG560 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

AL17

AM17

IO_DLL_L15P

AJ17

AM18

IO_DLL_L15N

D17

E17

IO_DLL_L21P

A17

C18

IO_DLL_L21N

IO LVDS

Total Outputs: 183, Asynchronous Outputs: 87

D29

E28

VREF

A31

D28

C29

E27

VREF

D27

B30

B29

E26

C27

D26

VREF

A28

E25

VREF

C26

D25

B26

E24

VREF

D24

C25

A25

E23

VREF

B24

D23

C23

E22

D22

A23

B22

E21

VREF

C21

D21

E20

B21

C20

D20

VREF

E19

B20

C19

D19

D18

A19

VREF

E17

C18

IO_LVDS_DLL

B17

C17

VREF

D16

B16

VREF

C16

E16

C15

A15

E15

D15

VREF

D14

C14

E14

A13

D13

C13

VREF

E13

C12

D12

A11

C11

B11

D11

B10

VREF

C10

D10

VREF

E10

VREF

DIN, D0

VREF

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

VREF

AA1

AA3

AA4

VREF

AB3

AA5

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

AC1

AB4

AC3

AB5

AC4

AD3

VREF

AE1

AC5

AD4

AF1

VREF

AF2

AD5

AG2

AE4

VREF

AH1

AE5

VREF

AF4

AJ1

AJ2

AF5

AG4

AK2

VREF

AJ3

AG5

AL1

AH4

VREF

AJ4

AH5

INIT

AL4

AJ6

AK5

AN3

VREF

AL5

AJ7

AM4

AM5

VREF

AK7

AL6

AM6

AN6

AL7

AJ9

VREF

AN7

AL8

VREF

100

AM8

AJ10

101

AL9

AM9

VREF

102

AK10

AN9

103

AL10

AM10

VREF

104

AL11

AJ12

105

AN11

AK12

106

AL12

AM12

107

AK13

AL13

VREF

108

AM13

AN13

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

109

AJ14

AK14

110

AM14

AN15

VREF

111

AJ15

AK15

112

AL15

AM16

113

AL16

AJ16

VREF

114

AK16

AN17

VREF

115

AM17

AM18

IO_LVDS_DLL

116

AK18

AJ18

VREF

117

AN19

AL19

118

AK19

AM20

119

AJ19

AL20

VREF

120

AN21

AL21

121

AJ20

AM22

122

AK21

AN23

VREF

123

AJ21

AM23

124

AK22

AM24

125

AL23

AJ22

126

AK23

AL24

VREF

127

AN26

AJ23

128

AK24

AM26

VREF

129

AM27

AJ24

130

AL26

AK25

VREF

131

AN29

AJ25

VREF

132

AK26

AM29

133

AM30

AJ26

134

AK27

AL29

VREF

135

AN31

AJ27

136

AM31

AK28

VREF

137

AJ30

AH29

138

AH30

AK31

VREF

139

AJ31

AG29

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

140

AG30

AK32

VREF

141

AF29

AH31

142

AF30

AH32

143

AH33

AE29

VREF

144

AE30

AG33

VREF

145

AF32

AD29

146

AD30

AE31

VREF

147

AC29

AE32

148

AC30

AD31

VREF

149

AC31

AB29

150

AB30

AC33

151

AA29

AB31

152

AA31

AA30

VREF

153

Y29

AA32

154

Y30

AA33

155

W29

Y32

VREF

156

W31

W30

157

V30

W33

158

V31

V29

VREF

159

U33

V32

VREF

160

U32

U31

161

T30

T32

VREF

162

T31

T29

VREF

163

R31

R33

164

R29

R30

165

P31

P32

VREF

166

P29

P30

167

N31

M32

168

L33

N30

VREF

169

L32

M31

170

L31

M30

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG256 Fine-Pitch Ball Grid Array Packages

XCV50E, XCV100E, XCV200E, and XCV300E devices in
FG256 fine-pitch Ball Grid Array packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V

REF

, it can be used as gen-

eral I/O. Immediately following

Table 16

, see

Table 17

for

Differential Pair information.

171

J33

M29

172

K31

L30

VREF

173

H33

L29

174

H32

J31

VREF

175

H31

K29

176

G32

J30

VREF

177

G31

J29

VREF

178

E32

E33

179

F31

H29

180

E31

D32

VREF

181

C33

G29

182

D31

F30

VREF

Notes:

AO in the XCV1600E.

AO in the XCV2000E.

AO in the XCV1600E, 2000E.

AO in the XCV1000E, 1600E.

AO in the XCV1000E, 2000E.

AO in the XCV1000E.

AO in the XCV1000E, 1600E, 2000E.

AO in the XCV600E, 1600E.

AO in the XCV400E, 600E, 1600E.

10. AO in the XCV400E, 600E, 1000E, 2000E.

11. AO in the XCV400E, 600E, 1000E.

12. AO in the XCV400E, 1000E, 2000E.

13. AO in the XCV400E, 600E, 1000E, 1600E.

14. AO in the XCV400E, 1000E, 1600E.

15. AO in the XCV600E, 1000E, 2000E.

16. AO in the XCV600E, 2000E.

17. AO in the XCV400E, 600E, 1600E, 2000E.

18. AO in the XCV600E, 1000E, 1600E, 2000E.

19. AO in the XCV400E, 600E, 2000E.

20. AO in the XCV400E, 1000E.

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

GCK3

IO_L0N_Y

IO_VREF_L0P_Y

IO_L1N_YY

IO_L1P_YY

IO_VREF_L2N_YY

IO_L2P_YY

IO_L3N_Y

IO_L3P_Y

IO_VREF_L4N_YY

IO_L4P_YY

IO_L5N_YY

IO_L5P_YY

IO_L6N_Y

IO_L6P_Y

IO_VREF_L7N_Y

IO_L7P_Y

IO_LVDS_DLL_L8N

GCK2

B10

IO_LVDS_DLL_L8P

IO_L9N_Y

IO_L9P_Y

IO_L10N_Y

E10

IO_VREF_L10P_Y

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L11N_Y

A10

IO_L11P_Y

D10

IO_L12N_YY

C10

IO_L12P_YY

A11

IO_L13N_YY

B11

IO_VREF_L13P_YY

E11

IO_L14N_Y

A12

IO_L14P_Y

D11

IO_L15N_YY

A13

IO_VREF_L15P_YY

C11

IO_L16N_YY

B12

IO_L16P_YY

D12

IO_VREF_L17N_Y

A14

IO_L17P_Y

C12

IO_WRITE_L18N_YY

C13

IO_CS_L18P_YY

B13

IO_DOUT_BUSY_L19P_YY

C15

IO_DIN_D0_L19N_YY

D14

IO_L20P

B16

IO_VREF_L20N

E13

IO_L21P_YY

C16

IO_L21N_YY

E14

IO_VREF_L22P_Y

F13

IO_L22N_Y

E15

IO_L23P

F12

IO_L23N

D16

IO_VREF_L24P_Y

F14

IO_D1_L24N_Y

E16

IO_D2_L25P_YY

F15

IO_L25N_YY

G13

IO_L26P

F16

IO_L26N

G12

IO_L27P_YY

G15

IO_L27N_YY

G14

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_VREF_L28P_Y

H13

IO_D3_L28N_Y

G16

IO_L29P

J13

IO_L29N

H15

IO_L30P_YY

H14

IO_L30N_YY

H16

J15

IO_L31P

K15

IO_L31N

J14

IO_D4_L32P_Y

J16

IO_VREF_L32N_Y

K16

IO_L33P_YY

K12

IO_L33N_YY

L15

IO_L34P

K13

IO_L34N

L16

IO_L35P_YY

K14

IO_D5_L35N_YY

M16

IO_D6_L36P_Y

N16

IO_VREF_L36N_Y

L13

IO_L37P

P16

IO_L37N

L12

IO_L38P_Y

M15

IO_VREF_L38N_Y

L14

IO_L39P_YY

M14

IO_L39N_YY

R16

IO_VREF_L40P

M13

IO_L40N

T15

IO_D7_L41P_YY

N14

IO_INIT_L41N_YY

N15

GCK0

P10

IO_L42P_YY

T14

IO_L42N_YY

P13

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L43P_Y

P12

IO_VREF_L43N_Y

R13

IO_L44P_YY

N12

IO_L44N_YY

T13

IO_VREF_L45P_YY

T12

IO_L45N_YY

P11

IO_L46P_Y

R12

IO_L46N_Y

N11

IO_VREF_L47P_YY

T11

IO_L47N_YY

M11

IO_L48P_YY

R11

IO_L48N_YY

T10

IO_L49P_Y

R10

IO_L49N_Y

M10

IO_VREF_L50P_Y

IO_L50N_Y

IO_L51P_Y

N10

IO_L51N_Y

IO_LVDS_DLL_L52P

GCK1

IO_LVDS_DLL_L52N

IO_L53P_Y

IO_VREF_L53N_Y

IO_L54P_Y

IO_L54N_Y

IO_L55P_YY

IO_L55N_YY

IO_L56P_YY

IO_VREF_L56N_YY

IO_L57P_Y

IO_L57N_Y

IO_L58P_YY

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

IO_VREF_L58N_YY

IO_L59P_YY

IO_L59N_YY

IO_VREF_L60P_Y

IO_L60N_Y

IO_L61N_YY

IO_L61P_YY

IO_L62N

IO_VREF_L62P

IO_L63N_YY

IO_L63P_YY

IO_VREF_L64N_Y

IO_L64P_Y

IO_L65N

IO_L65P

IO_VREF_L66N_Y

IO_L66P_Y

IO_L67N_YY

IO_L67P_YY

IO_L68N

IO_L68P

IO_L69N_YY

IO_L69P_YY

IO_VREF_L70N_Y

IO_L70P_Y

IO_L71N

IO_L71P

IO_L72N_YY

IO_L72P_YY

IO_L73N

IO_L73P

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L74N_Y

IO_VREF_L74P_Y

IO_L75N_YY

IO_L75P_YY

IO_L76N

IO_L76P

IO_L77N_YY

IO_L77P_YY

IO_L78N_Y

IO_VREF_L78P_Y

IO_L79N

IO_L79P

IO_L80N_Y

IO_VREF_L80P_Y

IO_L81N_YY

IO_L81P_YY

IO_VREF_L82N

IO_L82P

CCLK

D15

DONE

R14

DXN

DXP

PROGRAM

P15

TCK

TDI

A15

TDO

B14

TMS

VCCINT

C14

VCCINT

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

VCCINT

D13

VCCINT

E12

VCCINT

M12

VCCINT

N13

VCCINT

P14

VCCO

H12

VCCO

H11

VCCO

J12

VCCO

J11

VCCO

GND

T16

GND

R15

GND

L11

GND

L10

GND

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG256 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

GND

K11

GND

K10

GND

J10

GND

H10

GND

G11

GND

G10

GND

F11

GND

F10

GND

B15

GND

A16

GND

Notes:
1.

REF

or I/O option only in the XCV100E, 200E, 300E;

otherwise, I/O option only.

REF

or I/O option only in the XCV200E, 300E; otherwise,

I/O option only.

Table 16: FG256 Package -- XCV50E, XCV100E,
XCV200E, XCV300E

Bank

Pin Description

Pin #

Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

IO_DLL_L52P

IO_DLL_L52N

IO_DLL_L8P

IO_DLL_L8N

IO LVDS

Total Pairs: 83, Asynchronous Outputs: 35

VREF

IO_LVDS_DLL

E10

VREF

D10

A10

A11

C10

E11

B11

VREF

D11

A12

C11

A13

VREF

D12

B12

C12

A14

VREF

B13

C13

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

C15

D14

DIN, D0

B16

E13

VREF

C16

E14

F13

E15

VREF

F12

D16

F14

E16

F15

G13

F16

G12

G15

G14

H13

G16

J13

H15

H14

H16

K15

J14

J16

K16

VREF

K12

L15

K13

L16

K14

M16

N16

L13

VREF

P16

L12

M15

L14

VREF

M14

R16

M13

T15

VREF

N14

N15

INIT

T14

P13

P12

R13

VREF

N12

T13

T12

P11

VREF

R12

N11

T11

M11

VREF

R11

T10

R10

M10

VREF

N10

IO_LVDS_DLL

VREF

Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

VREF

Notes:
1.

AO in the XCV50E, 200E, 300E.

AO in the XCV50E, 200E.

AO in the XCV50E, 300E.

AO in the XCV100E, 200E.

AO in the XCV200E.

AO in the XCV100E.

AO in the XCV50E.

Table 17: FG256 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG456 Fine-Pitch Ball Grid Array Packages

XCV200E and XCV300E devices in FG456 fine-pitch Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in both devices pro-
vided in this package. If the pin is not used as V

REF

, it can be

used as general I/O. Immediately following

Table 18

, see

Table 19

for Differential Pair information.

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

GCK3

C11

A10

D10

E11

IO_L0N

IO_L0P

IO_VREF_L1N_YY

IO_L1P_YY

IO_L2N

IO_L2P

IO_VREF_L3N_YY

IO_L3P_YY

IO_L4N_Y

IO_L4P_Y

IO_L5N_Y

IO_L5P_Y

IO_VREF_L6N_YY

IO_L6P_YY

IO_L7N_YY

IO_L7P_YY

IO_L8N_Y

IO_L8P_Y

IO_L9N_Y

IO_L9P_Y

IO_L10N

IO_L10P

E10

IO_VREF_L11N_YY

IO_L11P_YY

C10

IO_L12N_Y

F11

IO_L12P_Y

B10

IO_LVDS_DLL_L13N

B11

GCK2

A11

A12

A14

B16

B19

E13

E15

E16

E17

IO_LVDS_DLL_L13P

D11

IO_L14N_Y

C12

IO_L14P_Y

D12

IO_L15N_Y

B12

IO_L15P_Y

A13

IO_L16N_YY

E12

IO_VREF_L16P_YY

B13

IO_L17N_YY

C13

IO_L17P_YY

D13

IO_L18N_Y

B14

IO_L18P_Y

C14

IO_L19N_Y

F12

IO_L19P_Y

A15

IO_L20N_YY

B15

IO_L20P_YY

C15

IO_L21N_YY

A16

IO_VREF_L21P_YY

E14

IO_L22N_Y

D14

IO_L22P_Y

C16

IO_L23N_Y

D15

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L23P_Y

A17

IO_L24N_YY

B17

IO_VREF_L24P_YY

A18

IO_L25N_YY

D16

IO_L25P_YY

C17

IO_L26N_YY

B18

IO_VREF_L26P_YY

A19

IO_L27N_YY

D17

IO_L27P_YY

C18

IO_WRITE_L28N_YY

A20

IO_CS_L28P_YY

C19

D18

E19

E20

F20

G21

G22

J22

L19

IO_D3

K20

IO_DOUT_BUSY_L29P_YY

C21

IO_DIN_D0_L29N_YY

D20

IO_L30P_YY

C22

IO_L30N_YY

D21

IO_VREF_L31P_YY

D22

IO_L31N_YY

E21

IO_L32P_YY

E22

IO_L32N_YY

F18

IO_VREF_L33P_YY

F21

IO_L33N_YY

F19

IO_L34P_Y

F22

IO_L34N_Y

G19

IO_L35P_Y

G20

IO_L35N_Y

G18

IO_VREF_L36P_Y

H18

IO_D1_L36N_Y

H22

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

IO_D2_L37P_YY

H20

IO_L37N_YY

H19

IO_L38P_YY

H21

IO_L38N_YY

J19

IO_L39P_YY

J18

IO_L39N_YY

J20

IO_L40P_Y

K18

IO_L40N_Y

J21

IO_L41P

K22

IO_VREF_L41N

K21

IO_L42P_Y

K19

IO_L42N_Y

L22

IO_L43P_YY

L21

IO_L43N_YY

L18

IO_L44P_YY

L17

IO_L44N_YY

L20

M21

P22

R20

R22

T19

U18

V20

V21

Y22

IO_L45P_YY

M18

IO_L45N_YY

M20

IO_L46P_Y

M19

IO_L46N_Y

M17

IO_D4_L47P_Y

N22

IO_VREF_L47N_Y

N21

IO_L48P_YY

N20

IO_L48N_YY

N18

IO_L49P_YY

N19

IO_L49N_YY

P21

IO_L50P_YY

P20

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L50N_YY

P19

IO_L51P_YY

P18

IO_D5_L51N_YY

R21

IO_D6_L52P_Y

T22

IO_VREF_L52N_Y

R19

IO_L53P_Y

U22

IO_L53N_Y

R18

IO_L54P_YY

T21

IO_L54N_YY

V22

IO_L55P_YY

T20

IO_VREF_L55N_YY

U21

IO_L56P_YY

W22

IO_L56N_YY

T18

IO_L57P_YY

U19

IO_VREF_L57N_YY

U20

IO_L58P_YY

W21

IO_L58N_YY

AA22

IO_D7_L59P_YY

Y21

IO_INIT_L59N_YY

V19

M22

GCK0

W12

W14

Y13

Y17

AA16

AA19

AB12

AB17

AB21

IO_L60P_YY

W18

IO_L60N_YY

AA20

IO_L61P

Y18

IO_L61N

V17

IO_VREF_L62P_YY

AB20

IO_L62N_YY

W17

IO_L63P

AA18

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

IO_L63N

V16

IO_VREF_L64P_YY

AB19

IO_L64N_YY

AB18

IO_L65P_Y

W16

IO_L65N_Y

AA17

IO_L66P_Y

Y16

IO_L66N_Y

V15

IO_VREF_L67P_YY

AB16

IO_L67N_YY

Y15

IO_L68P_YY

AA15

IO_L68N_YY

AB15

IO_L69P_Y

W15

IO_L69N_Y

Y14

IO_L70P_Y

V14

IO_L70N_Y

AA14

IO_L71P

AB14

IO_L71N

V13

IO_VREF_L72P_YY

AA13

IO_L72N_YY

AB13

IO_L73P_Y

W13

IO_L73N_Y

AA12

IO_L74P_Y

Y12

IO_L74N_Y

V12

IO_LVDS_DLL_L75P

U12

U11

AA3

AA9

AA10

AB4

AB7

AB8

GCK1

Y11

IO_LVDS_DLL_L75N

AA11

IO_L76P_Y

AB11

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L76N_Y

W11

IO_L77P_YY

V11

IO_VREF_L77N_YY

Y10

IO_L78P_YY

AB10

IO_L78N_YY

W10

IO_L79P_Y

V10

IO_L79N_Y

IO_L80P_Y

AB9

IO_L80N_Y

IO_L81P_YY

IO_L81N_YY

AA8

IO_L82P_YY

IO_VREF_L82N_YY

IO_L83P_Y

IO_L83N_Y

AA7

IO_L84P_Y

AB6

IO_L84N_Y

AA6

IO_L85P_YY

AB5

IO_VREF_L85N_YY

AA5

IO_L86P_YY

IO_L86N_YY

IO_L87P_YY

AA4

IO_VREF_L87N_YY

IO_L88P_YY

IO_L88N_YY

AB3

AA1

IO_L89N_YY

IO_L89P_YY

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

IO_L90N_YY

IO_L90P_YY

IO_VREF_L91N_YY

IO_L91P_YY

IO_L92N_YY

IO_L92P_YY

IO_VREF_L93N_YY

IO_L93P_YY

IO_L94N_Y

IO_L94P_Y

IO_L95N_Y

IO_L95P_Y

IO_VREF_L96N_Y

IO_L96P_Y

IO_L97N_YY

IO_L97P_YY

IO_L98N_YY

IO_L98P_YY

IO_L99N_YY

IO_L99P_YY

IO_L100N_Y

IO_L100P_Y

IO_L101N

IO_VREF_L101P

IO_L102N_Y

IO_L102P_Y

IO_L103N_YY

IO_L103P_YY

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L104N_YY

IO_L104P_YY

IO_L105N_YY

IO_L105P_YY

IO_L106N_Y

IO_L106P_Y

IO_L107N_Y

IO_VREF_L107P_Y

IO_L108N_YY

IO_L108P_YY

IO_L109N_YY

IO_L109P_YY

IO_L110N_YY

IO_L110P_YY

IO_L111N_YY

IO_L111P_YY

IO_L112N_Y

IO_VREF_L112P_Y

IO_L113N_Y

IO_L113P_Y

IO_L114N_YY

IO_L114P_YY

IO_L115N_YY

IO_VREF_L115P_YY

IO_L116N_YY

IO_L116P_YY

IO_L117N_YY

IO_VREF_L117P_YY

IO_L118N_YY

IO_L118P_YY

CCLK

B22

DONE

Y19

DXN

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

DXP

AB2

PROGRAM

W20

TCK

TDI

B20

TDO

A21

TMS

W19

D19

VCCINT

E18

VCCINT

F17

VCCINT

G14

VCCINT

G15

VCCINT

G16

VCCINT

H16

VCCINT

J16

VCCINT

P16

VCCINT

R16

VCCINT

T14

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCINT

T15

VCCINT

T16

VCCINT

U17

VCCINT

V18

VCCO_7

VCCO_6

VCCO_5

U10

VCCO_5

T11

VCCO_5

T10

VCCO_4

U16

VCCO_4

U15

VCCO_4

U14

VCCO_4

U13

VCCO_4

T13

VCCO_4

T12

VCCO_3

T17

VCCO_3

R17

VCCO_3

P17

VCCO_3

N17

VCCO_3

N16

VCCO_3

M16

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VCCO_2

K17

VCCO_2

J17

VCCO_2

H17

VCCO_2

G17

VCCO_2

L16

VCCO_2

K16

VCCO_1

G13

VCCO_1

G12

VCCO_1

F16

VCCO_1

F15

VCCO_1

F14

VCCO_1

F13

VCCO_0

G11

VCCO_0

G10

VCCO_0

F10

VCCO_0

GND

AB22

GND

AB1

GND

AA21

GND

AA2

GND

Y20

GND

P14

GND

P13

GND

P12

GND

P11

GND

P10

GND

N14

GND

N13

GND

N12

GND

N11

GND

N10

GND

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG456 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

GND

M14

GND

M13

GND

M12

GND

M11

GND

M10

GND

L14

GND

L13

GND

L12

GND

L11

GND

L10

GND

K14

GND

K13

GND

K12

GND

K11

GND

K10

GND

J14

GND

J13

GND

J12

GND

J11

GND

J10

GND

C20

GND

B21

GND

A22

GND

Note 1: NC in the XCV200E device.

Table 18: FG456 -- XCV200E and XCV300E

Bank

Pin Description

Pin #

Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

W12

U12

IO_DLL_L75P

Y11

AA11

IO_DLL_L75N

A11

D11

IO_DLL_L13P

C11

B11

IO_DLL_L13N

IO LVDS

Total Pairs: 119, Asynchronous Output Pairs: 69

VREF

E10

C10

VREF

B10

F11

D11

B11

IO_LVDS_DLL

D12

C12

A13

B12

B13

E12

VREF

D13

C13

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

C14

B14

A15

F12

C15

B15

E14

A16

VREF

C16

D14

A17

D15

A18

B17

VREF

C17

D16

A19

B18

VREF

C18

D17

C19

A20

C21

D20

DIN, D0

C22

D21

D22

E21

VREF

E22

F18

F21

F19

VREF

F22

G19

G20

G18

H18

H22

D1, VREF

H20

H19

H21

J19

J18

J20

K18

J21

K22

K21

VREF

K19

L22

L21

L18

L17

L20

M18

M20

M19

M17

N22

N21

VREF

N20

N18

N19

P21

P20

P19

P18

R21

T22

R19

VREF

Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

U22

R18

T21

V22

T20

U21

VREF

W22

T18

U19

U20

VREF

W21

AA22

Y21

V19

INIT

W18

AA20

Y18

V17

AB20

W17

VREF

AA18

V16

AB19

AB18

VREF

W16

AA17

Y16

V15

AB16

Y15

VREF

AA15

AB15

W15

Y14

V14

AA14

AB14

V13

AA13

AB13

VREF

W13

AA12

Y12

V12

U12

AA11

IO_LVDS_DLL

AB11

W11

V11

Y10

VREF

AB10

W10

V10

AB9

AA8

VREF

AA7

AB6

AA6

AB5

AA5

VREF

AA4

VREF

Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG676 Fine-Pitch Ball Grid Array Package

XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V

REF

, it can be used as general I/O. Immedi-

ately following

Table 20

, see

Table 21

for Differential Pair

information.

AB3

VREF

100

101

VREF

102

103

104

105

106

107

VREF

108

109

110

111

112

VREF

113

114

115

VREF

116

117

VREF

118

Notes:
1.

AO in the XCV200E.

AO in the XCV300E.

Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E

Pair

Bank

Pin

Other

Functions

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

GCK3

E13

A10

B12

D13

G13

IO_L0N_Y

IO_L0P_Y

IO_L1N_YY

IO_L1P_YY

IO_VREF_L2N_YY

IO_L2P_YY

IO_L3N

IO_L3P

IO_L4N

IO_L4P

IO_VREF_L5N_YY

IO_L5P_YY

IO_L6N_YY

IO_L6P_YY

IO_L7N_Y

IO_L7P_Y

IO_VREF_L8N_Y

IO_L8P_Y

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L9N

IO_L9P

IO_L10N

IO_VREF_L10P

G10

IO_L11N_YY

IO_L11P_YY

F10

IO_L12N_Y

IO_L12P_Y

E10

IO_L13N_YY

G11

IO_L13P_YY

D10

IO_L14N_YY

B10

IO_L14P_YY

F11

IO_L15N

C10

IO_L15P

E11

IO_L16N_YY

G12

IO_L16P_YY

D11

IO_VREF_L17N_YY

C11

IO_L17P_YY

F12

IO_L18N_YY

A11

IO_L18P_YY

E12

IO_L19N_Y

D12

IO_L19P_Y

C12

IO_VREF_L20N_Y

A12

IO_L20P_Y

H13

IO_LVDS_DLL_L21N

B13

GCK2

C13

A13

A16

A19

A20

A22

A24

B15

B17

B23

IO_LVDS_DLL_L21P

F14

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L22N

E14

IO_L22P

F13

IO_L23N_Y

D14

IO_VREF_L23P_Y

A14

IO_L24N_Y

C14

IO_L24P_Y

H14

IO_L25N_YY

G14

IO_L25P_YY

C15

IO_L26N_YY

E15

IO_VREF_L26P_YY

D15

IO_L27N_YY

C16

IO_L27P_YY

F15

IO_L28N

G15

IO_L28P

D16

IO_L29N_YY

E16

IO_L29P_YY

A17

IO_L30N_YY

C17

IO_L30P_YY

E17

IO_L31N_Y

F16

IO_L31P_Y

D17

IO_L32N_YY

F17

IO_L32P_YY

C18

IO_L33N_YY

A18

IO_VREF_L33P_YY

G16

IO_L34N_YY

C19

IO_L34P_YY

G17

IO_L35N_Y

D18

IO_VREF_L35P_Y

B19

IO_L36N_Y

D19

IO_L36P_Y

E18

IO_L37N_YY

F18

IO_L37P_YY

B20

IO_L38N_YY

G19

IO_VREF_L38P_YY

C20

IO_L39N_YY

G18

IO_L39P_YY

E19

IO_L40N_YY

A21

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L40P_YY

D20

IO_L41N_YY

F19

IO_VREF_L41P_YY

C21

IO_L42N_YY

B22

IO_L42P_YY

E20

IO_L43N_Y

A23

IO_L43P_Y

D21

IO_WRITE_L44N_YY

C22

IO_CS_L44P_YY

E21

D25

D26

E26

F26

H26

K26

M25

N26

IO_D1

K24

IO_DOUT_BUSY_L45P_YY

E23

IO_DIN_D0_L45N_YY

F22

IO_L46P_YY

E24

IO_L46N_YY

F20

IO_L47P_Y

G21

IO_L47N_Y

G22

IO_VREF_L48P_Y

F24

IO_L48N_Y

H20

IO_L49P_Y

E25

IO_L49N_Y

H21

IO_L50P_YY

F23

IO_L50N_YY

G23

IO_VREF_L51P_YY

H23

IO_L51N_YY

J20

IO_L52P_YY

G24

IO_L52N_YY

H22

IO_L53P_Y

J21

IO_L53N_Y

G25

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_VREF_L54P_Y

G26

IO_L54N_Y

J22

IO_L55P_YY

H24

IO_L55N_YY

J23

IO_L56P_YY

J24

IO_VREF_L56N_YY

K20

IO_D2_L57P_YY

K22

IO_L57N_YY

K21

IO_L58P_YY

H25

IO_L58N_YY

K23

IO_L59P_Y

L20

IO_L59N_Y

J26

IO_L60P_Y

K25

IO_L60N_Y

L22

IO_L61P_Y

L21

IO_L61N_Y

L23

IO_L62P_Y

M20

IO_L62N_Y

L24

IO_VREF_L63P_YY

M23

IO_D3_L63N_YY

M22

IO_L64P_YY

L26

IO_L64N_YY

M21

IO_L65P_Y

N19

IO_L65N_Y

M24

IO_VREF_L66P_Y

M26

IO_L66N_Y

N20

IO_L67P_YY

N24

IO_L67N_YY

N21

IO_L68P_YY

N23

IO_L68N_YY

N22

P24

P26

R26

T26

U26

W25

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

Y26

AB25

AC25

AC26

IO_L69P_YY

P21

IO_L69N_YY

P23

IO_L70P_Y

P22

IO_VREF_L70N_Y

R25

IO_L71P_Y

P19

IO_L71N_Y

P20

IO_L72P_YY

R21

IO_L72N_YY

R22

IO_D4_L73P_YY

R24

IO_VREF_L73N_YY

R23

IO_L74P_Y

T24

IO_L74N_Y

R20

IO_L75P_Y

T22

IO_L75N_Y

U24

IO_L76P_Y

T23

IO_L76N_Y

U25

IO_L77P_Y

T21

IO_L77N_Y

U20

IO_L78P_YY

U22

IO_L78N_YY

V26

IO_L79P_YY

T20

IO_D5_L79N_YY

U23

IO_D6_L80P_YY

V24

IO_VREF_L80N_YY

U21

IO_L81P_YY

V23

IO_L81N_YY

W24

IO_L82P_Y

V22

IO_VREF_L82N_Y

W26

IO_L83P_Y

Y25

IO_L83N_Y

V21

IO_L84P_YY

V20

IO_L84N_YY

AA26

IO_L85P_YY

Y24

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_VREF_L85N_YY

W23

IO_L86P_Y

AA24

IO_L86N_Y

Y23

IO_L87P_Y

AB26

IO_L87N_Y

W21

IO_L88P_Y

Y22

IO_VREF_L88N_Y

W22

IO_L89P_Y

AA23

IO_L89N_Y

AB24

IO_L90P_YY

W20

IO_L90N_YY

AC24

IO_D7_L91P_YY

AB23

IO_INIT_L91N_YY

Y21

GCK0

AA14

AC18

AE15

AE20

AE23

AF14

AF16

AF18

AF21

AF23

IO_L92P_YY

AC22

IO_L92N_YY

AD26

IO_L93P_Y

AD23

IO_L93N_Y

AA20

IO_L94P_YY

Y19

IO_L94N_YY

AC21

IO_VREF_L95P_YY

AD22

IO_L95N_YY

AB20

IO_L96P

AE22

IO_L96N

Y18

IO_L97P

AF22

IO_L97N

AA19

IO_VREF_L98P_YY

AD21

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L98N_YY

AB19

IO_L99P_YY

AC20

IO_L99N_YY

AA18

IO_L100P_Y

AC19

IO_L100N_Y

AD20

IO_VREF_L101P_Y

AF20

IO_L101N_Y

AB18

IO_L102P

AD19

IO_L102N

Y17

IO_L103P

AE19

IO_VREF_L103N

AD18

IO_L104P_YY

AF19

IO_L104N_YY

AA17

IO_L105P_Y

AC17

IO_L105N_Y

AB17

IO_L106P_YY

Y16

IO_L106N_YY

AE17

IO_L107P_YY

AF17

IO_L107N_YY

AA16

IO_L108P

AD17

IO_L108N

AB16

IO_L109P_YY

AC16

IO_L109N_YY

AD16

IO_VREF_L110P_YY

AC15

IO_L110N_YY

Y15

IO_L111P_YY

AD15

IO_L111N_YY

AA15

IO_L112P_Y

W14

IO_L112N_Y

AB15

IO_VREF_L113P_Y

AF15

IO_L113N_Y

Y14

IO_L114P

AD14

IO_L114N

AB14

IO_LVDS_DLL_L115P

AC14

GCK1

AB13

Y13

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

AD7

AD13

AE4

AE7

AE12

AF3

AF5

AF10

AF11

IO_LVDS_DLL_L115N

AF13

IO_L116P_Y

AA13

IO_VREF_L116N_Y

AF12

IO_L117P_Y

AC13

IO_L117N_Y

W13

IO_L118P_YY

AA12

IO_L118N_YY

AD12

IO_L119P_YY

AC12

IO_VREF_L119N_YY

AB12

IO_L120P_YY

AD11

IO_L120N_YY

Y12

IO_L121P

AB11

IO_L121N

AD10

IO_L122P_YY

AC11

IO_L122N_YY

AE10

IO_L123P_YY

AC10

IO_L123N_YY

AA11

IO_L124P_Y

Y11

IO_L124N_Y

AD9

IO_L125P_YY

AB10

IO_L125N_YY

AF9

IO_L126P_YY

AD8

IO_VREF_L126N_YY

AA10

IO_L127P_YY

AE8

IO_L127N_YY

Y10

IO_L128P_Y

AC9

IO_VREF_L128N_Y

AF8

IO_L129P_Y

AF7

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L129N_Y

AB9

IO_L130P_YY

AA9

IO_L130N_YY

AF6

IO_L131P_YY

AC8

IO_VREF_L131N_YY

AC7

IO_L132P_YY

AD6

IO_L132N_YY

IO_L133P_YY

AE5

IO_L133N_YY

AA8

IO_L134P_YY

AC6

IO_VREF_L134N_YY

AB8

IO_L135P_YY

AD5

IO_L135N_YY

AA7

IO_L136P_Y

AF4

IO_L136N_Y

AC5

AA3

AC1

IO_L137N_YY

AA5

IO_L137P_YY

AC3

IO_L138N_YY

AC2

IO_L138P_YY

AB4

IO_L139N_Y

IO_L139P_Y

AA4

IO_VREF_L140N_Y

AB3

IO_L140P_Y

IO_L141N_Y

AB2

IO_L141P_Y

IO_L142N_YY

AB1

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L142P_YY

IO_VREF_L143N_YY

IO_L143P_YY

IO_L144N_YY

AA1

IO_L144P_YY

IO_L145N_Y

IO_L145P_Y

IO_VREF_L146N_Y

IO_L146P_Y

IO_L147N_YY

IO_L147P_YY

IO_L148N_YY

IO_VREF_L148P_YY

IO_L149N_YY

IO_L149P_YY

IO_L150N_YY

IO_L150P_YY

IO_L151N_Y

IO_L151P_Y

IO_L152N_Y

IO_L152P_Y

IO_L153N_Y

IO_L153P_Y

IO_L154N_Y

IO_L154P_Y

IO_VREF_L155N_YY

IO_L155P_YY

IO_L156N_YY

IO_L156P_YY

IO_L157N_Y

IO_L157P_Y

IO_VREF_L158N_Y

IO_L158P_Y

IO_L159N_YY

IO_L159P_YY

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L160N_YY

IO_L160P_YY

IO_L161N_YY

IO_L161P_YY

IO_L162N_Y

IO_VREF_L162P_Y

IO_L163N_Y

IO_L163P_Y

IO_L164N_YY

IO_L164P_YY

IO_L165N_YY

IO_VREF_L165P_YY

IO_L166N_Y

IO_L166P_Y

IO_L167N_Y

IO_L167P_Y

IO_L168N_Y

IO_L168P_Y

IO_L169N_Y

IO_L169P_Y

IO_L170N_YY

IO_L170P_YY

IO_L171N_YY

IO_L171P_YY

IO_L172N_YY

IO_VREF_L172P_YY

IO_L173N_YY

IO_L173P_YY

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

IO_L174N_Y

IO_VREF_L174P_Y

IO_L175N_Y

IO_L175P_Y

IO_L176N_YY

IO_L176P_YY

IO_L177N_YY

IO_VREF_L177P_YY

IO_L178N_Y

IO_L178P_Y

IO_L179N_Y

IO_L179P_Y

IO_L180N_Y

IO_VREF_L180P_Y

IO_L181N_Y

IO_L181P_Y

IO_L182N_YY

IO_L182P_YY

CCLK

D24

DONE

AB21

DXN

AB7

DXP

AD4

AB6

PROGRAM

AA22

TCK

TDI

D22

TDO

C23

TMS

T25

N25

L25

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

F25

F21

C26

C25

B26

B24

B21

B16

B11

AF25

AF24

AF2

AE6

AE3

AE26

AE24

AE21

AE16

AE14

AE11

AE1

AD25

AD2

AD1

AA6

AA25

AA21

AA2

A25

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

A15

VCCINT

G20

VCCINT

H19

VCCINT

J10

VCCINT

J11

VCCINT

J16

VCCINT

J17

VCCINT

J18

VCCINT

K18

VCCINT

L18

VCCINT

T18

VCCINT

U18

VCCINT

V10

VCCINT

V11

VCCINT

V16

VCCINT

V17

VCCINT

V18

VCCINT

Y20

VCCINT

W19

VCCO

J13

VCCO

J12

VCCO

H12

VCCO

H11

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

VCCO

H10

VCCO

J15

VCCO

J14

VCCO

H18

VCCO

H17

VCCO

H16

VCCO

H15

VCCO

N18

VCCO

M19

VCCO

M18

VCCO

L19

VCCO

K19

VCCO

J19

VCCO

V19

VCCO

U19

VCCO

T19

VCCO

R19

VCCO

R18

VCCO

P18

VCCO

W18

VCCO

W17

VCCO

W16

VCCO

W15

VCCO

V15

VCCO

V14

VCCO

W12

VCCO

W11

VCCO

W10

VCCO

V13

VCCO

V12

VCCO

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VCCO

GND

V25

GND

U17

GND

U16

GND

U15

GND

U14

GND

U13

GND

U12

GND

U11

GND

U10

GND

T17

GND

T16

GND

T15

GND

T14

GND

T13

GND

T12

GND

T11

GND

T10

GND

R17

GND

R16

GND

R15

GND

R14

GND

R13

GND

R12

GND

R11

GND

R10

GND

P25

GND

P17

GND

P16

GND

P15

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

GND

P14

GND

P13

GND

P12

GND

P11

GND

P10

GND

N17

GND

N16

GND

N15

GND

N14

GND

N13

GND

N12

GND

N11

GND

N10

GND

M17

GND

M16

GND

M15

GND

M14

GND

M13

GND

M12

GND

M11

GND

M10

GND

L17

GND

L16

GND

L15

GND

L14

GND

L13

GND

L12

GND

L11

GND

L10

GND

K17

GND

K16

GND

K15

GND

K14

GND

K13

GND

K12

GND

K11

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

GND

K10

GND

J25

GND

E22

GND

D23

GND

C24

GND

B25

GND

B18

GND

B14

GND

AF26

GND

AF1

GND

AE9

GND

AE25

GND

AE2

GND

AE18

GND

AE13

GND

AD3

GND

AD24

GND

AC4

GND

AC23

GND

AB5

GND

AB22

GND

A26

GND

Notes:
1.

NC in the XCV400E.

REF

or I/O option only in the XCV600E; otherwise, I/O

option only.

Table 20: FG676 -- XCV400E, XCV600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

FG676 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

Global Differential Clock

E13

B13

IO_DLL_L21N

C13

F14

IO_DLL_L21P

AB13

AF13

IO_DLL_L115N

AA14

AC14

IO_DLL_L115P

IOLVDS

Total Pairs: 183, Asynchronous Output Pairs: 97

VREF

G10

VREF

F10

E10

D10

G11

F11

B10

E11

C10

D11

G12

F12

C11

VREF

E12

A11

C12

D12

H13

A12

VREF

F14

B13

IO_LVDS_DLL

F13

E14

A14

D14

VREF

H14

C14

C15

G14

D15

E15

VREF

F15

C16

D16

G15

A17

E16

E17

C17

D17

F16

C18

F17

G16

A18

VREF

G17

C19

B19

D18

VREF

E18

D19

B20

F18

C20

G19

VREF

E19

G18

D20

A21

C21

F19

VREF

E20

B22

D21

A23

E21

C22

E23

F22

DIN, D0

E24

F20

G21

G22

F24

H20

VREF

E25

H21

F23

G23

H23

J20

VREF

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

G24

H22

J21

G25

G26

J22

VREF

H24

J23

J24

K20

VREF

K22

K21

H25

K23

L20

J26

K25

L22

L21

L23

M20

L24

M23

M22

L26

M21

N19

M24

M26

N20

VREF

N24

N21

N23

N22

P21

P23

P22

R25

VREF

P19

P20

R21

R22

R24

R23

VREF

T24

R20

T22

U24

T23

U25

T21

U20

U22

V26

T20

U23

V24

U21

VREF

V23

W24

V22

W26

VREF

Y25

V21

V20

AA26

Y24

W23

VREF

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

AA24

Y23

AB26

W21

Y22

W22

VREF

AA23

AB24

W20

AC24

AB23

Y21

INIT

AC22

AD26

AD23

AA20

Y19

AC21

AD22

AB20

VREF

AE22

Y18

AF22

AA19

AD21

AB19

VREF

AC20

AA18

100

AC19

AD20

101

AF20

AB18

VREF

102

AD19

Y17

103

AE19

AD18

VREF

104

AF19

AA17

105

AC17

AB17

106

Y16

AE17

107

AF17

AA16

108

AD17

AB16

109

AC16

AD16

110

AC15

Y15

VREF

111

AD15

AA15

112

W14

AB15

113

AF15

Y14

VREF

114

AD14

AB14

115

AC14

AF13

IO_LVDS_DLL

116

AA13

AF12

VREF

117

AC13

W13

118

AA12

AD12

119

AC12

AB12

VREF

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

120

AD11

Y12

121

AB11

AD10

122

AC11

AE10

123

AC10

AA11

124

Y11

AD9

125

AB10

AF9

126

AD8

AA10

VREF

127

AE8

Y10

128

AC9

AF8

VREF

129

AF7

AB9

130

AA9

AF6

131

AC8

AC7

VREF

132

AD6

133

AE5

AA8

134

AC6

AB8

VREF

135

AD5

AA7

136

AF4

AC5

137

AC3

AA5

138

AB4

AC2

139

AA4

140

AB3

VREF

141

AB2

142

AB1

143

VREF

144

AA1

145

146

VREF

147

148

VREF

149

150

151

152

153

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

154

155

VREF

156

157

158

VREF

159

160

161

162

VREF

163

164

165

VREF

166

167

168

169

170

171

172

VREF

173

174

VREF

175

176

177

VREF

178

179

180

VREF

181

182

Notes:
1.

AO in the XCV600E.

AO in the XCV400E.

Table 21: FG676 Differential Pin Pair Summary
XCV400E, XCV600E

Pair

Ban

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

FG680 Fine-Pitch Ball Grid Array Package

XCV600E, XCV1000E, XCV1600E, and XCV2000E
devices in the FG680 fine-pitch Ball Grid Array package
have footprint compatibility. Pins labeled I0_VREF can be
used as either in all parts unless device-dependent as indi-
cated in the footnotes. If the pin is not used as V

REF

, it can

be used as general I/O. Immediately following

Table 22

, see

Table 23

for Differential Pair information.

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

GCK3

A20

D35

B36

IO_L0N_Y

C35

IO_L0P_Y

A36

IO_VREF_L1N_Y

D34

IO_L1P_Y

B35

IO_L2N_YY

C34

IO_L2P_YY

A35

IO_VREF_L3N_YY

D33

IO_L3P_YY

B34

IO_L4N

C33

IO_L4P

A34

IO_L5N_Y

D32

IO_L5P_Y

B33

IO_L6N_YY

C32

IO_L6P_YY

D31

IO_VREF_L7N_YY

A33

IO_L7P_YY

C31

IO_L8N_Y

B32

IO_L8P_Y

B31

IO_VREF_L9N_Y

A32

IO_L9P_Y

D30

IO_L10N_YY

A31

IO_L10P_YY

C30

IO_VREF_L11N_YY

B30

IO_L11P_YY

D29

IO_L12N_Y

A30

IO_L12P_Y

C29

IO_L13N_Y

A29

IO_L13P_Y

B29

IO_VREF_L14N_YY

B28

IO_L14P_YY

A28

IO_L15N_YY

C28

IO_L15P_YY

B27

IO_L16N_Y

D27

IO_L16P_Y

A27

IO_L17N_Y

C27

IO_L17P_Y

B26

IO_L18N_YY

D26

IO_L18P_YY

C26

IO_VREF_L19N_YY

A26

IO_L19P_YY

D25

IO_L20N_Y

B25

IO_L20P_Y

C25

IO_L21N_Y

A25

IO_L21P_Y

D24

IO_L22N_YY

A24

IO_L22P_YY

B23

IO_VREF_L23N_YY

C24

IO_L23P_YY

A23

IO_L24N_Y

B24

IO_L24P_Y

B22

IO_L25N_Y

E23

IO_L25P_Y

A22

IO_L26N_YY

D23

IO_L26P_YY

B21

IO_VREF_L27N_YY

C23

IO_L27P_YY

A21

IO_L28N_Y

E22

IO_L28P_Y

B20

IO_LVDS_DLL_L29N

C22

IO_VREF

D22

GCK2

D21

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_LVDS_DLL_L29P

A19

IO_L30N_Y

C21

IO_VREF_L30P_Y

B19

IO_L31N_Y

C19

IO_L31P_Y

A18

IO_L32N_YY

D19

IO_VREF_L32P_YY

B18

IO_L33N_YY

C18

IO_L33P_YY

A17

IO_L34N_Y

D18

IO_L34P_Y

B17

IO_L35N_Y

E18

IO_L35P_Y

A16

IO_L36N_YY

C17

IO_VREF_L36P_YY

D17

IO_L37N_YY

B16

IO_L37P_YY

E17

IO_L38N_Y

A15

IO_L38P_Y

C16

IO_L39N_Y

B15

IO_L39P_Y

D16

IO_L40N_YY

A14

IO_VREF_L40P_YY

B14

IO_L41N_YY

C15

IO_L41P_YY

A13

IO_L42N_Y

D15

IO_L42P_Y

B13

IO_L43N_Y

C14

IO_L43P_Y

A12

IO_L44N_YY

D14

IO_L44P_YY

C13

IO_L45N_YY

B12

IO_VREF_L45P_YY

D13

IO_L46N_Y

A11

IO_L46P_Y

C12

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L47N_Y

B11

IO_L47P_Y

C11

IO_L48N_YY

A10

IO_VREF_L48P_YY

D11

IO_L49N_YY

B10

IO_L49P_YY

C10

IO_L50N_Y

IO_VREF_L50P_Y

D10

IO_L51N_Y

IO_L51P_Y

IO_L52N_YY

IO_VREF_L52P_YY

IO_L53N_YY

IO_L53P_YY

IO_L54N_Y

IO_L54P_Y

IO_L55N_Y

IO_L55P_Y

IO_L56N_YY

IO_VREF_L56P_YY

IO_L57N_YY

IO_L57P_YY

IO_L58N_Y

IO_VREF_L58P_Y

IO_L59N_Y

IO_L59P_Y

IO_WRITE_L60N_YY

IO_CS_L60P_YY

IO_DOUT_BUSY_L61P_YY

IO_DIN_D0_L61N_YY

IO_L62P_Y

IO_L62N_Y

IO_VREF_L63P

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L63N

IO_L64P

IO_L64N

IO_VREF_L65P_Y

IO_L65N_Y

IO_L66P_YY

IO_L66N_YY

IO_L67P

IO_L67N

IO_L68P_Y

IO_L68N_Y

IO_VREF_L69P_YY

IO_L69N_YY

IO_L70P_YY

IO_L70N_YY

IO_VREF_L71P

IO_L71N

IO_L72P

IO_L72N

IO_VREF_L73P_YY

IO_L73N_YY

IO_L74P_YY

IO_L74N_YY

IO_L75P

IO_L75N

IO_VREF_L76P_YY

IO_D1_L76N_YY

IO_D2_L77P_YY

IO_L77N_YY

IO_L78P_Y

IO_L78N_Y

IO_L79P

IO_L79N

IO_L80P

IO_L80N

IO_VREF_L81P_Y

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L81N_Y

IO_L82P_YY

IO_L82N_YY

IO_L83P

IO_L83N

IO_L84P_Y

IO_L84N_Y

IO_VREF_L85P_YY

IO_D3_L85N_YY

IO_L86P_YY

IO_L86N_YY

IO_L87P

IO_L87N

IO_L88P

IO_L88N

IO_VREF_L89P_YY

IO_L89N_YY

IO_L90P_YY

AA3

IO_L90N_YY

IO_VREF_L91P

AA4

IO_L91N

IO_L92P_YY

AB2

IO_L92N_YY

AP3

AT3

AB3

IO_L93P

AB4

IO_VREF_L93N

IO_L94P_YY

AB5

IO_L94N_YY

IO_L95P_YY

AC2

IO_VREF_L95N_YY

IO_L96P

AC3

IO_L96N

AA1

IO_L97P

AC4

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L97N

AA2

IO_L98P_YY

AC5

IO_L98N_YY

AB1

IO_D4_L99P_YY

AD3

IO_VREF_L99N_YY

AC1

IO_L100P_Y

AD1

IO_L100N_Y

AD4

IO_L101P

AD2

IO_L101N

AE3

IO_L102P_YY

AE1

IO_L102N_YY

AE4

IO_L103P_Y

AE2

IO_VREF_L103N_Y

AF3

IO_L104P

AF4

IO_L104N

AF1

IO_L105P

AG3

IO_L105N

AF2

IO_L106P_Y

AG4

IO_L106N_Y

AG1

IO_L107P_YY

AH3

IO_D5_L107N_YY

AG2

IO_D6_L108P_YY

AH1

IO_VREF_L108N_YY

AJ2

IO_L109P

AH2

IO_L109N

AJ3

IO_L110P_YY

AJ1

IO_L110N_YY

AJ4

IO_L111P_YY

AK1

IO_VREF_L111N_YY

AK3

IO_L112P

AK2

IO_L112N

AK4

IO_L113P

AL1

IO_VREF_L113N

AL2

IO_L114P_YY

AM1

IO_L114N_YY

AL3

IO_L115P_YY

AM2

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_VREF_L115N_YY

AL4

IO_L116P_Y

AM3

IO_L116N_Y

AN1

IO_L117P

AM4

IO_L117N

AP1

IO_L118P_YY

AN2

IO_L118N_YY

AP2

IO_L119P_Y

AN3

IO_VREF_L119N_Y

AR1

IO_L120P

AN4

IO_L120N

AT1

IO_L121P

AR2

IO_VREF_L121N

AP4

IO_L122P_Y

AT2

IO_L122N_Y

AR3

IO_D7_L123P_YY

AR4

IO_INIT_L123N_YY

AU2

GCK0

AW19

AV3

IO_L124P_YY

AU4

IO_L124N_YY

AV5

IO_L125P_Y

AT6

IO_L125N_Y

AV4

IO_VREF_L126P_Y

AU6

IO_L126N_Y

AW4

IO_L127P_YY

AT7

IO_L127N_YY

AW5

IO_VREF_L128P_YY

AU7

IO_L128N_YY

AV6

IO_L129P_Y

AT8

IO_L129N_Y

AW6

IO_L130P_Y

AU8

IO_L130N_Y

AV7

IO_L131P_YY

AT9

IO_L131N_YY

AW7

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_VREF_L132P_YY

AV8

IO_L132N_YY

AU9

IO_L133P_Y

AW8

IO_L133N_Y

AT10

IO_VREF_L134P_Y

AV9

IO_L134N_Y

AU10

IO_L135P_YY

AW9

IO_L135N_YY

AT11

IO_VREF_L136P_YY

AV10

IO_L136N_YY

AU11

IO_L137P_Y

AW10

IO_L137N_Y

AU12

IO_L138P_Y

AV11

IO_L138N_Y

AT13

IO_VREF_L139P_YY

AW11

IO_L139N_YY

AU13

IO_L140P_YY

AT14

IO_L140N_YY

AV12

IO_L141P_Y

AU14

IO_L141N_Y

AW12

IO_L142P_Y

AT15

IO_L142N_Y

AV13

IO_L143P_YY

AU15

IO_L143N_YY

AW13

IO_VREF_L144P_YY

AV14

IO_L144N_YY

AT16

IO_L145P_Y

AW14

IO_L145N_Y

AU16

IO_L146P_Y

AV15

IO_L146N_Y

AR17

IO_L147P_YY

AW15

IO_L147N_YY

AT17

IO_VREF_L148P_YY

AU17

IO_L148N_YY

AV16

IO_L149P_Y

AR18

IO_L149N_Y

AW16

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L150P_Y

AT18

IO_L150N_Y

AV17

IO_L151P_YY

AU18

IO_L151N_YY

AW17

IO_VREF_L152P_YY

AT19

IO_L152N_YY

AV18

IO_L153P_Y

AU19

IO_L153N_Y

AW18

IO_VREF_L154P

AU21

IO_L154N

AV19

IO_LVDS_DLL_L155P

AT21

GCK1

AU22

AT34

AW20

IO_LVDS_DLL_L155N

AT22

IO_VREF_L156P_Y

AV20

IO_L156N_Y

AR22

IO_L157P_YY

AV23

IO_VREF_L157N_YY

AW21

IO_L158P_YY

AU23

IO_L158N_YY

AV21

IO_L159P_Y

AT23

IO_L159N_Y

AW22

IO_L160P_Y

AR23

IO_L160N_Y

AV22

IO_L161P_YY

AV24

IO_VREF_L161N_YY

AW23

IO_L162P_YY

AW24

IO_L162N_YY

AU24

IO_L163P_Y

AW25

IO_L163N_Y

AT24

IO_L164P_Y

AV25

IO_L164N_Y

AU25

IO_L165P_YY

AW26

IO_VREF_L165N_YY

AT25

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L166P_YY

AV26

IO_L166N_YY

AW27

IO_L167P_Y

AU26

IO_L167N_Y

AV27

IO_L168P_Y

AT26

IO_L168N_Y

AW28

IO_L169P_YY

AU27

IO_L169N_YY

AV28

IO_L170P_YY

AW29

IO_VREF_L170N_YY

AT27

IO_L171P_Y

AW30

IO_L171N_Y

AU28

IO_L172P_Y

AV30

IO_L172N_Y

AV29

IO_L173P_YY

AW31

IO_VREF_L173N_YY

AU29

IO_L174P_YY

AV31

IO_L174N_YY

AT29

IO_L175P_Y

AW32

IO_VREF_L175N_Y

AU30

IO_L176P_Y

AW33

IO_L176N_Y

AT30

IO_L177P_YY

AV33

IO_VREF_L177N_YY

AU31

IO_L178P_YY

AT31

IO_L178N_YY

AW34

IO_L179P_Y

AV32

IO_L179N_Y

AV34

IO_L180P_Y

AU32

IO_L180N_Y

AW35

IO_L181P_YY

AT32

IO_VREF_L181N_YY

AV35

IO_L182P_YY

AU33

IO_L182N_YY

AW36

IO_L183P_Y

AT33

IO_VREF_L183N_Y

AV36

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L184P_Y

AU34

IO_L184N_Y

AU36

W39

AR37

AR39

IO_L185N_YY

AR36

IO_L185P_YY

AT38

IO_L186N_Y

AR38

IO_L186P_Y

AP36

IO_VREF_L187N

AT39

IO_L187P

AP37

IO_L188N

AP38

IO_L188P

AP39

IO_VREF_L189N_Y

AN36

IO_L189P_Y

AN38

IO_L190N_YY

AN37

IO_L190P_YY

AN39

IO_L191N

AM36

IO_L191P

AM38

IO_L192N_Y

AM37

IO_L192P_Y

AL36

IO_VREF_L193N_YY

AM39

IO_L193P_YY

AL37

IO_L194N_YY

AL38

IO_L194P_YY

AK36

IO_VREF_L195N

AL39

IO_L195P

AK37

IO_L196N

AK38

IO_L196P

AJ36

IO_VREF_L197N_YY

AK39

IO_L197P_YY

AJ37

IO_L198N_YY

AJ38

IO_L198P_YY

AH37

IO_L199N

AJ39

IO_L199P

AH38

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_VREF_L200N_YY

AH39

IO_L200P_YY

AG38

IO_L201N_YY

AG36

IO_L201P_YY

AG39

IO_L202N_Y

AG37

IO_L202P_Y

AF39

IO_L203N

AF36

IO_L203P

AE38

IO_L204N

AF37

IO_L204P

AF38

IO_VREF_L205N_Y

AE39

IO_L205P_Y

AE36

IO_L206N_YY

AD38

IO_L206P_YY

AE37

IO_L207N

AD39

IO_L207P

AD36

IO_L208N_Y

AC38

IO_L208P_Y

AC39

IO_VREF_L209N_YY

AD37

IO_L209P_YY

AB38

IO_L210N_YY

AC35

IO_L210P_YY

AB39

IO_L211N

AC36

IO_L211P

AA38

IO_L212N

AC37

IO_L212P

AA39

IO_VREF_L213N_YY

AB35

IO_L213P_YY

Y38

IO_L214N_YY

AB36

IO_L214P_YY

Y39

IO_VREF_L215N

AB37

IO_L215P

AA36

C38

B37

F37

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L216N_YY

AA37

IO_L216P_YY

W38

IO_L217N

W37

IO_VREF_L217P

V39

IO_L218N_YY

W36

IO_L218P_YY

U39

IO_L219N_YY

V38

IO_VREF_L219P_YY

U38

IO_L220N

V37

IO_L220P

T39

IO_L221N

V36

IO_L221P

T38

IO_L222N_YY

V35

IO_L222P_YY

R39

IO_L223N_YY

U37

IO_VREF_L223P_YY

U36

IO_L224N_Y

R38

IO_L224P_Y

U35

IO_L225N

P39

IO_L225P

T37

IO_L226N_YY

P38

IO_L226P_YY

T36

IO_L227N_Y

N39

IO_VREF_L227P_Y

N38

IO_L228N

R37

IO_L228P

M39

IO_L229N

R36

IO_L229P

M38

IO_L230N_Y

P37

IO_L230P_Y

L39

IO_L231N_YY

P36

IO_L231P_YY

N37

IO_L232N_YY

L38

IO_VREF_L232P_YY

N36

IO_L233N

K39

IO_L233P

M37

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L234N_YY

K38

IO_L234P_YY

L37

IO_L235N_YY

J39

IO_VREF_L235P_YY

L36

IO_L236N

J38

IO_L236P

K37

IO_L237N

H39

IO_VREF_L237P

K36

IO_L238N_YY

H38

IO_L238P_YY

J37

IO_L239N_YY

G39

IO_VREF_L239P_YY

G38

IO_L240N_Y

J36

IO_L240P_Y

F39

IO_L241N

H37

IO_L241P

F38

IO_L242N_YY

H36

IO_L242P_YY

E39

IO_L243N_Y

G37

IO_VREF_L243P_Y

E38

IO_L244N

G36

IO_L244P

D39

IO_L245N

D38

IO_VREF_L245P

F36

IO_L246N_Y

D37

IO_L246P_Y

E37

CCLK

DONE

AU5

DXN

AV37

DXP

AU35

AT37

AU38

AT35

PROGRAM

AT5

TCK

C36

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

TDI

TDO

TMS

E36

VCCINT

E15

VCCINT

E16

VCCINT

E24

VCCINT

E25

VCCINT

E31

VCCINT

E32

VCCINT

H35

VCCINT

J35

VCCINT

R35

VCCINT

T35

VCCINT

AD5

VCCINT

AD35

VCCINT

AE5

VCCINT

AE35

VCCINT

AL5

VCCINT

AL35

VCCINT

AM5

VCCINT

AM35

VCCINT

AR8

VCCINT

AR9

VCCINT

AR15

VCCINT

AR16

VCCINT

AR24

VCCINT

AR25

VCCINT

AR31

VCCINT

AR32

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCO

E34

VCCO

E33

VCCO

E30

VCCO

E29

VCCO

E27

VCCO

E26

VCCO

E10

VCCO

E11

VCCO

E13

VCCO

E14

VCCO

AP5

VCCO

AN5

VCCO

AK5

VCCO

AJ5

VCCO

AG5

VCCO

AF5

VCCO

AR10

VCCO

AR11

VCCO

AR13

VCCO

AR14

VCCO

AR6

VCCO

AR7

VCCO

AR34

VCCO

AR33

VCCO

AR30

VCCO

AR29

VCCO

AR27

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VCCO

AR26

VCCO

AP35

VCCO

AN35

VCCO

AK35

VCCO

AJ35

VCCO

AG35

VCCO

AF35

VCCO

P35

VCCO

N35

VCCO

L35

VCCO

K35

VCCO

G35

VCCO

F35

GND

Y37

GND

Y36

GND

Y35

GND

W35

GND

M36

GND

M35

GND

E35

GND

E28

GND

E21

GND

E20

GND

E19

GND

E12

GND

D36

GND

D28

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

GND

D20

GND

D12

GND

C39

GND

C37

GND

C20

GND

B39

GND

B38

GND

AW39

GND

AW38

GND

AW37

GND

AW3

GND

AW2

GND

AW1

GND

AV39

GND

AV38

GND

AV2

GND

AV1

GND

AU39

GND

AU37

GND

AU3

GND

AU20

GND

AU1

GND

AT4

GND

AT36

GND

AT28

GND

AT20

GND

AT12

GND

AR5

GND

AR35

GND

AR28

GND

AR21

GND

AR20

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

GND

AR19

GND

AR12

GND

AH5

GND

AH4

GND

AH36

GND

AH35

GND

AA5

GND

AA35

GND

A39

GND

A38

GND

A37

GND

Notes:
1.

REF

or I/O option only in the XCV1000E, 1600E, 2000E;

otherwise, I/O option only.

REF

or I/O option only in the XCV1600E, 2000E; otherwise,

I/O option only.

REF

or I/O option only in the XCV2000E; otherwise, I/O

option only.

Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

FG680 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

GCLK LVDS

A20

C22

IO_DLL_L29N

D21

A19

IO_DLL_L29P

AU22

AT22

IO_DLL_L155N

AW19

AT21

IO_DLL_L155P

IO LVDS

Total Pairs: 247, Asynchronous Output Pairs: 111

A36

C35

B35

D34

VREF

A35

C34

B34

D33

VREF

A34

C33

B33

D32

D31

C32

C31

A33

VREF

B31

B32

D30

A32

VREF

C30

A31

D29

B30

VREF

C29

A30

B29

A29

A28

B28

VREF

B27

C28

A27

D27

B26

C27

C26

D26

D25

A26

VREF

C25

B25

D24

A25

B23

A24

A23

C24

VREF

B22

B24

A22

E23

B21

D23

A21

C23

VREF

B20

E22

A19

C22

IO_LVDS_DLL

B19

C21

VREF

A18

C19

B18

D19

VREF

A17

C18

B17

D18

A16

E18

D17

C17

VREF

E17

B16

C16

A15

D16

B15

B14

A14

VREF

A13

C15

B13

D15

A12

C14

C13

D14

D13

B12

VREF

C12

A11

C11

B11

D11

A10

VREF

C10

B10

D10

VREF

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

VREF

DIN, D0

VREF

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VREF

AA3

AA4

VREF

AB2

AB4

VREF

AB5

AC2

VREF

AC3

AA1

AC4

AA2

AC5

AB1

AD3

AC1

VREF

100

AD1

AD4

101

AD2

AE3

102

AE1

AE4

103

AE2

AF3

VREF

104

AF4

AF1

105

AG3

AF2

106

AG4

AG1

107

AH3

AG2

108

AH1

AJ2

VREF

109

AH2

AJ3

110

AJ1

AJ4

111

AK1

AK3

VREF

112

AK2

AK4

113

AL1

AL2

VREF

114

AM1

AL3

115

AM2

AL4

VREF

116

AM3

AN1

117

AM4

AP1

118

AN2

AP2

119

AN3

AR1

VREF

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

120

AN4

AT1

121

AR2

AP4

VREF

122

AT2

AR3

123

AR4

AU2

INIT

124

AU4

AV5

125

AT6

AV4

126

AU6

AW4

VREF

127

AT7

AW5

128

AU7

AV6

VREF

129

AT8

AW6

130

AU8

AV7

131

AT9

AW7

132

AV8

AU9

VREF

133

AW8

AT10

134

AV9

AU10

VREF

135

AW9

AT11

136

AV10

AU11

VREF

137

AW10

AU12

138

AV11

AT13

139

AW11

AU13

VREF

140

AT14

AV12

141

AU14

AW12

142

AT15

AV13

143

AU15

AW13

144

AV14

AT16

VREF

145

AW14

AU16

146

AV15

AR17

147

AW15

AT17

148

AU17

AV16

VREF

149

AR18

AW16

150

AT18

AV17

151

AU18

AW17

152

AT19

AV18

VREF

153

AU19

AW18

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

154

AU21

AV19

VREF

155

AT21

AT22

IO_LVDS_DLL

156

AV20

AR22

VREF

157

AV23

AW21

VREF

158

AU23

AV21

159

AT23

AW22

160

AR23

AV22

161

AV24

AW23

VREF

162

AW24

AU24

163

AW25

AT24

164

AV25

AU25

165

AW26

AT25

VREF

166

AV26

AW27

167

AU26

AV27

168

AT26

AW28

169

AU27

AV28

170

AW29

AT27

VREF

171

AW30

AU28

172

AV30

AV29

173

AW31

AU29

VREF

174

AV31

AT29

175

AW32

AU30

VREF

176

AW33

AT30

177

AV33

AU31

VREF

178

AT31

AW34

179

AV32

AV34

180

AU32

AW35

181

AT32

AV35

VREF

182

AU33

AW36

183

AT33

AV36

VREF

184

AU34

AU36

185

AT38

AR36

186

AP36

AR38

187

AP37

AT39

VREF

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

188

AP39

AP38

189

AN38

AN36

VREF

190

AN39

AN37

191

AM38

AM36

192

AL36

AM37

193

AL37

AM39

VREF

194

AK36

AL38

195

AK37

AL39

VREF

196

AJ36

AK38

197

AJ37

AK39

VREF

198

AH37

AJ38

199

AH38

AJ39

200

AG38

AH39

VREF

201

AG39

AG36

202

AF39

AG37

203

AE38

AF36

204

AF38

AF37

205

AE36

AE39

VREF

206

AE37

AD38

207

AD36

AD39

208

AC39

AC38

209

AB38

AD37

VREF

210

AB39

AC35

211

AA38

AC36

212

AA39

AC37

213

Y38

AB35

VREF

214

Y39

AB36

215

AA36

AB37

VREF

216

W38

AA37

217

V39

W37

VREF

218

U39

W36

219

U38

V38

VREF

220

T39

V37

221

T38

V36

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

222

R39

V35

223

U36

U37

VREF

224

U35

R38

225

T37

P39

226

T36

P38

227

N38

N39

VREF

228

M39

R37

229

M38

R36

230

L39

P37

231

N37

P36

232

N36

L38

VREF

233

M37

K39

234

L37

K38

235

L36

J39

VREF

236

K37

J38

237

K36

H39

VREF

238

J37

H38

239

G38

G39

VREF

240

F39

J36

241

F38

H37

242

E39

H36

243

E38

G37

VREF

244

D39

G36

245

F36

D38

VREF

246

E37

D37

Notes:
1.

AO in the XCV1000E, 1600E, 2000E.

AO in the XCV600E, 1000E, 1600E.

AO in the XCV600E, 1000E.

AO in the XCV1000E, 1600E.

AO in the XCV1000E, 2000E.

AO in the XCV600E, 1000E, 2000E.

AO in the XCV1000E.

AO in the XCV2000E.

Table 23: FG680 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

FG860 Fine-Pitch Ball Grid Array Package

XCV1000E, XCV1600E, and XCV2000E devices in the
FG680 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V

REF

, it can be used as gen-

eral I/O. Immediately following

Table 24

, see

Table 25

for

Differential Pair information.

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

GCK3

C22

A26

B31

B34

C24

C29

C34

D24

D36

D40

E26

E28

E35

IO_L0N_Y

A38

IO_L0P_Y

D38

IO_L1N_Y

B37

IO_L1P_Y

E37

IO_VREF_L2N_Y

A37

IO_L2P_Y

C39

IO_L3N_Y

B36

IO_L3P_Y

C38

IO_L4N_YY

A36

IO_L4P_YY

B35

IO_VREF_L5N_YY

A35

IO_L5P_YY

D37

IO_L6N_Y

C37

IO_L6P_Y

A34

IO_L7N_Y

E36

IO_L7P_Y

B33

IO_L8N_YY

A33

IO_L8P_YY

C32

IO_VREF_L9N_YY

C36

IO_L9P_YY

B32

IO_L10N_Y

A32

IO_L10P_Y

D35

IO_VREF_L11N_Y

C31

IO_L11P_Y

C35

IO_L12N_YY

E34

IO_L12P_YY

A31

IO_VREF_L13N_YY

D34

IO_L13P_YY

C30

IO_L14N_Y

B30

IO_L14P_Y

E33

IO_L15N_Y

A30

IO_L15P_Y

D33

IO_VREF_L16N_YY

C33

IO_L16P_YY

B29

IO_L17N_YY

E32

IO_L17P_YY

A29

IO_L18N_Y

D32

IO_L18P_Y

C28

IO_L19N_Y

E31

IO_L19P_Y

B28

IO_L20N_Y

D31

IO_L20P_Y

A28

IO_L21N_Y

D30

IO_L21P_Y

C27

IO_L22N_YY

E29

IO_L22P_YY

B27

IO_VREF_L23N_YY

D29

IO_L23P_YY

A27

IO_L24N_Y

C26

IO_L24P_Y

D28

IO_L25N_Y

B26

IO_L25P_Y

F27

IO_L26N_YY

E27

IO_L26P_YY

C25

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_VREF_L27N_YY

D27

IO_L27P_YY

B25

IO_L28N_Y

A25

IO_L28P_Y

D26

IO_L29N_Y

A24

IO_L29P_Y

E25

IO_L30N_YY

D25

IO_L30P_YY

B24

IO_VREF_L31N_YY

E24

IO_L31P_YY

A23

IO_L32N_Y

C23

IO_L32P_Y

E23

IO_VREF_L33N_Y

B23

IO_L33P_Y

D23

IO_LVDS_DLL_L34N

A22

GCK2

B22

A14

A20

B11

B13

C18

C21

D10

D15

D17

E20

IO_LVDS_DLL_L34P

D22

IO_L35N_Y

D21

IO_VREF_L35P_Y

B21

IO_L36N_Y

D20

IO_L36P_Y

A21

IO_L37N_YY

C20

IO_VREF_L37P_YY

D19

IO_L38N_YY

B20

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L38P_YY

E19

IO_L39N_Y

D18

IO_L39P_Y

A19

IO_L40N_Y

E18

IO_L40P_Y

C19

IO_L41N_YY

B19

IO_VREF_L41P_YY

E17

IO_L42N_YY

A18

IO_L42P_YY

D16

IO_L43N_Y

E16

IO_L43P_Y

B18

IO_L44N_Y

F16

IO_L44P_Y

A17

IO_L45N_YY

C17

IO_VREF_L45P_YY

E15

IO_L46N_YY

B17

IO_L46P_YY

D14

IO_L47N_Y

A16

IO_L47P_Y

E14

IO_L48N_Y

C16

IO_L48P_Y

D13

IO_L49N_Y

B16

IO_L49P_Y

D12

IO_L50N_Y

A15

IO_L50P_Y

E12

IO_L51N_YY

C15

IO_L51P_YY

C11

IO_L52N_YY

B15

IO_VREF_L52P_YY

D11

IO_L53N_Y

E11

IO_L53P_Y

C14

IO_L54N_Y

C10

IO_L54P_Y

B14

IO_L55N_YY

A13

IO_VREF_L55P_YY

E10

IO_L56N_YY

C13

IO_L56P_YY

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L57N_Y

IO_VREF_L57P_Y

A12

IO_L58N_Y

IO_L58P_Y

C12

IO_L59N_YY

B12

IO_VREF_L59P_YY

IO_L60N_YY

A11

IO_L60P_YY

IO_L61N_Y

IO_L61P_Y

A10

IO_L62N_Y

IO_L62P_Y

B10

IO_L63N_YY

IO_VREF_L63P_YY

IO_L64N_YY

IO_L64P_YY

IO_L65N_Y

IO_L65P_Y

IO_L66N_Y

IO_VREF_L66P_Y

IO_L67N_Y

IO_L67P_Y

IO_L68N_Y

IO_L68P_Y

IO_WRITE_L69N_YY

IO_CS_L69P_YY

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

AA3

IO_DOUT_BUSY_L70P_YY

IO_DIN_D0_L70N_YY

IO_L71P_Y

IO_L71N_Y

IO_L72P_Y

IO_L72N_Y

IO_VREF_L73P_Y

IO_L73N_Y

IO_L74P

IO_L74N

IO_L75P_Y

IO_L75N_Y

IO_VREF_L76P_Y

IO_L76N_Y

IO_L77P_YY

IO_L77N_YY

IO_L78P_Y

IO_L78N_Y

IO_L79P_Y

IO_L79N_Y

IO_VREF_L80P_YY

IO_L80N_YY

IO_L81P_YY

IO_L81N_YY

IO_VREF_L82P_Y

IO_L82N_Y

IO_L83P_Y

IO_L83N_Y

IO_VREF_L84P_YY

IO_L84N_YY

IO_L85P_YY

IO_L85N_YY

IO_L86P_Y

IO_L86N_Y

IO_VREF_L87P_YY

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_D1_L87N_YY

IO_D2_L88P_YY

IO_L88N_YY

IO_L89P_Y

IO_L89N_Y

IO_L90P_Y

IO_L90N_Y

IO_L91P_Y

IO_L91N_Y

IO_L92P

IO_L92N

IO_L93P_Y

IO_L93N_Y

IO_VREF_L94P_Y

IO_L94N_Y

IO_L95P_YY

IO_L95N_YY

IO_L96P_Y

IO_L96N_Y

IO_L97P_Y

IO_L97N_Y

IO_VREF_L98P_YY

IO_D3_L98N_YY

IO_L99P_YY

IO_L99N_YY

IO_L100P_Y

IO_L100N_Y

IO_L101P_Y

IO_L101N_Y

IO_VREF_L102P_YY

IO_L102N_YY

IO_L103P_YY

IO_L103N_YY

IO_VREF_L104P_Y

AA1

IO_L104N_Y

IO_L105P_YY

AA4

IO_L105N_YY

AA2

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

AB4

AC2

AD1

AE3

AF4

AH5

AJ2

AL1

AM3

AP3

AR5

AU4

AB2

IO_L106P_Y

AB3

IO_VREF_L106N_Y

AC4

IO_L107P_YY

AB1

IO_L107N_YY

AC5

IO_L108P_YY

AD4

IO_VREF_L108N_YY

AC3

IO_L109P_Y

AC1

IO_L109N_Y

AD5

IO_L110P_Y

AE4

IO_L110N_Y

AD3

IO_L111P_YY

AE5

IO_L111N_YY

AD2

IO_D4_L112P_YY

AE1

IO_VREF_L112N_YY

AF5

IO_L113P_Y

AE2

IO_L113N_Y

AG4

IO_L114P_Y

AG5

IO_L114N_Y

AF1

IO_L115P_YY

AH4

IO_L115N_YY

AF2

IO_L116P_Y

AF3

IO_VREF_L116N_Y

AJ4

IO_L117P_Y

AG1

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L117N_Y

AJ5

IO_L118P

AG2

IO_L118N

AK4

IO_L119P_Y

AG3

IO_L119N_Y

AL4

IO_L120P_Y

AH1

IO_L120N_Y

AL5

IO_L121P_Y

AH2

IO_L121N_Y

AM4

IO_L122P_YY

AH3

IO_D5_L122N_YY

AM5

IO_D6_L123P_YY

AJ1

IO_VREF_L123N_YY

AN3

IO_L124P_Y

AN4

IO_L124N_Y

AJ3

IO_L125P_YY

AN5

IO_L125N_YY

AK1

IO_L126P_YY

AK2

IO_VREF_L126N_YY

AP4

IO_L127P_Y

AK3

IO_L127N_Y

AP5

IO_L128P_Y

AR3

IO_VREF_L128N_Y

AL2

IO_L129P_YY

AR4

IO_L129N_YY

AL3

IO_L130P_YY

AM1

IO_VREF_L130N_YY

AT3

IO_L131P_Y

AM2

IO_L131N_Y

AT4

IO_L132P_Y

AT5

IO_L132N_Y

AN1

IO_L133P_YY

AU3

IO_L133N_YY

AN2

IO_L134P_Y

AP1

IO_VREF_L134N_Y

AP2

IO_L135P_Y

AR1

IO_L135N_Y

AV3

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L136P

AR2

IO_L136N

AT1

IO_L137P_Y

AV4

IO_VREF_L137N_Y

AT2

IO_L138P_Y

AU1

IO_L138N_Y

AU5

IO_L139P_Y

AU2

IO_L139N_Y

AW3

IO_D7_L140P_YY

AV1

IO_INIT_L140N_YY

AW5

GCK0

BA22

AV17

AY11

AY12

AY13

AY14

BA8

BA17

BA19

BA20

BA21

BB9

BB18

IO_L141P_YY

AV6

IO_L141N_YY

BA4

IO_L142P_Y

AY4

IO_L142N_Y

BA5

IO_L143P_Y

AW6

IO_L143N_Y

BB5

IO_VREF_L144P_Y

BA6

IO_L144N_Y

AY5

IO_L145P_Y

BB6

IO_L145N_Y

AY6

IO_L146P_YY

BA7

IO_L146N_YY

AV7

IO_VREF_L147P_YY

BB7

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L147N_YY

AW7

IO_L148P_Y

AY7

IO_L148N_Y

BB8

IO_L149P_Y

BA9

IO_L149N_Y

AV8

IO_L150P_YY

AW8

IO_L150N_YY

BA10

IO_VREF_L151P_YY

BB10

IO_L151N_YY

AY8

IO_L152P_Y

AV9

IO_L152N_Y

BA11

IO_VREF_L153P_Y

BB11

IO_L153N_Y

AW9

IO_L154P_YY

AY9

IO_L154N_YY

BA12

IO_VREF_L155P_YY

BB12

IO_L155N_YY

AV10

IO_L156P_Y

BA13

IO_L156N_Y

AW10

IO_L157P_Y

BB13

IO_L157N_Y

AY10

IO_VREF_L158P_YY

AV11

IO_L158N_YY

BA14

IO_L159P_YY

AW11

IO_L159N_YY

BB14

IO_L160P_Y

AV12

IO_L160N_Y

BA15

IO_L161P_Y

AW12

IO_L161N_Y

AY15

IO_L162P_Y

AW13

IO_L162N_Y

BB15

IO_L163P_Y

AV14

IO_L163N_Y

BA16

IO_L164P_YY

AW14

IO_L164N_YY

AY16

IO_VREF_L165P_YY

BB16

IO_L165N_YY

AV15

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L166P_Y

AY17

IO_L166N_Y

AW15

IO_L167P_Y

BB17

IO_L167N_Y

AU16

IO_L168P_YY

AV16

IO_L168N_YY

AY18

IO_VREF_L169P_YY

AW16

IO_L169N_YY

BA18

IO_L170P_Y

BB19

IO_L170N_Y

AW17

IO_L171P_Y

AY19

IO_L171N_Y

AV18

IO_L172P_YY

AW18

IO_L172N_YY

BB20

IO_VREF_L173P_YY

AY20

IO_L173N_YY

AV19

IO_L174P_Y

BB21

IO_L174N_Y

AW19

IO_VREF_L175P_Y

AY21

IO_L175N_Y

AV20

IO_LVDS_DLL_L176P

AW20

GCK1

AY22

AV24

AV34

AW27

AW36

AY23

AY31

AY33

BA26

BA29

BA33

BB25

IO_LVDS_DLL_L176N

AW21

IO_L177P_Y

BB22

IO_VREF_L177N_Y

AW22

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_L178P_Y

BB23

IO_L178N_Y

AW23

IO_L179P_YY

AV23

IO_VREF_L179N_YY

BA23

IO_L180P_YY

AW24

IO_L180N_YY

BB24

IO_L181P_Y

AY24

IO_L181N_Y

AW25

IO_L182P_Y

BA24

IO_L182N_Y

AV25

IO_L183P_YY

AW26

IO_VREF_L183N_YY

AY25

IO_L184P_YY

AV26

IO_L184N_YY

BA25

IO_L185P_Y

BB26

IO_L185N_Y

AV27

IO_L186P_Y

AY26

IO_L186N_Y

AU27

IO_L187P_YY

AW28

IO_VREF_L187N_YY

BB27

IO_L188P_YY

AY27

IO_L188N_YY

AV28

IO_L189P_Y

BA27

IO_L189N_Y

AW29

IO_L190P_Y

BB28

IO_L190N_Y

AV29

IO_L191P_Y

AY28

IO_L191N_Y

AW30

IO_L192P_Y

BA28

IO_L192N_Y

AW31

IO_L193P_YY

BB29

IO_L193N_YY

AV31

IO_L194P_YY

AY29

IO_VREF_L194N_YY

AY32

IO_L195P_Y

AW32

IO_L195N_Y

BB30

IO_L196P_Y

AV32

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L196N_Y

AY30

IO_L197P_YY

BA30

IO_VREF_L197N_YY

AW33

IO_L198P_YY

BB31

IO_L198N_YY

AV33

IO_L199P_Y

AY34

IO_VREF_L199N_Y

BA31

IO_L200P_Y

AW34

IO_L200N_Y

BB32

IO_L201P_YY

BA32

IO_VREF_L201N_YY

AY35

IO_L202P_YY

BB33

IO_L202N_YY

AW35

IO_L203P_Y

AV35

IO_L203N_Y

BB34

IO_L204P_Y

AY36

IO_L204N_Y

BA34

IO_L205P_YY

BB35

IO_VREF_L205N_YY

AV36

IO_L206P_YY

BA35

IO_L206N_YY

AY37

IO_L207P_Y

BB36

IO_L207N_Y

BA36

IO_L208P_Y

AW37

IO_VREF_L208N_Y

BB37

IO_L209P_Y

BA37

IO_L209N_Y

AY38

IO_L210P_Y

BB38

IO_L210N_Y

AY39

AA40

AB41

AC42

AD39

AE40

AF38

AF40

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

AJ40

AL41

AN38

AN42

AP41

AR39

IO_L211N_YY

AV41

IO_L211P_YY

AV42

IO_L212N_Y

AW40

IO_L212P_Y

AU41

IO_L213N_Y

AV39

IO_L213P_Y

AU42

IO_VREF_L214N_Y

AT41

IO_L214P_Y

AU38

IO_L215N

AT42

IO_L215P

AV40

IO_L216N_Y

AR41

IO_L216P_Y

AU39

IO_VREF_L217N_Y

AR42

IO_L217P_Y

AU40

IO_L218N_YY

AT38

IO_L218P_YY

AP42

IO_L219N_Y

AN41

IO_L219P_Y

AT39

IO_L220N_Y

AT40

IO_L220P_Y

AM40

IO_VREF_L221N_YY

AR38

IO_L221P_YY

AM41

IO_L222N_YY

AM42

IO_L222P_YY

AR40

IO_VREF_L223N_Y

AL40

IO_L223P_Y

AP38

IO_L224N_Y

AP39

IO_L224P_Y

AL42

IO_VREF_L225N_YY

AP40

IO_L225P_YY

AK40

IO_L226N_YY

AK41

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L226P_YY

AN39

IO_L227N_Y

AK42

IO_L227P_Y

AN40

IO_VREF_L228N_YY

AM38

IO_L228P_YY

AJ41

IO_L229N_YY

AJ42

IO_L229P_YY

AM39

IO_L230N_Y

AH40

IO_L230P_Y

AH41

IO_L231N_Y

AL38

IO_L231P_Y

AH42

IO_L232N_Y

AL39

IO_L232P_Y

AG41

IO_L233N

AK39

IO_L233P

AG40

IO_L234N_Y

AJ38

IO_L234P_Y

AG42

IO_VREF_L235N_Y

AF42

IO_L235P_Y

AJ39

IO_L236N_YY

AF41

IO_L236P_YY

AH38

IO_L237N_Y

AE42

IO_L237P_Y

AH39

IO_L238N_Y

AG38

IO_L238P_Y

AE41

IO_VREF_L239N_YY

AG39

IO_L239P_YY

AD42

IO_L240N_YY

AD40

IO_L240P_YY

AF39

IO_L241N_Y

AD41

IO_L241P_Y

AE38

IO_L242N_Y

AE39

IO_L242P_Y

AC40

IO_VREF_L243N_YY

AD38

IO_L243P_YY

AC41

IO_L244N_YY

AB42

IO_L244P_YY

AC38

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

IO_VREF_L245N_Y

AB40

IO_L245P_Y

AC39

F38

H40

H41

J42

K39

L42

N40

T40

U40

V38

W42

Y42

AA42

IO_L246N_YY

AA41

IO_L246P_YY

AB39

IO_L247N_Y

Y41

IO_VREF_L247P_Y

AA39

IO_L248N_YY

Y40

IO_L248P_YY

Y39

IO_L249N_YY

Y38

IO_VREF_L249P_YY

W41

IO_L250N_Y

W40

IO_L250P_Y

W39

IO_L251N_Y

W38

IO_L251P_Y

V41

IO_L252N_YY

V39

IO_L252P_YY

V40

IO_L253N_YY

V42

IO_VREF_L253P_YY

U39

IO_L254N_Y

U41

IO_L254P_Y

U38

IO_L255N_Y

U42

IO_L255P_Y

T39

IO_L256N_YY

T41

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

IO_L256P_YY

T38

IO_L257N_Y

R39

IO_VREF_L257P_Y

T42

IO_L258N_Y

R42

IO_L258P_Y

R38

IO_L259N

R40

IO_L259P

P39

IO_L260N_Y

R41

IO_L260P_Y

P38

IO_L261N_Y

P42

IO_L261P_Y

N39

IO_L262N_Y

P40

IO_L262P_Y

M39

IO_L263N_YY

P41

IO_L263P_YY

M38

IO_L264N_YY

N42

IO_VREF_L264P_YY

L39

IO_L265N_Y

L38

IO_L265P_Y

N41

IO_L266N_YY

K40

IO_L266P_YY

M42

IO_L267N_YY

M40

IO_VREF_L267P_YY

K38

IO_L268N_Y

M41

IO_L268P_Y

J40

IO_L269N_Y

J39

IO_VREF_L269P_Y

L40

IO_L270N_YY

J38

IO_L270P_YY

L41

IO_L271N_YY

K42

IO_VREF_L271P_YY

H39

IO_L272N_Y

K41

IO_L272P_Y

H38

IO_L273N_Y

J41

IO_L273P_Y

G40

IO_L274N_YY

H42

IO_L274P_YY

G39

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

IO_L275N_Y

G38

IO_VREF_L275P_Y

G42

IO_L276N_Y

G41

IO_L276P_Y

F40

IO_L277N

F42

IO_L277P

F41

IO_L278N_Y

F39

IO_VREF_L278P_Y

E42

IO_L279N_Y

E40

IO_L279P_Y

E41

IO_L280N_Y

E39

IO_L280P_Y

D41

CCLK

DONE

AW2

DXN

BA38

DXP

AW38

AW41

AV37

BA39

PROGRAM

AV2

TCK

B38

TDI

TDO

TMS

B39

VCCINT

F10

VCCINT

F17

VCCINT

F18

VCCINT

F25

VCCINT

F26

VCCINT

F33

VCCINT

F34

VCCINT

J37

VCCINT

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VCCINT

K37

VCCINT

T37

VCCINT

U37

VCCINT

V37

VCCINT

AE6

VCCINT

AE37

VCCINT

AF6

VCCINT

AF37

VCCINT

AG6

VCCINT

AG37

VCCINT

AN6

VCCINT

AN37

VCCINT

AP6

VCCINT

AP37

VCCINT

AU9

VCCINT

AU10

VCCINT

AU17

VCCINT

AU18

VCCINT

AU25

VCCINT

AU26

VCCINT

AU33

VCCINT

AU34

VCCO_0

F23

VCCO_0

F24

VCCO_0

F28

VCCO_0

F29

VCCO_0

F31

VCCO_0

F32

VCCO_0

F35

VCCO_0

F36

VCCO_1

F11

VCCO_1

F12

VCCO_1

F14

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

VCCO_1

F15

VCCO_1

F19

VCCO_1

F20

VCCO_1

VCCO_2

VCCO_3

AC6

VCCO_3

AD6

VCCO_3

AH6

VCCO_3

AJ6

VCCO_3

AL6

VCCO_3

AM6

VCCO_3

AR6

VCCO_3

AT6

VCCO_4

AU11

VCCO_4

AU12

VCCO_4

AU14

VCCO_4

AU15

VCCO_4

AU19

VCCO_4

AU20

VCCO_4

AU7

VCCO_4

AU8

VCCO_5

AU23

VCCO_5

AU24

VCCO_5

AU28

VCCO_5

AU29

VCCO_5

AU31

VCCO_5

AU32

VCCO_5

AU35

VCCO_5

AU36

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VCCO_6

AC37

VCCO_6

AD37

VCCO_6

AH37

VCCO_6

AJ37

VCCO_6

AL37

VCCO_6

AM37

VCCO_6

AR37

VCCO_6

AT37

VCCO_7

G37

VCCO_7

H37

VCCO_7

L37

VCCO_7

M37

VCCO_7

P37

VCCO_7

R37

VCCO_7

W37

VCCO_7

Y37

GND

N38

GND

N37

GND

F37

GND

F30

GND

F22

GND

F21

GND

F13

GND

E38

GND

E30

GND

E22

GND

E21

GND

E13

GND

D42

GND

D39

GND

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

GND

C42

GND

C41

GND

C40

GND

BB41

GND

BB40

GND

BB4

GND

BB39

GND

BB3

GND

BB2

GND

BA42

GND

BA41

GND

BA40

GND

BA3

GND

BA2

GND

BA1

GND

B42

GND

B41

GND

B40

GND

AY42

GND

AY41

GND

AY40

GND

AY3

GND

AY2

GND

AY1

GND

AW42

GND

AW4

GND

AW39

GND

AW1

GND

AV5

GND

AV38

GND

AV30

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

GND

AV22

GND

AV21

GND

AV13

GND

AU6

GND

AU37

GND

AU30

GND

AU22

GND

AU21

GND

AU13

GND

AK6

GND

AK5

GND

AK38

GND

AK37

GND

AB6

GND

AB5

GND

AB38

GND

AB37

GND

AA6

GND

AA5

GND

AA38

GND

AA37

GND

A41

GND

A40

GND

A39

GND

Notes:
1.

REF

or I/O option only in the XCV1600E, 2000E; otherwise,

I/O option only.

REF

or I/O option only in the XCV2000E; otherwise, I/O

option only.

Table 24: FG860 -- XCV1000E, XCV1600E, XCV2000E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

1-800-255-7778

Production Product Specification

FG860 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

Global Differential Clock

C22

A22

IO_DLL_L34N

B22

D22

IO_DLL_L34P

AY22

AW21

IO_DLL_L176N

BA22

AW20

IO_DLL_L176P

IO LVDS

Total Pairs: 281, Asynchronous Output Pairs: 111

D38

A38

E37

B37

C39

A37

VREF

C38

B36

B35

A36

D37

A35

VREF

A34

C37

B33

E36

C32

A33

B32

C36

VREF

D35

A32

C35

C31

VREF

A31

E34

C30

D34

VREF

E33

B30

D33

A30

B29

C33

VREF

A29

E32

C28

D32

B28

E31

A28

D31

C27

D30

B27

E29

A27

D29

VREF

D28

C26

F27

B26

C25

E27

B25

D27

VREF

D26

A25

E25

A24

B24

D25

A23

E24

VREF

E23

C23

D23

B23

VREF

D22

A22

IO_LVDS_DLL

B21

D21

VREF

A21

D20

D19

C20

VREF

E19

B20

A19

D18

C19

E18

E17

B19

VREF

D16

A18

B18

E16

A17

F16

E15

C17

VREF

D14

B17

E14

A16

D13

C16

D12

B16

E12

A15

C11

C15

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

D11

B15

VREF

C14

E11

B14

C10

E10

A13

VREF

C13

A12

VREF

C12

B12

VREF

A11

A10

B10

VREF

DIN, D0

VREF

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VREF

100

101

102

VREF

103

104

AA1

VREF

105

AA4

AA2

106

AB3

AC4

VREF

107

AB1

AC5

108

AD4

AC3

VREF

109

AC1

AD5

110

AE4

AD3

111

AE5

AD2

112

AE1

AF5

VREF

113

AE2

AG4

114

AG5

AF1

115

AH4

AF2

116

AF3

AJ4

VREF

117

AG1

AJ5

118

AG2

AK4

119

AG3

AL4

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

100

1-800-255-7778

Production Product Specification

120

AH1

AL5

121

AH2

AM4

122

AH3

AM5

123

AJ1

AN3

VREF

124

AN4

AJ3

125

AN5

AK1

126

AK2

AP4

VREF

127

AK3

AP5

128

AR3

AL2

VREF

129

AR4

AL3

130

AM1

AT3

VREF

131

AM2

AT4

132

AT5

AN1

133

AU3

AN2

134

AP1

AP2

VREF

135

AR1

AV3

136

AR2

AT1

137

AV4

AT2

VREF

138

AU1

AU5

139

AU2

AW3

140

AV1

AW5

INIT

141

AV6

BA4

142

AY4

BA5

143

AW6

BB5

144

BA6

AY5

VREF

145

BB6

AY6

146

BA7

AV7

147

BB7

AW7

VREF

148

AY7

BB8

149

BA9

AV8

150

AW8

BA10

151

BB10

AY8

VREF

152

AV9

BA11

153

BB11

AW9

VREF

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

154

AY9

BA12

155

BB12

AV10

VREF

156

BA13

AW10

157

BB13

AY10

158

AV11

BA14

VREF

159

AW11

BB14

160

AV12

BA15

161

AW12

AY15

162

AW13

BB15

163

AV14

BA16

164

AW14

AY16

165

BB16

AV15

VREF

166

AY17

AW15

167

BB17

AU16

168

AV16

AY18

169

AW16

BA18

VREF

170

BB19

AW17

171

AY19

AV18

172

AW18

BB20

173

AY20

AV19

VREF

174

BB21

AW19

175

AY21

AV20

VREF

176

AW20

AW21

IO_LVDS_DLL

177

BB22

AW22

VREF

178

BB23

AW23

179

AV23

BA23

VREF

180

AW24

BB24

181

AY24

AW25

182

BA24

AV25

183

AW26

AY25

VREF

184

AV26

BA25

185

BB26

AV27

186

AY26

AU27

187

AW28

BB27

VREF

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

101

188

AY27

AV28

189

BA27

AW29

190

BB28

AV29

191

AY28

AW30

192

BA28

AW31

193

BB29

AV31

194

AY29

AY32

VREF

195

AW32

BB30

196

AV32

AY30

197

BA30

AW33

VREF

198

BB31

AV33

199

AY34

BA31

VREF

200

AW34

BB32

201

BA32

AY35

VREF

202

BB33

AW35

203

AV35

BB34

204

AY36

BA34

205

BB35

AV36

VREF

206

BA35

AY37

207

BB36

BA36

208

AW37

BB37

VREF

209

BA37

AY38

210

BB38

AY39

211

AV42

AV41

212

AU41

AW40

213

AU42

AV39

214

AU38

AT41

VREF

215

AV40

AT42

216

AU39

AR41

217

AU40

AR42

VREF

218

AP42

AT38

219

AT39

AN41

220

AM40

AT40

221

AM41

AR38

VREF

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

222

AR40

AM42

223

AP38

AL40

VREF

224

AL42

AP39

225

AK40

AP40

VREF

226

AN39

AK41

227

AN40

AK42

228

AJ41

AM38

VREF

229

AM39

AJ42

230

AH41

AH40

231

AH42

AL38

232

AG41

AL39

233

AG40

AK39

234

AG42

AJ38

235

AJ39

AF42

VREF

236

AH38

AF41

237

AH39

AE42

238

AE41

AG38

239

AD42

AG39

VREF

240

AF39

AD40

241

AE38

AD41

242

AC40

AE39

243

AC41

AD38

VREF

244

AC38

AB42

245

AC39

AB40

VREF

246

AB39

AA41

247

AA39

Y41

VREF

248

Y39

Y40

249

W41

Y38

VREF

250

W39

W40

251

V41

W38

252

V40

V39

253

U39

V42

VREF

254

U38

U41

255

T39

U42

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

102

1-800-255-7778

Production Product Specification

FG900 Fine-Pitch Ball Grid Array Package

XCV600E, XCV1000E, and XCV1600E devices in the
FG900 fine-pitch Ball Grid Array package have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V

REF

, it can be used as gen-

eral I/O. Immediately following

Table 26

, see

Table 27

for

Differential Pair information.

256

T38

T41

257

T42

R39

VREF

258

R38

R42

259

P39

R40

260

P38

R41

261

N39

P42

262

M39

P40

263

M38

P41

264

L39

N42

VREF

265

N41

L38

266

M42

K40

267

K38

M40

VREF

268

J40

M41

269

L40

J39

VREF

270

L41

J38

271

H39

K42

VREF

272

H38

K41

273

G40

J41

274

G39

H42

275

G42

G38

VREF

276

F40

G41

277

F41

F42

278

E42

F39

VREF

279

E41

E40

280

D41

E39

Notes:
1.

AO in the XCV1000E, 2000E.

AO in the XCV1000E, 1600E.

AO in the XCV2000E.

AO in the XCV1600E.

AO in the XCV1000E.

Table 25: FG860 Differential Pin Pair Summary
XCV1000E, XCV1600E, XCV2000E

Pair

Bank

Pin

Other

Functions

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

GCK3

C15

A13

C14

D10

D13

E14

F14

G15

K11

K12

L13

IO_L0N_YY

IO_L0P_YY

IO_L1N_Y

IO_L1P_Y

IO_VREF_L2N_Y

IO_L2P_Y

IO_L3N_Y

IO_L3P_Y

J10

IO_L4N_YY

IO_L4P_YY

IO_VREF_L5N_YY

IO_L5P_YY

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

103

IO_L6N_Y

IO_L6P_Y

IO_L7N_Y

IO_L7P_Y

N11

IO_L8N_YY

IO_L8P_YY

IO_VREF_L9N_YY

IO_L9P_YY

J11

IO_L10N_Y

IO_L10P_Y

IO_L11N_Y

IO_L11P_Y

H10

IO_L12N_YY

G10

IO_L12P_YY

F10

IO_VREF_L13N_YY

IO_L13P_YY

H11

IO_L14N

IO_L14P

IO_L15N_YY

IO_L15P_YY

J12

IO_L16N

E10

IO_VREF_L16P

IO_L17N

G11

IO_L17P

B10

IO_L18N_YY

H12

IO_L18P_YY

C10

IO_L19N_Y

H13

IO_L19P_Y

F11

IO_L20N_Y

E11

IO_L20P_Y

D11

IO_L21N_Y

B11

IO_L21P_Y

G12

IO_L22N_YY

F12

IO_L22P_YY

C11

IO_VREF_L23N_YY

A10

IO_L23P_YY

D12

IO_L24N_Y

E12

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L24P_Y

A11

IO_L25N_Y

G13

IO_L25P_Y

B12

IO_L26N_YY

A12

IO_L26P_YY

K13

IO_VREF_L27N_YY

F13

IO_L27P_YY

B13

IO_L28N_Y

G14

IO_L28P_Y

E13

IO_L29N_Y

D14

IO_L29P_Y

B14

IO_L30N_YY

A14

IO_L30P_YY

J14

IO_VREF_L31N_YY

K14

IO_L31P_YY

J15

IO_L32N

B15

IO_L32P

H15

IO_VREF_L33N_YY

F15

2,3

IO_L33P_YY

D15

IO_LVDS_DLL_L34N

A15

GCK2

E15

A25

B17

B18

C23

D16

D17

D23

E19

E24

F22

G17

G20

J16

J17

J19

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

104

1-800-255-7778

Production Product Specification

J20

L18

IO_LVDS_DLL_L34P

E16

IO_L35N_YY

B16

IO_VREF_L35P_YY

F16

IO_L36N_YY

A16

IO_L36P_YY

H16

IO_L37N_YY

C16

IO_VREF_L37P_YY

K15

IO_L38N_YY

K16

IO_L38P_YY

G16

IO_L39N_Y

A17

IO_L39P_Y

E17

IO_L40N_Y

F17

IO_L40P_Y

C17

IO_L41N_YY

E18

IO_VREF_L41P_YY

A18

IO_L42N_YY

D18

IO_L42P_YY

A19

IO_L43N_Y

B19

IO_L43P_Y

G18

IO_L44N_Y

D19

IO_L44P_Y

H18

IO_L45N_YY

F18

IO_VREF_L45P_YY

F19

IO_L46N_YY

B20

IO_L46P_YY

K17

IO_L47N_Y

D20

IO_L47P_Y

A20

IO_L48N_Y

G19

IO_L48P_Y

C20

IO_L49N_Y

K18

IO_L49P_Y

E20

IO_L50N_YY

B21

IO_L50P_YY

D21

IO_L51N_YY

F20

IO_L51P_YY

A21

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L52N_YY

C21

IO_VREF_L52P_YY

A22

IO_L53N_YY

H19

IO_L53P_YY

B22

IO_L54N_YY

E21

IO_L54P_YY

D22

IO_L55N_YY

F21

IO_VREF_L55P_YY

C22

IO_L56N_YY

H20

IO_L56P_YY

E22

IO_L57N_Y

G21

IO_L57P_Y

A23

IO_L58N_Y

A24

IO_L58P_Y

K19

IO_L59N_YY

C24

IO_VREF_L59P_YY

B24

IO_L60N_YY

H21

IO_L60P_YY

G22

IO_L61N_Y

E23

IO_L61P_Y

C25

IO_L62N_Y

D24

IO_L62P_Y

A26

IO_L63N_YY

B26

IO_VREF_L63P_YY

K20

IO_L64N_YY

D25

IO_L64P_YY

J21

IO_L65N_Y

C26

IO_L65P_Y

F23

IO_L66N_Y

B27

IO_VREF_L66P_Y

G23

IO_L67N_Y

A27

IO_L67P_Y

F24

IO_L68N_YY

B28

IO_L68P_YY

A28

IO_WRITE_L69N_YY

K21

IO_CS_L69P_YY

C27

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

105

D29

G26

H24

H25

H28

J25

J27

K30

M24

M25

N20

N23

P26

P27

P30

R30

IO_DOUT_BUSY_L70P_YY

J22

IO_DIN_D0_L70N_YY

E27

IO_L71P

C29

IO_L71N

D28

IO_L72P_Y

G25

IO_L72N_Y

E25

IO_VREF_L73P_YY

E28

IO_L73N_YY

C30

IO_L74P_Y

K22

IO_L74N_Y

F27

IO_L75P_YY

D30

IO_L75N_YY

J23

IO_VREF_L76P_Y

L21

IO_L76N_Y

F28

IO_L77P_YY

G28

IO_L77N_YY

E30

IO_L78P_YY

G27

IO_L78N_YY

E29

IO_L79P

K23

IO_L79N

H26

IO_VREF_L80P_YY

F30

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L80N_YY

L22

IO_L81P_YY

H27

IO_L81N_YY

G29

IO_L82P

G30

IO_L82N

M21

IO_L83P_YY

J24

IO_L83N_YY

J26

IO_VREF_L84P_YY

H30

IO_L84N_YY

L23

IO_L85P_YY

K26

IO_L85N_YY

J28

IO_L86P_YY

J29

IO_L86N_YY

K24

IO_L87P_YY

K27

IO_VREF_L87N_YY

J30

IO_D1_L88P

M22

IO_D2_L88N

K29

IO_L89P_YY

K28

IO_L89N_YY

L25

IO_L90P

N21

IO_L90N

K25

IO_L91P_YY

L24

IO_L91N_YY

L27

IO_L92P_Y

L29

IO_L92N_Y

M23

IO_L93P_YY

L26

IO_L93N_YY

L28

IO_VREF_L94P

L30

IO_L94N

M27

IO_L95P_YY

M26

IO_L95N_YY

M29

IO_L96P_YY

N29

IO_L96N_YY

M30

IO_L97P

N25

IO_L97N

N27

IO_VREF_L98P_YY

N30

IO_D3_L98N_YY

P21

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

106

1-800-255-7778

Production Product Specification

IO_L99P_YY

N26

IO_L99N_YY

P28

IO_L100P

P29

IO_L100N

N24

IO_L101P_YY

P22

IO_L101N_YY

R26

IO_VREF_L102P_YY

P25

IO_L102N_YY

R29

IO_L103P_YY

R21

IO_L103N_YY

R28

IO_VREF_L104P_YY

R25

IO_L104N_YY

T30

IO_L105P_YY

P24

IO_L105N_YY

R27

IO_L106P

R24

T22

T24

T26

T29

U26

V23

V25

V30

Y21

AA26

AA23

AB27

AB29

AC28

AD26

AD29

AE27

IO_L106N

U29

IO_L107P_YY

R22

IO_VREF_L107N_YY

T27

IO_L108P_YY

R23

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L108N_YY

T28

IO_L109P_YY

T21

IO_VREF_L109N_YY

T25

IO_L110P_YY

U28

IO_L110N_YY

U30

IO_L111P

T23

IO_L111N

U27

IO_L112P_YY

U25

IO_L112N_YY

V27

IO_D4_L113P_YY

U24

IO_VREF_L113N_YY

V29

IO_L114P

W30

IO_L114N

U22

IO_L115P_YY

U21

IO_L115N_YY

W29

IO_L116P_YY

V26

IO_L116N_YY

W27

IO_L117P

W26

IO_VREF_L117N

Y29

IO_L118P_YY

W25

IO_L118N_YY

Y30

IO_L119P_Y

V24

IO_L119N_Y

Y28

IO_L120P_YY

AA30

IO_L120N_YY

W24

IO_L121P

AA29

IO_L121N

V20

IO_L122P

Y27

IO_L122N

W23

IO_L123P_YY

Y26

IO_D5_L123N_YY

AB30

IO_D6_L124P_YY

V21

IO_VREF_L124N_YY

AA28

IO_L125P_YY

Y25

IO_L125N_YY

AA27

IO_L126P_YY

W22

IO_L126N_YY

Y23

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

107

IO_L127P_YY

Y24

IO_VREF_L127N_YY

AB28

IO_L128P_YY

AC30

IO_L128N_YY

AA25

IO_L129P

W21

IO_L129N

AA24

IO_L130P_YY

AB26

IO_L130N_YY

AD30

IO_L131P_YY

Y22

IO_VREF_L131N_YY

AC27

IO_L132P

AD28

IO_L132N

AB25

IO_L133P_YY

AC26

IO_L133N_YY

AE30

IO_L134P_YY

AD27

IO_L134N_YY

AF30

IO_L135P

AF29

IO_VREF_L135N

AB24

IO_L136P_YY

AB23

IO_L136N_YY

AE28

IO_L137P_Y

AG30

IO_L137N_Y

AC25

IO_L138P_YY

AE26

IO_VREF_L138N_YY

AG29

IO_L139P

AH30

IO_L139N

AC24

IO_L140P

AF28

IO_L140N

AD25

IO_D7_L141P_YY

AH29

IO_INIT_L141N_YY

AA22

GCK0

AJ16

AB19

AC16

AC19

AD18

AD21

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

AE15

AE18

AE21

AE24

AF17

AF18

AJ18

AK18

AK25

AK27

AH23

AH24

IO_L142P_YY

AF27

IO_L142N_YY

AK28

IO_L143P_YY

AG26

IO_L143N_YY

AH27

IO_L144P

AD23

IO_L144N

AJ27

IO_VREF_L145P

AB21

IO_L145N

AF25

IO_L146P

AC22

IO_L146N

AH26

IO_L147P_YY

AA21

IO_L147N_YY

AG25

IO_VREF_L148P_YY

AJ26

IO_L148N_YY

AD22

IO_L149P

AA20

IO_L149N

AH25

IO_L150P

AC21

IO_L150N

AF24

IO_L151P_YY

AG24

IO_L151N_YY

AK26

IO_VREF_L152P_YY

AJ24

IO_L152N_YY

AF23

IO_L153P

AE23

IO_L153N

AB20

IO_L154P

AC20

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

108

1-800-255-7778

Production Product Specification

IO_L154N

AG23

IO_L155P_YY

AF22

IO_L155N_YY

AE22

IO_VREF_L156P_YY

AJ22

IO_L156N_YY

AG22

IO_L157P

AK24

IO_L157N

AD20

IO_L158P_YY

AA19

IO_L158N_YY

AF21

IO_L159P

AH22

IO_VREF_L159N

AA18

IO_L160P

AG21

IO_L160N

AK23

IO_L161P_YY

AH21

IO_L161N_YY

AD19

IO_L162P

AE20

IO_L162N

AJ21

IO_L163P

AG20

IO_L163N

AF20

IO_L164P

AC18

IO_L164N

AF19

IO_L165P_YY

AJ20

IO_L165N_YY

AE19

IO_VREF_L166P_YY

AK22

IO_L166N_YY

AH20

IO_L167P

AG19

IO_L167N

AB17

IO_L168P

AJ19

IO_L168N

AD17

IO_L169P_YY

AA16

IO_L169N_YY

AA17

IO_VREF_L170P_YY

AK21

IO_L170N_YY

AB16

IO_L171P

AG18

IO_L171N

AK20

IO_L172P

AK19

IO_L172N

AD16

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L173P_YY

AE16

IO_L173N_YY

AE17

IO_VREF_L174P_YY

AG17

IO_L174N_YY

AJ17

IO_L175P

AD15

IO_L175N

AH17

IO_VREF_L176P_YY

AG16

IO_L176N_YY

AK17

IO_LVDS_DLL_L177P

AF16

GCK1

AK16

AA11

AA14

AD14

AE7

AE8

AE10

AF6

AF10

AG9

AG12

AG14

AH8

AK6

AK14

AJ13

AJ15

IO_LVDS_DLL_L177N

AH16

IO_L178P_YY

AC15

IO_VREF_L178N_YY

AG15

2,3

IO_L179P_YY

AB15

IO_L179N_YY

AF15

IO_L180P_YY

AA15

IO_VREF_L180N_YY

AF14

IO_L181P_YY

AH15

IO_L181N_YY

AK15

IO_L182P

AB14

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

109

IO_L182N

AF13

IO_L183P

AH14

IO_L183N

AJ14

IO_L184P_YY

AE14

IO_VREF_L184N_YY

AG13

IO_L185P_YY

AK13

IO_L185N_YY

AD13

IO_L186P

AE13

IO_L186N

AF12

IO_L187P

AC13

IO_L187N

AA13

IO_L188P_YY

AA12

IO_VREF_L188N_YY

AJ12

IO_L189P_YY

AB12

IO_L189N_YY

AE11

IO_L190P

AK12

IO_L190N

Y13

IO_L191P

AG11

IO_L191N

AF11

IO_L192P

AH11

IO_L192N

AJ11

IO_L193P_YY

AE12

IO_L193N_YY

AG10

IO_L194P_YY

AD12

IO_L194N_YY

AK11

IO_L195P_YY

AJ10

IO_VREF_L195N_YY

AC12

IO_L196P_YY

AK10

IO_L196N_YY

AD11

IO_L197P_YY

AJ9

IO_L197N_YY

AE9

IO_L198P_YY

AH10

IO_VREF_L198N_YY

AF9

IO_L199P_YY

AH9

IO_L199N_YY

AK9

IO_L200P

AF8

IO_L200N

AB11

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L201P

AC11

IO_L201N

AG8

IO_L202P_YY

AK8

IO_VREF_L202N_YY

AF7

IO_L203P_YY

AG7

IO_L203N_YY

AK7

IO_L204P

AJ7

IO_L204N

AD10

IO_L205P

AH6

IO_L205N

AC10

IO_L206P_YY

AD9

IO_VREF_L206N_YY

AG6

IO_L207P_YY

AB10

IO_L207N_YY

AJ5

IO_L208P

AD8

IO_L208N

AK5

IO_L209P

AC9

IO_VREF_L209N

AJ4

IO_L210P

AG5

IO_L210N

AK4

IO_L211P_YY

AH5

IO_L211N_YY

AG3

T10

Y10

AA4

AB5

AB7

AC3

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

110

1-800-255-7778

Production Product Specification

AC5

AD1

AE5

IO_L212N_YY

AF3

IO_L212P_YY

AC6

IO_L213N

AH2

IO_L213P

AG2

IO_L214N

AB9

IO_L214P

AE4

IO_VREF_L215N_YY

AE3

IO_L215P_YY

AH1

IO_L216N_Y

AB8

IO_L216P_Y

AD6

IO_L217N_YY

AG1

IO_L217P_YY

AA10

IO_VREF_L218N

AA9

IO_L218P

AD4

IO_L219N_YY

AD5

IO_L219P_YY

AD2

IO_L220N_YY

AD3

IO_L220P_YY

AF2

IO_L221N

AA8

IO_L221P

AA7

IO_VREF_L222N_YY

AF1

IO_L222P_YY

IO_L223N_YY

AB6

IO_L223P_YY

AC4

IO_L224N

AE1

IO_L224P

IO_L225N_YY

IO_L225P_YY

AB4

IO_VREF_L226N_YY

AB3

IO_L226P_YY

IO_L227N_YY

AA5

IO_L227P_YY

W10

IO_L228N_YY

AB1

IO_L228P_YY

V10

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L229N_YY

IO_VREF_L229P_YY

AC1

IO_L230N

V11

IO_L230P

AA3

IO_L231N_YY

AA2

IO_L231P_YY

U10

IO_L232N

IO_L232P

AA6

IO_L233N_YY

IO_L233P_YY

IO_L234N_Y

AA1

IO_L234P_Y

IO_L235N_YY

IO_L235P_YY

IO_VREF_L236N

IO_L236P

IO_L237N_YY

IO_L237P_YY

IO_L238N_YY

IO_L238P_YY

IO_L239N

IO_L239P

IO_VREF_L240N_YY

AB2

IO_L240P_YY

IO_L241N_YY

IO_L241P_YY

IO_L242N

IO_L242P

IO_L243N_YY

IO_L243P_YY

IO_VREF_L244N_YY

IO_L244P_YY

IO_L245N_YY

IO_L245P_YY

IO_VREF_L246N_YY

IO_L246P_YY

IO_L247N

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

111

L10

N10

IO_L247P

R10

IO_L248N_YY

IO_L248P_YY

IO_L249N_YY

IO_VREF_L249P_YY

IO_L250N_YY

IO_L250P_YY

IO_L251N_YY

P10

IO_VREF_L251P_YY

IO_L252N_YY

IO_L252P_YY

IO_L253N

IO_L253P

IO_L254N_YY

IO_L254P_YY

IO_L255N_YY

IO_VREF_L255P_YY

IO_L256N

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

IO_L256P

IO_L257N_YY

IO_L257P_YY

IO_L258N_YY

IO_L258P_YY

IO_L259N

IO_VREF_L259P

IO_L260N_YY

IO_L260P_YY

IO_L261N_Y

IO_L261P_Y

IO_L262N_YY

IO_L262P_YY

IO_L263N

IO_L263P

IO_L264N

IO_L264P

M10

IO_L265N_YY

IO_L265P_YY

IO_L266N_YY

IO_VREF_L266P_YY

IO_L267N_YY

IO_L267P_YY

IO_L268N_YY

IO_L268P_YY

IO_L269N_YY

IO_VREF_L269P_YY

IO_L270N_YY

IO_L270P_YY

IO_L271N

IO_L271P

IO_L272N_YY

IO_L272P_YY

IO_L273N_YY

IO_VREF_L273P_YY

IO_L274N

IO_L274P

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

112

1-800-255-7778

Production Product Specification

IO_L275N_YY

IO_L275P_YY

IO_L276N_YY

IO_L276P_YY

IO_L277N

IO_VREF_L277P

IO_L278N_YY

IO_L278P_YY

IO_L279N_Y

IO_L279P_Y

IO_L280N_YY

IO_VREF_L280P_YY

IO_L281N

IO_L281P

IO_L282N_YY

IO_L282P_YY

K10

CCLK

F26

DONE

AJ28

DXN

AJ3

DXP

AH4

AF4

AC7

AK3

PROGRAM

AG28

TCK

TDI

H22

TDO

D26

TMS

VCCINT

L11

VCCINT

L12

VCCINT

L19

VCCINT

L20

VCCINT

M11

VCCINT

M12

VCCINT

M19

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VCCINT

M20

VCCINT

N13

VCCINT

N14

VCCINT

N15

VCCINT

N16

VCCINT

N17

VCCINT

N18

VCCINT

P13

VCCINT

P18

VCCINT

R13

VCCINT

R18

VCCINT

T13

VCCINT

T18

VCCINT

U13

VCCINT

U18

VCCINT

V13

VCCINT

V14

VCCINT

V15

VCCINT

V16

VCCINT

V17

VCCINT

V18

VCCINT

W11

VCCINT

W12

VCCINT

W19

VCCINT

W20

VCCINT

Y11

VCCINT

Y12

VCCINT

Y19

VCCINT

Y20

VCCO_0

M15

VCCO_0

M14

VCCO_0

L15

VCCO_0

L14

VCCO_0

H14

VCCO_0

M13

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

113

VCCO_0

C12

VCCO_1

B25

VCCO_1

C19

VCCO_1

M18

VCCO_1

M17

VCCO_1

L17

VCCO_1

H17

VCCO_1

L16

VCCO_1

M16

VCCO_2

F29

VCCO_2

M28

VCCO_2

P23

VCCO_2

R20

VCCO_2

P20

VCCO_2

R19

VCCO_2

N19

VCCO_2

P19

VCCO_3

AE29

VCCO_3

W28

VCCO_3

U23

VCCO_3

U20

VCCO_3

T20

VCCO_3

V19

VCCO_3

T19

VCCO_3

U19

VCCO_4

AJ25

VCCO_4

AH19

VCCO_4

W18

VCCO_4

AC17

VCCO_4

Y17

VCCO_4

W17

VCCO_4

W16

VCCO_4

Y16

VCCO_5

AJ6

VCCO_5

Y15

VCCO_5

W15

VCCO_5

AC14

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VCCO_5

Y14

VCCO_5

W14

VCCO_5

W13

VCCO_5

AH12

VCCO_6

AE2

VCCO_6

V12

VCCO_6

U12

VCCO_6

T12

VCCO_6

U11

VCCO_6

T11

VCCO_6

VCCO_7

R12

VCCO_7

P12

VCCO_7

N12

VCCO_7

R11

VCCO_7

P11

VCCO_7

GND

Y18

GND

AH7

GND

AK30

GND

AJ30

GND

B30

GND

A30

GND

AK29

GND

AJ29

GND

AC29

GND

H29

GND

B29

GND

A29

GND

AH28

GND

V28

GND

N28

GND

C28

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

114

1-800-255-7778

Production Product Specification

GND

AG27

GND

D27

GND

AF26

GND

E26

GND

F25

GND

AE25

GND

G24

GND

AJ23

GND

AD24

GND

H23

GND

B23

GND

AC23

GND

AB22

GND

V22

GND

N22

GND

AH18

GND

AB18

GND

J18

GND

C18

GND

U17

GND

T17

GND

R17

GND

P17

GND

U16

GND

T16

GND

R16

GND

P16

GND

U15

GND

T15

GND

R15

GND

P15

GND

U14

GND

T14

GND

R14

GND

P14

GND

AH13

GND

AB13

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

GND

J13

GND

C13

GND

AJ8

GND

AC8

GND

AD7

GND

AE6

GND

AF5

GND

AG4

GND

AK2

GND

AH3

GND

AC2

GND

AK1

GND

AJ2

GND

AJ1

GND

Notes:
1.

REF

or I/O option only in the XCV1000E and XCV1600E;

otherwise, I/O option only.

REF

or I/O option only in the XCV1600E; otherwise, I/O

option only.

I/O option only in the XCV600E.

No Connect in the XCV600E.

No Connect in the XCV600E, 1000E.

Table 26: FG900 -- XCV600E, XCV1000E, XCV1600E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

115

FG900 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

GCLK LVDS

C15

A15

IO_DLL_ 34N

E15

E16

IO_DLL_ 34P

AK16

AH16

IO_DLL_ 177N

AJ16

AF16

IO_DLL_ 177P

IO LVDS

Total Pairs: 283, Asynchronous Output Pairs: 168

VREF

J10

VREF

N11

J11

VREF

H10

F10

G10

H11

VREF

J12

E10

VREF

B10

G11

C10

H12

F11

H13

D11

E11

G12

B11

C11

F12

D12

A10

VREF

A11

E12

B12

G13

K13

A12

B13

F13

VREF

E13

G14

B14

D14

J14

A14

J15

K14

VREF

H15

B15

D15

F15

VREF

E16

A15

IO_ LVDS_DLL

F16

B16

VREF

H16

A16

K15

C16

VREF

G16

K16

E17

A17

C17

F17

A18

E18

VREF

A19

D18

G18

B19

H18

D19

F19

F18

VREF

K17

B20

A20

D20

C20

G19

E20

K18

D21

B21

A21

F20

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

116

1-800-255-7778

Production Product Specification

A22

C21

VREF

B22

H19

D22

E21

C22

F21

VREF

E22

H20

A23

G21

K19

A24

B24

C24

VREF

G22

H21

C25

E23

A26

D24

K20

B26

VREF

J21

D25

F23

C26

G23

B27

VREF

F24

A27

A28

B28

C27

K21

J22

E27

DIN, D0

C29

D28

G25

E25

E28

C30

VREF

K22

F27

D30

J23

L21

F28

VREF

G28

E30

G27

E29

K23

H26

F30

L22

VREF

H27

G29

G30

M21

J24

J26

H30

L23

VREF

K26

J28

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

J29

K24

K27

J30

VREF

M22

K29

K28

L25

N21

K25

L24

L27

L29

M23

L26

L28

L30

M27

VREF

M26

M29

N29

M30

N25

N27

N30

P21

N26

P28

100

P29

N24

101

P22

R26

102

P25

R29

VREF

103

R21

R28

104

R25

T30

VREF

105

P24

R27

106

R24

U29

107

R22

T27

VREF

108

R23

T28

109

T21

T25

VREF

110

U28

U30

111

T23

U27

112

U25

V27

113

U24

V29

VREF

114

W30

U22

115

U21

W29

116

V26

W27

117

W26

Y29

VREF

118

W25

Y30

119

V24

Y28

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

117

120

AA30

W24

121

AA29

V20

122

Y27

W23

123

Y26

AB30

124

V21

AA28

VREF

125

Y25

AA27

126

W22

Y23

127

Y24

AB28

VREF

128

AC30

AA25

129

W21

AA24

130

AB26

AD30

131

Y22

AC27

VREF

132

AD28

AB25

133

AC26

AE30

134

AD27

AF30

135

AF29

AB24

VREF

136

AB23

AE28

137

AG30

AC25

138

AE26

AG29

VREF

139

AH30

AC24

140

AF28

AD25

141

AH29

AA22

INIT

142

AF27

AK28

143

AG26

AH27

144

AD23

AJ27

145

AB21

AF25

VREF

146

AC22

AH26

147

AA21

AG25

148

AJ26

AD22

VREF

149

AA20

AH25

150

AC21

AF24

151

AG24

AK26

152

AJ24

AF23

VREF

153

AE23

AB20

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

154

AC20

AG23

155

AF22

AE22

156

AJ22

AG22

VREF

157

AK24

AD20

158

AA19

AF21

159

AH22

AA18

VREF

160

AG21

AK23

161

AH21

AD19

162

AE20

AJ21

163

AG20

AF20

164

AC18

AF19

165

AJ20

AE19

166

AK22

AH20

VREF

167

AG19

AB17

168

AJ19

AD17

169

AA16

AA17

170

AK21

AB16

VREF

171

AG18

AK20

172

AK19

AD16

173

AE16

AE17

174

AG17

AJ17

VREF

175

AD15

AH17

176

AG16

AK17

VREF

177

AF16

AH16

IO_ LVDS_DLL

178

AC15

AG15

VREF

179

AB15

AF15

180

AA15

AF14

VREF

181

AH15

AK15

182

AB14

AF13

183

AH14

AJ14

184

AE14

AG13

VREF

185

AK13

AD13

186

AE13

AF12

187

AC13

AA13

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

118

1-800-255-7778

Production Product Specification

188

AA12

AJ12

VREF

189

AB12

AE11

190

AK12

Y13

191

AG11

AF11

192

AH11

AJ11

193

AE12

AG10

194

AD12

AK11

195

AJ10

AC12

VREF

196

AK10

AD11

197

AJ9

AE9

198

AH10

AF9

VREF

199

AH9

AK9

200

AF8

AB11

201

AC11

AG8

202

AK8

AF7

VREF

203

AG7

AK7

204

AJ7

AD10

205

AH6

AC10

206

AD9

AG6

VREF

207

AB10

AJ5

208

AD8

AK5

209

AC9

AJ4

VREF

210

AG5

AK4

211

AH5

AG3

212

AC6

AF3

213

AG2

AH2

214

AE4

AB9

215

AH1

AE3

VREF

216

AD6

AB8

217

AA10

AG1

218

AD4

AA9

VREF

219

AD2

AD5

220

AF2

AD3

221

AA7

AA8

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

222

AF1

VREF

223

AC4

AB6

224

AE1

225

AB4

226

AB3

VREF

227

W10

AA5

228

V10

AB1

229

AC1

VREF

230

AA3

V11

231

U10

AA2

232

AA6

233

234

AA1

235

236

VREF

237

238

239

240

AB2

VREF

241

242

243

244

VREF

245

246

VREF

247

R10

248

249

VREF

250

251

P10

VREF

252

253

254

255

VREF

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

119

FG1156 Fine-Pitch Ball Grid Array Package

XCV1000E, XCV1600E, XCV2000E, XCV2600E, and
XCV3200E devices in the FG1156 fine-pitch Ball Grid Array
package have footprint compatibility. Pins labeled IO_VREF
can be used as either V

REF

or general I/O, unless indicated

in the footnotes. If the pin is not used as V

REF

, it can be used

as general I/O. Immediately following

Table 28

, see

Table 29

for Differential Pair information.

256

257

258

259

VREF

260

261

262

263

264

M10

265

266

VREF

267

268

269

VREF

270

271

272

273

VREF

274

275

276

277

VREF

278

279

280

VREF

281

282

K10

Notes:
1.

AO in the XCV600E, 1000E.

AO in the XCV1000E.

AO in the XCV1600E.

AO in the XCV1000E, XCV1600E.

Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E

Pair

Bank

Pin

Other

Functions

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

GCK3

E17

B10

D16

E11

E13

E16

F17

J12

J13

J14

K11

IO_L0N_Y

IO_L0P_Y

IO_L1N_Y

IO_L1P_Y

J10

IO_VREF_L2N_Y

IO_L2P_Y

IO_L3N_Y

IO_L3P_Y

IO_L4N_YY

IO_L4P_YY

J11

IO_VREF_L5N_YY

IO_L5P_YY

IO_L6N_YY

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

120

1-800-255-7778

Production Product Specification

IO_L6P_YY

H10

IO_L7N_Y

IO_L7P_Y

IO_L8N_Y

K12

IO_L8P_Y

IO_L9N

IO_L9P

IO_L10N_YY

G10

IO_L10P_YY

IO_VREF_L11N_YY

IO_L11P_YY

IO_L12N

H11

IO_L12P

IO_L13N_Y

IO_L13P_Y

IO_VREF_L14N_Y

K13

IO_L14P_Y

G11

IO_L15N

IO_L15P

F10

IO_L16N_YY

IO_L16P_YY

H12

IO_VREF_L17N_YY

D10

IO_L17P_YY

IO_L18N_Y

F11

IO_L18P_Y

A10

IO_L19N_Y

K14

IO_L19P_Y

C10

IO_VREF_L20N_YY

H13

IO_L20P_YY

G12

IO_L21N_YY

A11

IO_L21P_YY

B11

IO_L22N_Y

E12

IO_L22P_Y

D11

IO_L23N_Y

G13

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L23P_Y

C12

IO_L24N_Y

K15

IO_L24P_Y

A12

IO_L25N_Y

B12

IO_L25P_Y

H14

IO_L26N_YY

D12

IO_L26P_YY

F13

IO_VREF_L27N_YY

A13

IO_L27P_YY

B13

IO_L28N_YY

J15

IO_L28P_YY

G14

IO_L29N_Y

C13

IO_L29P_Y

F14

IO_L30N_Y

H15

IO_L30P_Y

D13

IO_L31N

A14

IO_L31P

K16

IO_L32N_YY

E14

IO_L32P_YY

B14

IO_VREF_L33N_YY

G15

IO_L33P_YY

D14

IO_L34N

J16

IO_L34P

D15

IO_L35N_Y

F15

IO_L35P_Y

B15

IO_L36N_Y

A15

IO_L36P_Y

E15

IO_L37N

G16

IO_L37P

A16

IO_L38N_YY

F16

IO_L38P_YY

J17

IO_VREF_L39N_YY

C16

IO_L39P_YY

B16

IO_L40N_Y

H17

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

121

IO_L40P_Y

A17

IO_VREF_L41N_Y

G17

IO_L41P_Y

B17

IO_LVDS_DLL_L42N

C17

GCK2

D17

A18

B18

B24

B25

E22

E23

D18

D19

D25

D26

D28

D29

G23

J23

IO_LVDS_DLL_L42P

J18

IO_L43N_Y

G18

IO_VREF_L43P_Y

C18

IO_L44N_Y

H18

IO_L44P_Y

F18

IO_L45N_YY

B19

IO_VREF_L45P_YY

A19

IO_L46N_YY

K19

IO_L46P_YY

C19

IO_L47N

F19

IO_L47P

E19

IO_L48N_Y

G19

IO_L48P_Y

J19

IO_L49N_Y

A20

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L49P_Y

G20

IO_L50N

B20

IO_L50P

F20

IO_L51N_YY

D20

IO_VREF_L51P_YY

E20

IO_L52N_YY

H20

IO_L52P_YY

A21

IO_L53N

E21

IO_L53P

J20

IO_L54N_Y

D21

IO_L54P_Y

K20

IO_L55N_Y

B21

IO_L55P_Y

H21

IO_L56N_YY

G21

IO_L56P_YY

F21

IO_L57N_YY

A22

IO_VREF_L57P_YY

B22

IO_L58N_YY

J21

IO_L58P_YY

C22

IO_L59N_Y

D22

IO_L59P_Y

G22

IO_L60N_Y

K21

IO_L60P_Y

A23

IO_L61N_Y

F22

IO_L61P_Y

B23

IO_L62N_Y

C23

IO_L62P_Y

H22

IO_L63N_YY

D23

IO_L63P_YY

K22

IO_L64N_YY

A24

IO_VREF_L64P_YY

J22

IO_L65N_Y

H23

IO_L65P_Y

D24

IO_L66N_Y

A25

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

122

1-800-255-7778

Production Product Specification

IO_L66P_Y

E24

IO_L67N_YY

A26

IO_VREF_L67P_YY

C25

IO_L68N_YY

F24

IO_L68P_YY

B26

IO_L69N

K23

IO_L69P

F25

IO_L70N_Y

C26

IO_VREF_L70P_Y

H24

IO_L71N_Y

G24

IO_L71P_Y

A27

IO_L72N

B27

IO_L72P

G25

IO_L73N_YY

E26

IO_VREF_L73P_YY

C27

IO_L74N_YY

J24

IO_L74P_YY

B28

IO_L75N

K24

IO_L75P

H25

IO_L76N_Y

D27

IO_L76P_Y

F26

IO_L77N_Y

G26

IO_L77P_Y

C28

IO_L78N_YY

E27

IO_L78P_YY

J25

IO_L79N_YY

A30

IO_VREF_L79P_YY

H26

IO_L80N_YY

G27

IO_L80P_YY

B29

IO_L81N_Y

F27

IO_L81P_Y

C29

IO_L82N_Y

E28

IO_VREF_L82P_Y

F28

IO_L83N_Y

L25

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L83P_Y

B30

IO_L84N

B31

IO_L84P

E29

IO_WRITE_L85N_YY

A31

IO_CS_L85P_YY

D30

F31

J32

K27

K31

L28

L30

M32

N26

N28

P25

U26

U30

U32

U34

IO_D2

M30

IO_DOUT_BUSY_L86P_YY

D32

IO_DIN_D0_L86N_YY

J27

IO_L87P_Y

E31

IO_L87N_Y

F30

IO_L88P_Y

G29

IO_L88N_Y

F32

IO_VREF_L89P_Y

E32

IO_L89N_Y

G30

IO_L90P

M25

IO_L90N

G31

IO_L91P_Y

L26

IO_L91N_Y

D33

IO_VREF_L92P_Y

D34

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

123

IO_L92N_Y

H29

IO_L93P_YY

J28

IO_L93N_YY

E33

IO_L94P_YY

H28

IO_L94N_YY

H30

IO_L95P_Y

H32

IO_L95N_Y

K28

IO_L96P_Y

L27

IO_L96N_Y

F33

IO_L97P_Y

M26

IO_L97N_Y

E34

IO_VREF_L98P_YY

H31

IO_L98N_YY

G32

IO_L99P_YY

N25

IO_L99N_YY

J31

IO_L100P_YY

J30

IO_L100N_YY

G33

IO_VREF_L101P_Y

H34

IO_L101N_Y

J29

IO_L102P

M27

IO_L102N

H33

IO_L103P_Y

K29

IO_L103N_Y

J34

IO_VREF_L104P_YY

L29

IO_L104N_YY

J33

IO_L105P_YY

M28

IO_L105N_YY

K34

IO_L106P_Y

N27

IO_L106N_Y

L34

IO_VREF_L107P_YY

K33

IO_D1_L107N_YY

P26

IO_L108P_Y

R25

IO_L108N_Y

M34

IO_L109P_Y

L31

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L109N_Y

L33

IO_L110P_Y

P27

IO_L110N_Y

M33

IO_L111P

M31

IO_L111N

R26

IO_L112P_Y

N30

IO_L112N_Y

P28

IO_VREF_L113P_Y

N29

IO_L113N_Y

N33

IO_L114P_YY

T25

IO_L114N_YY

N34

IO_L115P_YY

P34

IO_L115N_YY

R27

IO_L116P_Y

P29

IO_L116N_Y

P31

IO_L117P_Y

P33

IO_L117N_Y

T26

IO_L118P_Y

R34

IO_L118N_Y

R28

IO_VREF_L119P_YY

N31

IO_D3_L119N_YY

N32

IO_L120P_YY

P30

IO_L120N_YY

R33

IO_L121P_YY

R29

IO_L121N_YY

T34

IO_L122P_Y

R30

IO_L122N_Y

T30

IO_L123P

T28

IO_L123N

R31

IO_L124P_Y

T29

IO_L124N_Y

U27

IO_VREF_L125P_YY

T31

IO_L125N_YY

T33

IO_L126P_YY

U28

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

124

1-800-255-7778

Production Product Specification

IO_L126N_YY

T32

IO_VREF_L127P_Y

U29

IO_L127N_Y

U33

IO_L128P_YY

V33

IO_L128N_YY

U31

V27

V31

V32

W33

AB25

AB26

AB31

AC31

AF34

AG31

AG33

AG34

AH29

AJ30

IO_L129P_Y

V26

IO_VREF_L129N_Y

V30

IO_L130P_YY

W34

IO_L130N_YY

V28

IO_L131P_YY

W32

IO_VREF_L131N_YY

W30

IO_L132P_Y

V29

IO_L132N_Y

Y34

IO_L133P

W29

IO_L133N

Y33

IO_L134P_Y

W26

IO_L134N_Y

W28

IO_L135P_YY

Y31

IO_L135N_YY

Y30

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L136P_YY

AA34

IO_L136N_YY

W31

IO_D4_L137P_YY

AA33

IO_VREF_L137N_YY

Y29

IO_L138P_Y

W25

IO_L138N_Y

AB34

IO_L139P_Y

Y28

IO_L139N_Y

AB33

IO_L140P_Y

AA30

IO_L140N_Y

Y26

IO_L141P_YY

Y27

IO_L141N_YY

AA31

IO_L142P_YY

AA27

IO_L142N_YY

AA29

IO_L143P_Y

AB32

IO_VREF_L143N_Y

AB29

IO_L144P_Y

AA28

IO_L144N_Y

AC34

IO_L145P

Y25

IO_L145N

AD34

IO_L146P_Y

AB30

IO_L146N_Y

AC33

IO_L147P_Y

AA26

IO_L147N_Y

AC32

IO_L148P_Y

AD33

IO_L148N_Y

AB28

IO_L149P_YY

AE34

IO_D5_L149N_YY

AB27

IO_D6_L150P_YY

AE33

IO_VREF_L150N_YY

AC30

IO_L151P_Y

AA25

IO_L151N_Y

AE32

IO_L152P_YY

AE31

IO_L152N_YY

AD29

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

125

IO_L153P_YY

AD31

IO_VREF_L153N_YY

AF33

IO_L154P_Y

AC28

IO_L154N_Y

AF31

IO_L155P_Y

AC27

IO_L155N_Y

AF32

IO_L156P_Y

AE29

IO_VREF_L156N_Y

AD28

IO_L157P_YY

AD30

IO_L157N_YY

AG32

IO_L158P_YY

AC26

IO_L158N_YY

AH33

IO_L159P_YY

AD26

IO_VREF_L159N_YY

AF30

IO_L160P_Y

AC25

IO_L160N_Y

AH32

IO_L161P_Y

AE28

IO_L161N_Y

AL34

IO_L162P_Y

AG30

IO_L162N_Y

AD27

IO_L163P_YY

AF29

IO_L163N_YY

AK34

IO_L164P_YY

AD25

IO_L164N_YY

AE27

IO_L165P_Y

AJ33

IO_VREF_L165N_Y

AH31

IO_L166P_Y

AE26

IO_L166N_Y

AL33

IO_L167P

AF28

IO_L167N

AL32

IO_L168P_Y

AJ31

IO_VREF_L168N_Y

AF27

IO_L169P_Y

AG29

IO_L169N_Y

AJ32

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L170P_Y

AK33

IO_L170N_Y

AH30

IO_D7_L171P_YY

AK32

IO_INIT_L171N_YY

AK31

V34

GCK0

AH18

AE21

AG18

AG23

AH24

AH25

AJ28

AK18

AK19

AL25

AL27

AL30

AN18

AN22

AN24

IO_L172P_YY

AP31

IO_L172N_YY

AK29

IO_L173P_Y

AP30

IO_L173N_Y

AN31

IO_L174P_Y

AH27

IO_L174N_Y

AN30

IO_VREF_L175P_Y

AM30

IO_L175N_Y

AK28

IO_L176P_Y

AG26

IO_L176N_Y

AN29

IO_L177P_YY

AF25

IO_L177N_YY

AM29

IO_VREF_L178P_YY

AL29

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

126

1-800-255-7778

Production Product Specification

IO_L178N_YY

AL28

IO_L179P_YY

AE24

IO_L179N_YY

AN28

IO_L180P_Y

AJ27

IO_L180N_Y

AH26

IO_L181P_Y

AG25

IO_L181N_Y

AK27

IO_L182P

AM28

IO_L182N

AF24

IO_L183P_YY

AJ26

IO_L183N_YY

AP27

IO_VREF_L184P_YY

AK26

IO_L184N_YY

AN27

IO_L185P

AE23

IO_L185N

AM27

IO_L186P_Y

AL26

IO_L186N_Y

AP26

IO_VREF_L187P_Y

AN26

IO_L187N_Y

AJ25

IO_L188P

AG24

IO_L188N

AP25

IO_L189P_YY

AF23

IO_L189N_YY

AM26

IO_VREF_L190P_YY

AJ24

IO_L190N_YY

AN25

IO_L191P_Y

AE22

IO_L191N_Y

AM25

IO_L192P_Y

AK24

IO_L192N_Y

AH23

IO_VREF_L193P_YY

AF22

IO_L193N_YY

AP24

IO_L194P_YY

AL24

IO_L194N_YY

AK23

IO_L195P_Y

AG22

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L195N_Y

AN23

IO_L196P_Y

AP23

IO_L196N_Y

AM23

IO_L197P_Y

AH22

IO_L197N_Y

AP22

IO_L198P_Y

AL23

IO_L198N_Y

AF21

IO_L199P_YY

AL22

IO_L199N_YY

AJ22

IO_VREF_L200P_YY

AK22

IO_L200N_YY

AM22

IO_L201P_YY

AG21

IO_L201N_YY

AJ21

IO_L202P_Y

AP21

IO_L202N_Y

AE20

IO_L203P_Y

AH21

IO_L203N_Y

AL21

IO_L204P

AN21

IO_L204N

AF20

IO_L205P_YY

AK21

IO_L205N_YY

AP20

IO_VREF_L206P_YY

AE19

IO_L206N_YY

AN20

IO_L207P_Y

AG20

IO_L207N_Y

AL20

IO_L208P_Y

AH20

IO_L208N_Y

AK20

IO_L209P_Y

AN19

IO_L209N_Y

AJ20

IO_L210P

AF19

IO_L210N

AP19

IO_L211P_YY

AM19

IO_L211N_YY

AH19

IO_VREF_L212P_YY

AJ19

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

127

IO_L212N_YY

AP18

IO_L213P_Y

AF18

IO_L213N_Y

AP17

IO_VREF_L214P_Y

AJ18

IO_L214N_Y

AL18

IO_LVDS_DLL_L215P

AM18

GCK1

AL19

AF17

AG12

AH12

AJ10

AJ11

AK7

AK13

AL13

AM4

AN9

AN10

AN16

AN17

IO_LVDS_DLL_L215N

AL17

IO_L216P_Y

AH17

IO_VREF_L216N_Y

AM17

IO_L217P_Y

AJ17

IO_L217N_Y

AG17

IO_L218P_YY

AP16

IO_VREF_L218N_YY

AL16

IO_L219P_YY

AJ16

IO_L219N_YY

AM16

IO_L220P

AK16

IO_L220N

AP15

IO_L221P_Y

AL15

IO_L221N_Y

AH16

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L222P_Y

AN15

IO_L222N_Y

AF16

IO_L223P_Y

AP14

IO_L223N_Y

AE16

IO_L224P_YY

AK15

IO_VREF_L224N_YY

AJ15

IO_L225P_YY

AH15

IO_L225N_YY

AN14

IO_L226P

AK14

IO_L226N

AG15

IO_L227P_Y

AM13

IO_L227N_Y

AF15

IO_L228P_Y

AG14

IO_L228N_Y

AP13

IO_L229P_YY

AE14

IO_L229N_YY

AE15

IO_L230P_YY

AN13

IO_VREF_L230N_YY

AG13

IO_L231P_YY

AH14

IO_L231N_YY

AP12

IO_L232P_Y

AJ14

IO_L232N_Y

AL14

IO_L233P_Y

AF13

IO_L233N_Y

AN12

IO_L234P_Y

AF14

IO_L234N_Y

AP11

IO_L235P_Y

AN11

IO_L235N_Y

AH13

IO_L236P_YY

AM12

IO_L236N_YY

AL12

IO_L237P_YY

AJ13

IO_VREF_L237N_YY

AP10

IO_L238P_Y

AK12

IO_L238N_Y

AM10

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

128

1-800-255-7778

Production Product Specification

IO_L239P_Y

AP9

IO_L239N_Y

AK11

IO_L240P_YY

AL11

IO_VREF_L240N_YY

AL10

IO_L241P_YY

AE13

IO_L241N_YY

AM9

IO_L242P

AF12

IO_L242N

AP8

IO_L243P_Y

AL9

IO_VREF_L243N_Y

AH11

IO_L244P_Y

AF11

IO_L244N_Y

AN8

IO_L245P_Y

AM8

IO_L245N_Y

AG11

IO_L246P_YY

AL8

IO_VREF_L246N_YY

AK9

IO_L247P_YY

AH10

IO_L247N_YY

AN7

IO_L248P

AE12

IO_L248N

AJ9

IO_L249P_Y

AM7

IO_L249N_Y

AL7

IO_L250P_Y

AG10

IO_L250N_Y

AN6

IO_L251P_YY

AK8

IO_L251N_YY

AH9

IO_L252P_YY

AP5

IO_VREF_L252N_YY

AJ8

IO_L253P_YY

AE11

IO_L253N_YY

AN5

IO_L254P_Y

AF10

IO_L254N_Y

AM6

IO_L255P_Y

AL6

IO_VREF_L255N_Y

AG9

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L256P_Y

AH8

IO_L256N_Y

AP4

IO_L257P_Y

AN4

IO_L257N_Y

AJ7

IO_L258P_YY

AM5

IO_L258N_YY

AK6

AA10

AB5

AB7

AB9

AD7

AD8

AE2

AE4

AJ4

AH5

IO_L259N_YY

AH6

IO_L259P_YY

AF8

IO_L260N_Y

AE9

IO_L260P_Y

AK3

IO_L261N_Y

AD10

IO_L261P_Y

AL2

IO_VREF_L262N_Y

AL1

IO_L262P_Y

AH4

IO_L263N

AG6

IO_L263P

AK1

IO_L264N_Y

AF7

IO_L264P_Y

AK2

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

129

IO_VREF_L265N_Y

AJ3

IO_L265P_Y

AG5

IO_L266N_YY

AD9

IO_L266P_YY

AJ2

IO_L267N_YY

AC10

IO_L267P_YY

AH2

IO_L268N_Y

AH3

IO_L268P_Y

AF5

IO_L269N_Y

AE8

IO_L269P_Y

AG3

IO_L270N_Y

AE7

IO_L270P_Y

AG2

IO_VREF_L271N_YY

AF6

IO_L271P_YY

AG1

IO_L272N_YY

AC9

IO_L272P_YY

AG4

IO_L273N_YY

AE6

IO_L273P_YY

AF3

IO_VREF_L274N_Y

AF1

IO_L274P_Y

AF4

IO_L275N

AB10

IO_L275P

AF2

IO_L276N_Y

AC8

IO_L276P_Y

AE1

IO_VREF_L277N_YY

AD5

IO_L277P_YY

AE3

IO_L278N_YY

AC7

IO_L278P_YY

AD1

IO_L279N_Y

AD6

IO_L279P_Y

AD2

IO_VREF_L280N_YY

AB8

IO_L280P_YY

AC1

IO_L281N_YY

AC5

IO_L281P_YY

AC2

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L282N_Y

AA9

IO_L282P_Y

AC3

IO_L283N_Y

AC4

IO_L283P_Y

AD4

IO_L284N_Y

AA8

IO_L284P_Y

AB6

IO_L285N

AB1

IO_L285P

Y10

IO_L286N_Y

AB2

IO_L286P_Y

AA7

IO_VREF_L287N_Y

AA4

IO_L287P_Y

AA1

IO_L288N_YY

IO_L288P_YY

AB4

IO_L289N_YY

AA2

IO_L289P_YY

IO_L290N_Y

AA6

IO_L290P_Y

AA5

IO_L291N_Y

AB3

IO_L291P_Y

IO_L292N_Y

IO_L292P_Y

W10

IO_VREF_L293N_YY

IO_L293P_YY

IO_L294N_YY

IO_L294P_YY

IO_L295N_YY

IO_L295P_YY

IO_L296N_Y

IO_L296P_Y

IO_L297N_Y

IO_L297P_Y

IO_L298N_Y

IO_L298P_Y

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

130

1-800-255-7778

Production Product Specification

IO_VREF_L299N_YY

IO_L299P_YY

IO_L300N_YY

IO_L300P_YY

IO_VREF_L301N_Y

IO_L301P_Y

M10

N10

IO_L302N_YY

IO_L302P_YY

IO_L303N_Y

IO_VREF_L303P_Y

IO_L304N_YY

IO_L304P_YY

IO_L305N_YY

IO_VREF_L305P_YY

IO_L306N_Y

IO_L306P_Y

IO_L307N_Y

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_L307P_Y

IO_L308N_Y

IO_L308P_Y

T10

IO_L309N_YY

IO_L309P_YY

IO_L310N_YY

IO_VREF_L310P_YY

IO_L311N_Y

IO_L311P_Y

IO_L312N_Y

IO_L312P_Y

IO_L313N_Y

IO_L313P_Y

R10

IO_L314N_YY

IO_L314P_YY

IO_L315N_YY

IO_L315P_YY

IO_L316N_Y

IO_VREF_L316P_Y

IO_L317N_Y

IO_L317P_Y

IO_L318N

IO_L318P

IO_L319N_Y

IO_L319P_Y

IO_L320N_Y

P10

IO_L320P_Y

IO_L321N_Y

IO_L321P_Y

IO_L322N_YY

IO_L322P_YY

IO_L323N_YY

IO_VREF_L323P_YY

IO_L324N_Y

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

131

IO_L324P_Y

IO_L325N_YY

IO_L325P_YY

IO_L326N_YY

IO_VREF_L326P_YY

IO_L327N_Y

IO_L327P_Y

IO_L328N_Y

IO_L328P_Y

IO_L329N_Y

IO_VREF_L329P_Y

IO_L330N_YY

IO_L330P_YY

IO_L331N_YY

IO_L331P_YY

IO_L332N_YY

IO_VREF_L332P_YY

IO_L333N_Y

IO_L333P_Y

IO_L334N_Y

IO_L334P_Y

IO_L335N_Y

IO_L335P_Y

IO_L336N_YY

IO_L336P_YY

IO_L337N_YY

IO_L337P_YY

L10

IO_L338N_Y

IO_VREF_L338P_Y_Y

IO_L339N_Y

IO_L339P_Y

IO_L340N

IO_L340P

IO_L341N_Y

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

IO_VREF_L341P_Y

IO_L342N_Y

IO_L342P_Y

IO_L343N_Y

IO_L343P_Y

CCLK

C31

DONE

AM31

DXN

AJ5

DXP

AL5

AK4

AG7

AL3

PROGRAM

AG28

TCK

TDI

C30

TDO

K26

TMS

VCCINT

K10

VCCINT

K17

VCCINT

K18

VCCINT

K25

VCCINT

L11

VCCINT

L24

VCCINT

M12

VCCINT

M23

VCCINT

N13

VCCINT

N14

VCCINT

N15

VCCINT

N16

VCCINT

N19

VCCINT

N20

VCCINT

N21

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

132

1-800-255-7778

Production Product Specification

VCCINT

N22

VCCINT

P13

VCCINT

P22

VCCINT

R13

VCCINT

R22

VCCINT

T13

VCCINT

T22

VCCINT

U10

VCCINT

U25

VCCINT

V10

VCCINT

V25

VCCINT

W13

VCCINT

W22

VCCINT

Y13

VCCINT

Y22

VCCINT

AA13

VCCINT

AA22

VCCINT

AB13

VCCINT

AB14

VCCINT

AB15

VCCINT

AB16

VCCINT

AB19

VCCINT

AB20

VCCINT

AB21

VCCINT

AB22

VCCINT

AC12

VCCINT

AC23

VCCINT

AD24

VCCINT

AD11

VCCINT

AE10

VCCINT

AE17

VCCINT

AE18

VCCINT

AE25

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VCCO_0

M17

VCCO_0

L17

VCCO_0

L16

VCCO_0

E10

VCCO_0

C14

VCCO_0

M13

VCCO_0

M14

VCCO_0

M15

VCCO_0

M16

VCCO_0

L12

VCCO_0

L13

VCCO_0

L14

VCCO_0

L15

VCCO_1

M18

VCCO_1

L18

VCCO_1

L23

VCCO_1

E25

VCCO_1

C21

VCCO_1

A29

VCCO_1

M19

VCCO_1

M20

VCCO_1

M21

VCCO_1

M22

VCCO_1

L19

VCCO_1

L20

VCCO_1

L21

VCCO_1

L22

VCCO_2

U24

VCCO_2

U23

VCCO_2

N24

VCCO_2

M24

VCCO_2

K30

VCCO_2

F34

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

133

VCCO_2

T23

VCCO_2

T24

VCCO_2

R23

VCCO_2

R24

VCCO_2

P23

VCCO_2

P24

VCCO_2

P32

VCCO_2

N23

VCCO_3

V23

VCCO_3

V24

VCCO_3

Y23

VCCO_3

Y24

VCCO_3

W23

VCCO_3

W24

VCCO_3

AJ34

VCCO_3

AE30

VCCO_3

AC24

VCCO_3

AB23

VCCO_3

AB24

VCCO_3

AA23

VCCO_3

AA24

VCCO_3

AA32

VCCO_4

AD18

VCCO_4

AC18

VCCO_4

AC19

VCCO_4

AC20

VCCO_4

AC21

VCCO_4

AC22

VCCO_4

AP29

VCCO_4

AM21

VCCO_4

AK25

VCCO_4

AD19

VCCO_4

AD20

VCCO_4

AD21

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VCCO_4

AD22

VCCO_4

AD23

VCCO_5

AC17

VCCO_5

AD17

VCCO_5

AC13

VCCO_5

AC14

VCCO_5

AC15

VCCO_5

AC16

VCCO_5

AP6

VCCO_5

AM14

VCCO_5

AK10

VCCO_5

AD12

VCCO_5

AD13

VCCO_5

AD14

VCCO_5

AD15

VCCO_5

AD16

VCCO_6

V11

VCCO_6

V12

VCCO_6

Y11

VCCO_6

Y12

VCCO_6

W11

VCCO_6

W12

VCCO_6

AJ1

VCCO_6

AE5

VCCO_6

AC11

VCCO_6

AB11

VCCO_6

AB12

VCCO_6

AA3

VCCO_6

AA11

VCCO_6

AA12

VCCO_7

U11

VCCO_7

U12

VCCO_7

N12

VCCO_7

M11

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

134

1-800-255-7778

Production Product Specification

VCCO_7

T11

VCCO_7

T12

VCCO_7

R11

VCCO_7

R12

VCCO_7

P11

VCCO_7

P12

VCCO_7

N11

GND

K32

GND

AN1

GND

AM11

GND

AK5

GND

AH28

GND

AD32

GND

AA20

GND

Y20

GND

W19

GND

V19

GND

U20

GND

T20

GND

R19

GND

P19

GND

F12

GND

AP1

GND

AN2

GND

AM15

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

GND

AK17

GND

AH34

GND

AC6

GND

AA21

GND

Y21

GND

W20

GND

V20

GND

U21

GND

T21

GND

R20

GND

P20

GND

H16

GND

F23

GND

A28

GND

AP34

GND

AM3

GND

AL31

GND

AH7

GND

AD3

GND

AA19

GND

Y19

GND

W18

GND

V18

GND

U19

GND

T19

GND

R18

GND

P18

GND

J26

GND

C34

GND

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

135

GND

AP2

GND

AN3

GND

AM20

GND

AK30

GND

AG8

GND

AC29

GND

Y32

GND

W21

GND

V21

GND

T27

GND

R21

GND

P21

GND

H19

GND

F29

GND

C11

GND

A32

GND

AP3

GND

AN32

GND

AM24

GND

AJ6

GND

AG16

GND

AA14

GND

Y14

GND

W27

GND

U14

GND

T14

GND

R32

GND

H27

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

GND

C15

GND

B32

GND

A33

GND

AP7

GND

AN33

GND

AM32

GND

AJ12

GND

AG19

GND

AA15

GND

Y15

GND

W14

GND

V14

GND

U15

GND

T15

GND

R14

GND

P14

GND

M29

GND

E18

GND

C20

GND

B33

GND

A34

GND

AP28

GND

AN34

GND

AM33

GND

AJ23

GND

AG27

GND

AA16

GND

Y16

GND

W15

GND

V15

GND

U16

GND

T16

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

136

1-800-255-7778

Production Product Specification

GND

R15

GND

P15

GND

E30

GND

C24

GND

B34

GND

AP32

GND

AM1

GND

AM34

GND

AJ29

GND

AF9

GND

AA17

GND

Y17

GND

W16

GND

V16

GND

U17

GND

T17

GND

R16

GND

P16

GND

L32

GND

G28

GND

C32

GND

AP33

GND

AM2

GND

AL4

GND

AH1

GND

AF26

GND

AA18

GND

Y18

GND

W17

GND

V17

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

GND

U18

GND

T18

GND

R17

GND

P17

GND

G34

GND

D31

GND

C33

GND

AB17

GND

AB18

GND

N17

GND

N18

GND

U13

GND

V13

GND

U22

GND

V22

Notes:

REF

or I/O option only in the XCV1600E, XCV2000E,

XCV2600E, and XCV3200E; otherwise, I/O option only.

REF

or I/O option only in the XCV2000E, XCV2600E, and

XCV3200E; otherwise, I/O option only.

No Connect in the XCV1000E, XCV1600E.

No Connect in the XCV1000E.

I/O in the XCV1000E.

Table 28: FG1156 -- XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E

Bank

Pin Description

Pin #

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

137

FG1156 Differential Pin Pairs

Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. The
AO column in

Table 29

indicates which devices in this pack-

age can use the pin pair as an asynchronous output. The
"Other Functions" column indicates alternative function(s)
that are not available when the pair is used as a differential
pair or differential clock

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

GCLK LVDS

E17

C17

IO_DLL_L 42N

D17

J18

IO_DLL_L 42P

AL19

AL17

IO_DLL_L 215N

AH18

AM18

IO_DLL_L 215P

IO LVDS

Total Pairs: 344, Asynchronous Output Pairs: 134

3200 1600

1000

J10

3200 2000

1000

3200 2000

1000

VREF

3200 2600

1000

J11

3200 2600
2000 1600

1000

3200 2600
2000 1600

1000

VREF

H10

2000 1600

3200 1000

K12

3200 1000

3200 2600

G10

3200 2600
2000 1600

1000

3200 2600
2000 1600

1000

VREF

H11

3200 1600

3200 2000

1000

G11

K13

3200 2000

1000

VREF

F10

3200 2600

H12

3200 2600
2000 1600

1000

D10

3200 2600
2000 1600

1000

VREF

A10

F11

2600 1600

1000

C10

K14

2600 1600

1000

G12

H13

3200 2600
2000 1600

1000

VREF

B11

A11

3200 2600
2000 1600

1000

D11

E12

3200 1600

1000

C12

G13

3200 2000

1000

A12

K15

3200 2000

1000

H14

B12

3200 2600

1000

F13

D12

3200 2600
2000 1600

1000

B13

A13

3200 2600
2000 1600

1000

VREF

G14

J15

2000 1600

F14

C13

3200 2600

1000

D13

H15

3200 2600

1000

K16

A14

3200 -

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

138

1-800-255-7778

Production Product Specification

B14

E14

3200 2600
2000 1600

1000

D14

G15

3200 2600
2000 1600

1000

VREF

D15

J16

3200 1600

B15

F15

3200 2000

1000

E15

A15

3200 2000

1000

A16

G16

3200 2600

J17

F16

3200 2600
2000 1600

1000

B16

C16

3200 2600
2000 1600

1000

VREF

A17

H17

2600 1600

1000

B17

G17

2600 1600

1000

VREF

J18

C17

None

IO_LVDS_DLL

C18

G18

2600 1600

1000

VREF

F18

H18

2600 1600

1000

A19

B19

3200 2600
2000 1600

1000

VREF

C19

K19

3200 2600
2000 1600

1000

E19

F19

3200 2600

J19

G19

3200 2000

1000

G20

A20

3200 2000

1000

F20

B20

3200 1600

E20

D20

3200 2600
2000 1600

1000

VREF

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

A21

H20

3200 2600
2000 1600

1000

J20

E21

3200 -

K20

D21

3200 2600

1000

H21

B21

3200 2600

1000

F21

G21

2000 1600

B22

A22

3200 2600
2000 1600

1000

VREF

C22

J21

3200 2600
2000 1600

1000

G22

D22

3200 2600

1000

A23

K21

3200 2000

1000

B23

F22

3200 2000

1000

H22

C23

3200 1600

1000

K22

D23

3200 2600
2000 1600

1000

J22

A24

3200 2600
2000 1600

1000

VREF

D24

H23

2600 1600

1000

E24

A25

2600 1600

1000

C25

A26

3200 2600
2000 1600

1000

VREF

B26

F24

3200 2600
2000 1600

1000

F25

K23

3200 2600

H24

C26

3200 2000

1000

VREF

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

139

A27

G24

3200 2000

1000

G25

B27

3200 1600

C27

E26

3200 2600
2000 1600

1000

VREF

B28

J24

3200 2600
2000 1600

1000

H25

K24

3200 2600

F26

D27

3200 1000

C28

G26

3200 1000

J25

E27

2000 1600

H26

A30

3200 2600
2000 1600

1000

VREF

B29

G27

3200 2600
2000 1600

1000

C29

F27

3200 2600

1000

F28

E28

3200 2000

1000

VREF

B30

L25

3200 2000

1000

E29

B31

3200 1600

1000

D30

A31

3200 2600
2000 1600

1000

D32

J27

3200 2600
2000 1600

1000

DIN, D0

E31

F30

3200 2600

2000

G29

F32

2600 2000

1000

E32

G30

3200 2600
1600 1000

VREF

M25

G31

2600 1600

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

L26

D33

3200 2600
1600 1000

D34

H29

2600 2000

1000

VREF

J28

E33

3200 2600
2000 1600

H28

H30

3200 2600
2000 1600

1000

H32

K28

3200 2600
1600 1000

L27

F33

3200 2600

2000

M26

E34

2600 2000

1000

H31

G32

3200 2600
2000 1600

1000

VREF

N25

J31

2000 1600

100

J30

G33

3200 2600
2000 1600

1000

101

H34

J29

2600 1000

VREF

102

M27

H33

3200 2600

1600

103

K29

J34

3200 2600
1600 1000

104

L29

J33

3200 2600
2000 1600

1000

VREF

105

M28

K34

3200 2600
2000 1600

1000

106

N27

L34

3200 1600

1000

107

K33

P26

2000 1600

1000

108

R25

M34

3200 2600

2000

109

L31

L33

2000 1000

110

P27

M33

3200 2600
1600 1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

140

1-800-255-7778

Production Product Specification

111

M31

R26

2600 1600

112

N30

P28

3200 1600

1000

113

N29

N33

2600 2000

1000

VREF

114

T25

N34

3200 2600
2000 1600

115

P34

R27

3200 2600
2000 1600

1000

116

P29

P31

3200 2600
1600 1000

117

P33

T26

3200 2600

2000

118

R34

R28

2600 2000

1000

119

N31

N32

2000 1600

1000

120

P30

R33

2000 1600

121

R29

T34

3200 2600
2000 1600

1000

122

R30

T30

1000 -

123

T28

R31

3200 1600

124

T29

U27

3200 2600
1600 1000

125

T31

T33

2000 1600

1000

VREF

126

U28

T32

2000 1600

1000

127

U29

U33

3200 2600
1600 1000

VREF

128

V33

U31

3200 2600
2000 1600

1000

129

V26

V30

3200 2600
1600 1000

VREF

130

W34

V28

2000 1600

1000

131

W32

W30

2000 1600

1000

VREF

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

132

V29

Y34

3200 2600
1600 1000

133

W29

Y33

3200 1600

134

W26

W28

1000 -

135

Y31

Y30

3200 2600
2000 1600

1000

136

AA34

W31

2000 1600

137

AA33

Y29

2000 1600

1000

VREF

138

W25

AB34

2600 2000

1000

139

Y28

AB33

3200 2600

2000

140

AA30

Y26

3200 2600
1600 1000

141

Y27

AA31

3200 2600
2000 1600

1000

142

AA27

AA29

3200 2600
2000 1600

143

AB32

AB29

2600 2000

1000

VREF

144

AA28

AC34

3200 1600

1000

145

Y25

AD34

2600 1600

146

AB30

AC33

3200 2600
1600 1000

147

AA26

AC32

2000 1000

148

AD33

AB28

3200 2600

2000

149

AE34

AB27

3200 2600
2000 1600

1000

150

AE33

AC30

2000 1600

1000

VREF

151

AA25

AE32

3200 1600

1000

152

AE31

AD29

3200 2600
2000 1600

1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

141

153

AD31

AF33

3200 2600
2000 1600

1000

VREF

154

AC28

AF31

3200 2600
1600 1000

155

AC27

AF32

3200 2600

1600

156

AE29

AD28

2600 1000

VREF

157

AD30

AG32

3200 2600
2000 1600

1000

158

AC26

AH33

2000 1600

159

AD26

AF30

3200 2600
2000 1600

1000

VREF

160

AC25

AH32

2600 2000

1000

161

AE28

AL34

3200 2600

2000

162

AG30

AD27

3200 2600
1600 1000

163

AF29

AK34

3200 2600
2000 1600

1000

164

AD25

AE27

3200 2600
2000 1600

165

AJ33

AH31

2600 2000

1000

VREF

166

AE26

AL33

3200 2600
1600 1000

167

AF28

AL32

2600 1600

168

AJ31

AF27

3200 2600
1600 1000

VREF

169

AG29

AJ32

2600 2000

1000

170

AK33

AH30

3200 2600

2000

171

AK32

AK31

3200 2600
2000 1600

1000

INIT

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

172

AP31

AK29

3200 2600
2000 1600

1000

173

AP30

AN31

3200 1600

1000

174

AH27

AN30

3200 2000

1000

175

AM30

AK28

3200 2000

1000

VREF

176

AG26

AN29

3200 2600

1000

177

AF25

AM29

3200 2600
2000 1600

1000

178

AL29

AL28

3200 2600
2000 1600

1000

VREF

179

AE24

AN28

2000 1600

180

AJ27

AH26

3200 1000

181

AG25

AK27

3200 1000

182

AM28

AF24

3200 2600

183

AJ26

AP27

3200 2600
2000 1600

1000

184

AK26

AN27

3200 2600
2000 1600

1000

VREF

185

AE23

AM27

3200 1600

186

AL26

AP26

3200 2000

1000

187

AN26

AJ25

3200 2000

1000

VREF

188

AG24

AP25

3200 2600

189

AF23

AM26

3200 2600
2000 1600

1000

190

AJ24

AN25

3200 2600
2000 1600

1000

VREF

191

AE22

AM25

2600 1600

1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

142

1-800-255-7778

Production Product Specification

192

AK24

AH23

2600 1600

1000

193

AF22

AP24

3200 2600
2000 1600

1000

VREF

194

AL24

AK23

3200 2600
2000 1600

1000

195

AG22

AN23

3200 1600

1000

196

AP23

AM23

3200 2000

1000

197

AH22

AP22

3200 2000

1000

198

AL23

AF21

3200 2600

1000

199

AL22

AJ22

3200 2600
2000 1600

1000

200

AK22

AM22

3200 2600
2000 1600

1000

VREF

201

AG21

AJ21

2000 1600

202

AP21

AE20

3200 2600

1000

203

AH21

AL21

3200 2600

1000

204

AN21

AF20

3200 -

205

AK21

AP20

3200 2600
2000 1600

1000

206

AE19

AN20

3200 2600
2000 1600

1000

VREF

207

AG20

AL20

3200 1600

208

AH20

AK20

3200 2000

1000

209

AN19

AJ20

3200 2000

1000

210

AF19

AP19

3200 2600

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

211

AM19

AH19

3200 2600
2000 1600

1000

212

AJ19

AP18

3200 2600
2000 1600

1000

VREF

213

AF18

AP17

2600 1600

1000

214

AJ18

AL18

2600 1600

1000

VREF

215

AM18

AL17

None

IO_LVDS_DLL

216

AH17

AM17

2600 1600

1000

VREF

217

AJ17

AG17

2600 1600

1000

218

AP16

AL16

3200 2600
2000 1600

1000

VREF

219

AJ16

AM16

3200 2600
2000 1600

1000

220

AK16

AP15

3200 2600

221

AL15

AH16

3200 2000

1000

222

AN15

AF16

3200 2000

1000

223

AP14

AE16

3200 1600

224

AK15

AJ15

3200 2600
2000 1600

1000

VREF

225

AH15

AN14

3200 2600
2000 1600

1000

226

AK14

AG15

3200 -

227

AM13

AF15

3200 2600

1000

228

AG14

AP13

3200 2600

1000

229

AE14

AE15

2000 1600

230

AN13

AG13

3200 2600
2000 1600

1000

VREF

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

143

231

AH14

AP12

3200 2600
2000 1600

1000

232

AJ14

AL14

3200 2600

1000

233

AF13

AN12

3200 2000

1000

234

AF14

AP11

3200 2000

1000

235

AN11

AH13

3200 1600

1000

236

AM12

AL12

3200 2600
2000 1600

1000

237

AJ13

AP10

3200 2600
2000 1600

1000

VREF

238

AK12

AM10

2600 1600

1000

239

AP9

AK11

2600 1600

1000

240

AL11

AL10

3200 2600
2000 1600

1000

VREF

241

AE13

AM9

3200 2600
2000 1600

1000

242

AF12

AP8

3200 2600

243

AL9

AH11

3200 2000

1000

VREF

244

AF11

AN8

3200 2000

1000

245

AM8

AG11

3200 1600

246

AL8

AK9

3200 2600
2000 1600

1000

VREF

247

AH10

AN7

3200 2600
2000 1600

1000

248

AE12

AJ9

3200 2600

249

AM7

AL7

3200 1000

250

AG10

AN6

3200 1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

251

AK8

AH9

2000 1600

252

AP5

AJ8

3200 2600
2000 1600

1000

VREF

253

AE11

AN5

3200 2600
2000 1600

1000

254

AF10

AM6

3200 2600

1000

255

AL6

AG9

3200 2000

1000

VREF

256

AH8

AP4

3200 2000

1000

257

AN4

AJ7

3200 1600

1000

258

AM5

AK6

3200 2600
2000 1600

1000

259

AF8

AH6

3200 2600
2000 1600

1000

260

AK3

AE9

3200 2600

2000

261

AL2

AD10

2600 2000

1000

262

AH4

AL1

3200 2600
1600 1000

VREF

263

AK1

AG6

2600 1600

264

AK2

AF7

3200 2600
1600 1000

265

AG5

AJ3

2600 2000

1000

VREF

266

AJ2

AD9

3200 2600
2000 1600

267

AH2

AC10

3200 2600
2000 1600

1000

268

AF5

AH3

3200 2600
1600 1000

269

AG3

AE8

3200 2600

2000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

144

1-800-255-7778

Production Product Specification

270

AG2

AE7

2600 2000

1000

271

AG1

AF6

3200 2600
2000 1600

1000

VREF

272

AG4

AC9

2000 1600

273

AF3

AE6

3200 2600
2000 1600

1000

274

AF4

AF1

2600 1000

VREF

275

AF2

AB10

3200 2600

1600

276

AE1

AC8

3200 2600
1600 1000

277

AE3

AD5

3200 2600
2000 1600

1000

VREF

278

AD1

AC7

3200 2600
2000 1600

1000

279

AD2

AD6

3200 1600

1000

280

AC1

AB8

2000 1600

1000

VREF

281

AC2

AC5

3200 2600
2000 1600

1000

282

AC3

AA9

3200 2600

2000

283

AD4

AC4

2000 1000

284

AB6

AA8

3200 2600
1600 1000

285

Y10

AB1

2600 1600

286

AA7

AB2

3200 1600

1000

287

AA1

AA4

2600 2000

1000

VREF

288

AB4

3200 2600
2000 1600

289

AA2

3200 2600
2000 1600

1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

290

AA5

AA6

3200 2600
1600 1000

291

AB3

3200 2600

2000

292

W10

2600 2000

1000

293

2000 1600

1000

VREF

294

2000 1600

295

3200 2600
2000 1600

1000

296

1000 -

297

3200 1600

298

3200 2600
1600 1000

299

2000 1600

1000

VREF

300

2000 1600

1000

301

3200 2600
1600 1000

VREF

302

3200 2600
2000 1600

1000

303

3200 2600
1600 1000

VREF

304

2000 1600

1000

305

2000 1600

1000

VREF

306

3200 2600
1600 1000

307

3200 1600

308

T10

1000 -

309

3200 2600
2000 1600

1000

310

2000 1600

1000

VREF

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

145

311

2600 2000

1000

312

3200 2600

2000

313

R10

3200 2600
1600 1000

314

3200 2600
2000 1600

1000

315

3200 2600
2000 1600

316

2600 2000

1000

VREF

317

3200 1600

1000

318

2600 1600

319

3200 2600
1600 1000

320

P10

2000 1000

321

3200 2600

2000

322

3200 2600
2000 1600

1000

323

2000 1600

1000

VREF

324

3200 1600

1000

325

3200 2600
2000 1600

1000

326

3200 2600
2000 1600

1000

VREF

327

3200 2600
1600 1000

328

3200 2600

1600

329

2600 1000

VREF

330

3200 2600
2000 1600

1000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

331

2000 1600

332

3200 2600
2000 1600

1000

VREF

333

2600 2000

1000

334

3200 2600

2000

335

3200 2600
1600 1000

336

3200 2600
2000 1600

1000

337

L10

3200 2600
2000 1600

338

2600 2000

1000

VREF

339

3200 2600
1600 1000

340

2600 1600

341

3200 2600
1600 1000

VREF

342

2600 2000

1000

343

3200 2600

2000

Table 29: FG1156 Differential Pin Pair Summary:
XCV1000E, XCV1600E, XCV2000E, XCV2600E, XCV3200E

Pair

Bank

Pin

Other

Functions

VirtexTM-E 1.8 V Field Programmable Gate Arrays

Module 4 of 4

www.xilinx.com

DS022-4 (v2.5) March 14, 2003

146

1-800-255-7778

Production Product Specification

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

12/7/99

1.0

Initial Xilinx release.

1/10/00

1.1

Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.

1/28/00

1.2

Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T

BYP

values, buffered Hex Line info, p. 8, I/O Timing

Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.

2/29/00

1.3

Updated pinout tables, V

page 20, and corrected Figure 20.

5/23/00

1.4

Correction to table on p. 22.

7/10/00

1.5

Numerous minor edits.

Data sheet upgraded to Preliminary.

Preview -8 numbers added to Virtex-E Electrical Characteristics tables.

8/1/00

1.6

Reformatted entire document to follow new style guidelines.

Changed speed grade values in tables on pages 35-37.

9/20/00

1.7

Min values added to Virtex-E Electrical Characteristics tables.

XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).

Corrected user I/O count for XCV100E device in Table 1 (Module 1).

Changed several pins to "No Connect in the XCV100E" and removed duplicate V

CCINT

pins in Table ~ (Module 4).

Changed pin J10 to "No connect in XCV600E" in Table 74 (Module 4).

Changed pin J30 to "

REF

or I/O option only

in the XCV600E" in Table 74 (Module 4).

Corrected pair 18 in Table 75 (Module 4) to be "AO in the XCV1000E, XCV1600E".

11/20/00

1.8

Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Preliminary.

Updated minimums in Table 13 and added notes to Table 14.

Added to note 2 to Absolute Maximum Ratings.

Changed speed grade -8 numbers for T

SHCKO32

, T

REG

, T

BCCS

, and T

ICKOF

Changed all minimum hold times to 0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.

Revised maximum T

DLLPW

in -6 speed grade for DLL Timing Parameters.

Changed GCLK0 to BA22 for FG860 package in Table 46.

2/12/01

1.9

Revised footnote for Table 14.

Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.

Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.

Revised Table 62 to include pinout information for the XCV400E and XCV600E devices
in the BG560 package.

Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.

VirtexTM-E 1.8 V Field Programmable Gate Arrays

DS022-4 (v2.5) March 14, 2003

www.xilinx.com

Module 4 of 4

Production Product Specification

1-800-255-7778

147

Virtex-E Data Sheet

The Virtex-E Data Sheet contains the following modules:

DS022-1, Virtex-E 1.8V FPGAs:

Introduction and Ordering Information (Module 1)

DS022-2, Virtex-E 1.8V FPGAs:

Functional Description (Module 2)

DS022-3, Virtex-E 1.8V FPGAs:

DC and Switching Characteristics (Module 3)

DS022-4, Virtex-E 1.8V FPGAs:

Pinout Tables (Module 4)

4/2/01

2.0

Updated numerous values in

Virtex-E Switching Characteristics

tables.

Changed pinout table footnotes from "

REF

option only

" to "

REF

or I/O option only

" to

improve clarity.

Converted file to modularized format. See the

Virtex-E Data Sheet

section.

7/26/01

2.1

Changed pinout table footnotes from "

REF

or I/O option only

" to "

REF

or I/O option only;

otherwise I/O only

" to improve clarity.

Changed designation for pin pair 300 in

Table 29

from AO to footnote 9.

10/25/01

2.2

Changed

Table 29

to clarify which devices in the FG1156 package can use each pin

pair as an asynchronous output.

Updated references to the XCV3200E device in the FG1156 package.

11/15/01

2.3

Fixed cosmetic error.

07/17/02

2.4

Added "VREF" to the description for pin B15 in

Table 12

Changed designation for pin pair 129 in

Table 15

from AO to "AO in the XCV1000E,

1600E, 2000E".

Data sheet designation upgraded from Preliminary to Production.

03/14/03

2.5

Removed the Virtex-E XCV300E section under

Pinout Differences Between Virtex

and Virtex-E Families

(and revised

Table 1

), since these differences do not exist.

Date

Version

Revision

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XCV3200E-7FG860C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XCV3200E-7FG860C