YSS902

AC3D

Dolby Digital (AC-3) / Pro Logic decoder + Sub DSP

YSS902 CATALOG

CATALOG No.:LSI-4SS902A4

1999. 7

INTRODUCTION

The YSS902 is one chip LSI consisting of two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic (Main DSP) and a
sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by
down-loading the program and coefficient.

FEATURERS

Dolby Digital 5.1 channel full decode.
24 bit DSP. (Group-A Dolby Digital decoder)

No external memory is required. (Memories for center and surround channel delay are included)

Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
AC-3 karaoke mode.
Original compression modes as well as four compression modes recommended by Dolby.
Dolby Digital decoding latency is fixed to two audio blocks (512 samples).

Included de-emphasis filter.
Pro Logic decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM.

High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original

surround, filtering, virtual surround etc.

Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)

Reads Dolby Digital decode information through the microprocessor interface.
Provide total sixteen I/O ports.
Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
Has a built-in PLL oscillation circuit to generates its own operating clock.

Internal operating clock is 25MHz.
Supply Voltage: 3.3v for core logic. 5v for I/Os.
Power saving mode.
Si-gate CMOS process.
100 QFP.(YSS902-F)

Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation.

Use of this LSI must be licensed by Dolby Laboratories Licensing Corporation.

YSS902

PIN FUNCTION

No.

Name

I/O

FUNCTION

VDD1

+5V power supply (for I/Os)

RAMCEN

External SRAM interface /CE

RAMA16

External SRAM interface address 16

RAMA15

External SRAM interface address 15

SDIB0

I+

PCM input 0 to Sub DSP

SDIB1

I+

PCM input 1 to Sub DSP

SDIB2

I+

PCM input 2 to Sub DSP

Crystal oscillator connection (6.125MHz - 50.0MHz)

Crystal oscillator connection

VSS

Ground

AVDD

+3.3 V power supply (for PLL circuit)

TEST

Test terminal (to be open in normal use)

TEST

Test terminal (to be open in normal use)

TEST

Test terminal (to be open in normal use)

OVFB

Detection of overflow at Sub DSP

TEST

Test terminal (to be open in normal use)

TEST

Test terminal (to be open in normal use)

TEST

Test terminal (to be open in normal use)

CPO

Output terminal for PLL, to be connected to ground through the external analog filter circuit

AVSS

Ground (for PLL circuit)

VDD2

+3.3 V power supply (for core logic)

SDOA2

PCM output from Main DSP (C, LFE)

SDOA1

PCM output from Main DSP (LS, RS )

SDOA0

PCM output from Main DSP (L, R)

RAMA14

External SRAM interface address 14

RAMA13

External SRAM interface address 13

RAMA12

External SRAM interface address 12

RAMA11

External SRAM interface address 11

RAMA10

External SRAM interface address 10

VSS

Ground

VDD1

+5V power supply (for I/Os)

OPORT0

Output port for general purpose

OPORT1

Output port for general purpose

OPORT2

Output port for general purpose

OPORT3

Output port for general purpose

OPORT4

Output port for general purpose

OPORT5

Output port for general purpose

OPORT6

Output port for general purpose

OPORT7

Output port for general purpose

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

RAMA9

External SRAM interface address 9

RAMA8

External SRAM interface address 8

RAMA7

External SRAM interface address 7

SDOB2

PCM output from Sub DSP

SDOB1

PCM output from Sub DSP

SDOB0

PCM output from Sub DSP

SDBCK1

I+

Bit clock input for SDOA, SDIB, SDOB

SDWCK1

I+

Word clock input for SDOA, SDIB, SDOB

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

NONPCM

Detection of non-PCM data

CRC

Detection of CRC error

MUTE

Detection of auto mute

KARAOKE

Detection of AC-3 karaoke data

YSS902

No.

Name

I/O

FUNCTION

SURENC

Detection of AC-3 2/0 mode Dolby surround encoded input

/SDBCK0

Inverted SDBCK0 clock output (refer to Block diagram)

RAMA6

External SRAM interface address 6

RAMA5

External SRAM interface address 5

VSS

Ground

RAMA4

External SRAM interface address 4

/IC

Initial clear

TEST

Test terminal (to be open in normal use)

RAMA3

External SRAM interface address 3

/CSB

Is+

Sub DSP Chip select

/CS

Microprocessor interface Chip select input

Microprocessor interface Serial data output

Microprocessor interface / Sub DSP Serial data input

SCK

Microprocessor interface / Sub DSP clock input

RAMA2

External SRAM interface address 2

VDD1

+5V power supply (for I/Os)

RAMD0

I+/ O

External SRAM interface data (STREAM0 output when External SRAM is not in use)

RAMD1

I+/ O

External SRAM interface data (STREAM1 output when External SRAM is not in use)

RAMD2

I+/ O

External SRAM interface data (STREAM2 output when External SRAM is not in use)

RAMD3

I+/ O

External SRAM interface data (STREAM3 output when External SRAM is not in use)

RAMD4

I+/ O

External SRAM interface data (STREAM4 output when External SRAM is not in use)

RAMD5

I+/ O

External SRAM interface data (STREAM5 output when External SRAM is not in use)

RAMD6

I+/ O

External SRAM interface data (STREAM6 output when External SRAM is not in use)

RAMD7

I+/ O

External SRAM interface data (STREAM7 output when External SRAM is not in use)

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

SDWCK0

Word clock input for SDIA, SDOA, SDIB, SDOB

SDBCK0

Bit clock input for SDIA, SDOA, SDIB, SDOB

SDIA0

AC-3 bitstream (or PCM) data input for Main DSP

SDIA1

AC-3 bitstream (or PCM) data input for Main DSP

RAMA1

External SRAM interface address 1

RAMA0

External SRAM interface address 0

RAMWEN

External SRAM interface /WE

RAMOEN

External SRAM interface /OE

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

IPORT7

I+