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YTD423
IHDLC2
ISDN BRI controller with B-ch HDLC controllers
1
INTR
ODUCTION
YTD423
is
a
high-p
erformance
comm
unication
LSI
for
the
ISDN
BRI
user-net
w
ork
in
terface
function
(digital
four-wire
time-division
full-duplex
op
eration),
supp
orting
D-c
hannel
la
y
er
1,
la
y
er
2
and
HDLC
con
troller
for
B-
c
hannels,
all
in
one
100-pin
SQFP
c
hip.
YTD423
supp
orts
la
y
er
1
(ph
ysical
la
y
er)
con
trol
function
conforming
to
ITU-T
Recommendation
I.430
and
fully
supp
orts
la
y
er
2
(LAP-D
proto
col)
function
conforming
to
ITU-T
Recommendations
Q.920
and
Q.921.
ETSI
(Europ
ean
T
elecomm
unications
Standards
Institute)
and
sev
eral
North
American
standard
op
erating
mo
des
are
also
supp
orted.
In
addition,
YTD423
includes
la
y
er
3
pro
cessor
in
terface
function
and
2-c
hannel
HDLC
con
troller
for
B-c
hannels,
whic
h
op
erate
in
DMA
transfer
mo
de
or
I/O
transfer
mo de.
This
giv
es
a
great
adv
an
tage
to
moun
ting
and
functional
designing
of
b
oth
\activ
e"
(with
CPU
on
b
oard)
terminal
equipmen
t
and
\passiv
e"
(no
CPU
on
b
oard)
PC
cards.
In
order
to
supp
ort
the
U
in
terface,
YTD423
has
a
TTL
in
terface
(no
built-in
analog
driv
er/receiv
er)
suitable
for
connecting
to
an
NT1
c
hip
or
a
DSU
mo
dule.
S/T
reference
p
oin
t
can
also
b
e
supp
orted
b
y
connecting
it
to
YTD421
(analog
driv
er/receiv
er
LSI).
1.1
F
eatures
1.
La
y
er
1
function
Supp
orts
la
y
er
1
con
trol
function
conforming
to
ITU-T
Recommendation
I.430
[1992
edition]
and
TTC
Standard
JT-I430
[1993
edition]
(default)
{
TTL
in
terface
{
192
kbps
transmission
rate
{
In
terface
structure
:
2B
+
D
(B
=
64
kbps,
D
=
16
kbps)
{
F
rame
assem
bling
and
disassem
bling
function
{
Collision
con
trol
(built-in
random
n
um
b
er
(Ri)
reset),
priorit
y
con
trol
(built-in
retransmission
con-
trol),
and
state
transition
con
trol
{
Programmable
T3
and
T4
timers
YTD423D CATALOG
CATALOG No.:4TD423D2
2001.1
Supp
orts
ETSI
ETS
300
012
[April
1992]
and
ANSI
T1.605
op
erating
mo
des
Leased
line
capabilit
y
(JT-I430-a)
B
c
hannel
I/O
clo
c
k
selection
function
{
In
ternal
clo
c
k
mo
de:
Inputs/outputs
the
B-c
hannel
data
with
64
k,
56
k
or
32
kHz
in
ternal
clo
c
k
{
External
clo
c
k
mo
de
(PCM
High
w
a
y
mo
de):
Inputs/outputs
the
B
c
hannel
data
with
a
128
kHz
to
2048
kHz
external
clo
c
k
B
c
hannel
selection
function
{
In
ternal
clo
c
k
mo
de:
Selects/switc
hes
B
c
hannel
I/O
pins
{
External
clo
c
k
mo
de
(PCM
High
w
a
y
mo
de):
Selects/switc
hes
B
c
hannel
time
slots
Multiframing
capabilit
y
Abundan
t
T
est
functions
(for
testing
and
main
tenance)
{
Three
kinds
of
lo
op-bac
k
mo
des
(Lo
op-bac
k
1
to
3)
{
INF
O
signals
output
for
testing
{
T
est
pulse
output
for
pulse
shap
e
ev
aluation
INF
O1
transmission
and
INF
O4
reception
monitor
pins
SLEEP
monitor
pin
I.430
transmission
frame
phase
adjustmen
t
function
2.
La
y
er
2
function
Conforms
to
ITU-T
Recommendation
Q.920
and
Q.921
[1992
edition]
and
TTC
Standard
JT-Q920
and
JT-Q921
[1993
edition]
(default)
{
HDLC
frame
con
trol
(Flag
con
trol,
F
CS
generation/c
hec
king,
automatic
zero
insertion/deletion,
ab
ort
pattern
transmission/detection,
etc.)
{
LAP-D
status
con
trol
(sequence
con
trol,
o
w
con
trol,
SAPI
con
trol)
{
Built-in
timer
for
time-out
c
hec
k
Supp
orts
ETSI
ETS
300
125
[Septem
b
er
1991],
National
ISDN-1/2,
A
T&T
5ESS
5E9
and
Nortel
DMS-
100
S208-6
op
erating
mo
des
Multi-link
capabilit
y
(circuit
switc
hing,
pac
k
et
switc
hing)
Automatic
assigned
TEI/non-automatic
assigned
TEI
(V
C/PV
C)
Leased
line
mo
de
(disable
la
y
er
2
function)
3.
La
y
er
3
in
terface
function
Connects
to
8-bit
or
16-bit
micropro
cessor
(8086
family
,
Z80
family
,
6800
family
and
68000
family)
Op
erates
in
one
of
t
w
o
data
transfer
mo
des
{
DMA
transfer
mo
de
(with
the
built-in
24-bit
address
DMA
con
troller)
{
I/O
transfer
mo
de
(with
the
built-in
FIF
O)
Primitiv
e
logical
in
terface
2
4.
HDLC
con
troller
for
B-c
hannels
HDLC
frame
con
trol
(Flag
con
trol,
optional
marks
or
ags
in
idle
state,
optional
F
CS
generation/c
hec
king,
automatic
zero
insertion/deletion,
ab
ort
pattern
transmission/detection,
optional
address
eld
genera-
tion/c
hec
king
etc.)
F
ull-duplex
comm
unication
2
2
c
hannels
Data
rates
Net
w
ork
sync
hronization
clo
c
k
mo
de
:
56
k
or
64
kbps
Net
w
ork
indep
enden
t
clo
c
k
mo
de
:
Up
to
128
kbps
Optional
16-bit/32-bit
CR
C
Programmable
data
transfer
mo
des
{
DMA
transfer
mo
de
(with
the
built-in
DMA
con
troller)
3
optional
8-bit/16-bit
access
3
24-bit
address
3
4
c
hannels
{
I/O
transfer
mo
de
(with
the
built-in
FIF
O)
3
Tx
FIF
O
:
32
b
ytes
2
2
3
Rx
FIF
O
:
64
b
ytes
2
2
3
V
ariable
in
terrupt
lev
els
3
Byte/W
ord
access
selection
Optional
transparen
t
mo
de
(disable
HDLC
con
troller
function)
5.
Lo
w-p
o
w
er
op
eration
(the
host
pro
cessor
clo
c
k
con
trol
function,
LSI
in
ternal
clo
c
k
freezing
function)
6.
CMOS
tec
hnology
7.
100-pin
SQFP
8.
Single
+5V
v
olt
supply
1.2
Applications
T
erminal
Adapter
(T
A)
Router
ISDN
PC
Card
PBX
ISDN
T
elephone
3
2
BLOCK
DIA
GRAM
2.1
User
Net
w
ork
In
terface
Blo
c
k
Diagram
YTD423
is
the
most-suited
LSI
for
terminal
equipmen
t
suc
h
as
terminal
adapters
and
ISDN
telephones
and
for
PHS
base
stations.
YTD423
con
tains
la
y
er
1
and
la
y
er
2
functions
as
w
ell
as
the
HDLC
con
troller
and
DMA
con
troller
for
the
B
c
hannel.
Because
of
this,
terminal
equipmen
t
can
b
e
optimally
con gured
b
y
adding
few
circuits
suc
h
as
the
la
y
er
3
con
trol
pro
cessor
and
analog
driv
er/receiv
er.
The
blo
c
k
diagram
of
the
user
net
w
ork
in
terface
with
YTD423
is
sho
wn
in
Figure
1.
ISDN
Network
YTD423
User's premises
TE1
(ISDN terminal)
NT2
(PBX etc.)
NT1
(DSU)
TE2
(Non-ISDN terminal)
TA(Terminal Adapter)
TE1
TA with built-in DSU
TE1
TE2
T
S/T
R
U
R
S
S
U
S/T
YTD421
(
Driver / Receiver
)
YTD428
(DSU)
Figure
1:
User
Net
w
ork
In
terface
Blo
c
k
Diagram
4
2.2
YTD423
P
eripheral
LSI
In
terface
Blo
c
k
Diagram
YTD423
Memory
System data bus (D0 ~ D15)
Control signal bus
Peripheral LSI
B1 , B2
CLK
MPU
System interrupt
controller
(8086 , 68000 etc.)
A0 ~
A23
D0 ~
D15
CS
CS
A0 ~
A23
D0 ~
D7
R/W
CS
A0 ~
A23
D0 ~
D15
HRD
LRD
HTD
LTD
YTD421
or
YTD428
Decoder
System address bus (A0 ~ A23)
A0 ~
A23
D0 ~
D15
Figure
2:
P
eripheral
LSI
In
terface
Blo
c
k
Diagram
5