GP2010

GPS Receiver RF Front End

DS4056

ISSUE 3.5

February 2002

Ordering Information

GP2010 IG GPBN (Trays, Bake & Drypack)

(supersedes GP2010 IG GPBR)

44 pin Quad Flat Pack (-40°C to +85°C)

The GP2010 is a second generation RF Front-end for

Global Positioning System (GPS) receivers. The GP2010
uses many innovative design techniques and a leading-edge
bipolar process to offer a low power, low cost and high
reliability RF Front End solution . The GP2010 is designed to
operate from either 3 or 5 Volt power supplies.

The input to the device is the L1 (1575.42MHz) Coarse-

Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2010 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.

The device has been designed to operate with the GP2021

12-channel Global Positioning Correlator, also available from
Zarlink Semiconductor.

FEATURES

Low Voltage Operation (3V - 5V)

Low Power - 200mW typ. (3V supply)

C/A Code Compatible

On-chip PLL Including Complete VCO

Triple Conversion Receiver

44-Lead Surface Mount Quad Flat-Pack Package

Sign and Magnitude Digital Outputs

Compatible with GP2021 CMOS Correlator

APPLICATIONS

C/A Code Global Positioning by Satellite Receivers

Time Standards

Navigation

· Surveying

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22

Name

IF Output
PLL Filter 1
PLL Filter 2
V

(OSC)

(REG)

PRef
PReset
V

(IO)

CLK
MAG
SIGN
OPC

IK-

OPC

IK+

(IO)

TEST
LD
V

(DIG)

AGC -
AGC +

Name

(DIG)

REF 2
REF 1
V

(RF)

RF Input
V

(RF)

O/P 1-
O/P 1+
V

(2)

I/P 2-
I/P 2+
V

(IF)

O/P 2-
O/P 2+
V

(3)

I/P 3-
I/P 3+

Pin

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Fig. 1 Pin connections - top view

2010

22
21
20
19
18
17
16
15
14
13
12

34
35
36
37
38
39
40
41
42
43
44

RELATED PRODUCTS AND PUBLICATIONS

DS4374

DS4057

AN4855

AB5202

Data

Reference

Part

Description

Small RF Format Front End
GP2000 GPS Receiver
Hardware Design

Twelve-Channel Correlator

GP2000 GPS Receiver
Hardware Design

GP2010/GP2015: Using Murata
SAFJA35M4WC0Z00 SAW Filter

GP2015

GP2021

App. Note

App. Brief

GP2010

ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)

Max. Supply Voltage

Max. RF Input

+15dBm

Max. voltage on any pin

+ 0.5V

except LD (pin 19) and PReset (pin 9), which are 5.5V

Min. voltage on any pin

- 0.5V

Storage Temperature

-65

C to +150

Operation Junction Temperature

-40

C to +150

10MHz Reference Input

1.5V pk -pk

IF STRIP

The input signal to the GP2010 is the GPS L1 signal

received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about
-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input compression
point of the GP2010 means that with subsequent IF filtering
it is possible to reject large out of band jamming signals, in
particular 900MHz as used by mobile telephones.The on-chip
PLL generates the first local-oscillator frequency at 1400MHz.
The output of the front-end mixer (Stage 1) at 175.42 MHz can
then be filtered before being applied to the second stage. The
double-balanced stage 1 mixer outputs are open-collectors,
and require external dc bias to V

The second stage contains further gain and a mixer

with a local oscillator signal at 140 MHz giving a second IF at
35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to V

The signal from stage 2 is passed through an external

filter with a 1dB bandwidth of 1.9MHz. The performance of this
filter is critical to system performance and it is recommended
that a SAW filter is used (part number SAFJA35M4WC0Z00,
available from Murata). The output of the filter then feeds the
main IF amplifier. This includes 2 AGC amplifiers and a third
mixer with a local oscillator signal at 31.111 MHz giving a final
IF at 4.309 MHz. There is an on-chip filter after the third mixer
which provides filtering centred on 4.309 MHz. The IF output,
which has 1k

output impedance, is provided for test purposes.

All of the signals within the IF amplifier are differential including
the filter inputs and outputs, except the IF output (pin 1), to
reduce any common mode interference.

Fig. 2 Block diagram of GP2010

ESD PROTECTION

The GP2010 device is static sensitive. The most

sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.

PRODUCT DESCRIPTION

The GP2010 receives the 1575.42MHz signal

transmitted by GPS satellites and converts it to a 4.309MHz
IF, using a triple down-conversion. The 4.309MHz IF is
sampled to produce a 2-bit digital output. If the GP2010 is
used in conjunction with the GP2021 correlator, then the
GP2021 provides a sampling clock of 5.714MHz. This converts
the IF to a 1.405MHz 2-bit digital output at TTL levels.

The GP2010 can operate from a single supply from

+3V (nominal) to +5V (nominal).

A block diagram of the circuit is shown in figure 2.

FRONT

END

MIXER

VCO

PLL

LOOP

FILTER

EXTERNAL

LOOP

FILTER

2nd

STAGE

MIXER

175.42MHz FILTER

AGC

3rd

STAGE

MIXER

4.3MHz
FILTER

35.42MHz FILTER

31.11MHz

140MHz

PHASE

DETECTOR

VOLTAGE

REGULATOR

1.400GHz

PHASE-

LOCKED

LOOP

PLL REF I/P

10MHz (REF 2)

40MHz CLOCK O/P

(FOR CORRELATOR

CHIP)

(OPCIK +/-)

PLL LOCK
LOGIC O/P

(LD)

1. 400GHz

BITE

(TEST)

AGC

CONTROL

+Vr

-Vr

SIGN

O/P

LATCH

MAG

O/P

LATCH

SIGN
TTL O/P

MAG
TTL O/P

SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)

IF Output
(4.309MHz)

A -> D

CONVERTER

RF Input

(1575.42MHz)

PLL

REFERENCE

OSCILLATOR

AGC CAPACITOR

REF 1 I/P

(FOR USE WITH

CRYSTAL REF

ONLY)

+1.21V

POWER-ON

REFERENCE

I/P

(PREF)

POWER-ON
RESET O/P

(PRESET)

POWER

CONTROL

POWER

DOWN I/P

(PDn)

POWER-ON

RESET

(1)

(13)

(12)

(11)

(9)

(17)

(8)

(18)

(25)

(14, 15)

(24)

(19)

(3)

(2)

(29)

(33,34)

(36,37)

(40,41)

(43,44)

(21)

(22)

GP2010

POWER-DOWN CAPABILITY

A power down function is provided on the GP2010, to

limit power consumption. This powers down the majority of
the circuit except the "power-on reset" function (see below).

If the power down feature is not required, the Power-

down input, PD

(pin 17), should be connected to 0V dc

(=Vee/Ground).

POWER-ON RESET FUNCTION

The GP2010 includes a voltage detector which

operates from the digital interface supply. This circuit is used
to produce a TTL logic low output while the GPS receiver
power supply is switching on, and produces a logic high
output when the power supply voltage has achieved a nominal
value. This output can be used to disable the GP2021
correlator while the power supply is switching on. An internal
bandgap reference of approximately +1.21V is compared
with the voltage on a sense pin, PRef (pin 8); when the
voltage on this pin exceeds the reference, a TTL logic high
level appears at the Power-on Reset output, PReset (pin 9).
Thus, if the sense input voltage is derived from an external
resistive divider from the Digital Interface supply, V

(IO) (pin

16), such that the sense voltage at nominal V

is V

, then the

supply threshold, Vcc(thresh), at which the PReset output
goes to logic high is:-

For a V

(nom) of 5.0V, V

(thresh) may be set to approx.

4.0V, giving V

of 1.5V.

For a V

(nom) of 3.0V, V

(thresh) may be set to approx.

2.4V, giving V

of 1.5V.

ADDITIONAL INFORMATION

All the digital inputs and outputs can use a separate

power supply to help prevent digital switching transitions
interacting with the analog sections of the device, and as an
additional precaution, the digital inputs and outputs are on
the opposite side of the device to the critical analog pins.

The IF output is fed to a 2-bit quantiser which provides

sign and magnitude (MSB and LSB) outputs. The magnitude
data controls the AGC loop, such that on average the magnitude
bit is set (high) 30% of the time. The AGC time constant is set
by an external capacitor.

The sign and magnitude data, SIGN (pin 13) and MAG (pin

12), are latched by the rising edge of the sample clock, CLK
(pin 11), which is normally derived from the correlator; the
GP2021 provides a 5.714MHz (=40/7) clock, giving a sampled
IF centred on 1.405MHz.

The Digital Interface circuits use a separate power-supply,

(IO), which would normally be shared with the correlator to

minimise crosstalk between the analog and digital sections of
the device.

ON-CHIP PHASE-LOCKED LOOP SYNTHESISER

All of the local oscillator signals are derived from an on

chip phase locked loop synthesiser. This includes a 1400MHz
VCO complete with on-chip tank circuit, dividers and phase
detector, with external loop filter components. A 10.000MHz
reference frequency is required for the PLL. This can be
achieved by attaching an external 10.000MHz crystal to the
on-chip PLL reference oscillator (see figure 5). However in
most applications the user will need an external source, such
as a TCXO, to provide greater frequency stability (see figure
6). An external reference should be ac coupled to REF2 (pin
24); REF 1 (pin 25) should be left open circuit.

The three local oscillator signals 1400MHz, 140.0MHz

and 31.11MHz are derived from the 1400MHz synthesiser
output. The synthesiser also provides a 40 MHz balanced
differential output clock (pins 14 & 15) which can be used to
clock the GP2021 correlator. The clock is a low level differential
signal which helps minimise interference with the analog
areas of the circuit. A PLL lock-detect output, LD (pin 19), is
also provided, which is logic high when the PLL is phase-
locked to the 10.000MHz reference signal.

The VCO power-supply incorporates an on-chip

regulator to improve the noise-immunity of the PLL. This
feature is only available when operating with a 5 volt (nominal)
supply which is regulated to 3.3 volts internally. This internal
regulated supply is referenced to V

(OSC) (pin 5). Figure 7

shows the required connections for both 3 volt and 5 volt
operation.

A further feature of the circuit is the TEST input (pin 18).

When this input is held high the PLL is unlocked with the VCO
at its maximum frequency.

= V

(nom) x 1.21

(thresh)

GP2010

ELECTRICAL CHARACTERISTICS

The Electrical Characteristics are guaranteed over the following range of operating conditions (see Fig. 3 for test circuit):

Industrial (I) grade:

AMB

= -40

C to +85

Supply voltage:

and V

= +2.7V to +5.5V

Test conditions (unless otherwise stated):

Supply voltages:

= +2.7V and +5.5V, V

= +2.7V and +5.5V

Test temperature:

Industrial (I) grade product: +25

mA
mA
mA
mA
mV

dBm

mV rms

dB
dB
dB

mV rms

dB
dB
dB

%
%

dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz

dBc

Pins 5, 23, 26, 32, 35, 42
Pin 16
Pins 5, 23, 26, 32, 35, 42
Pin 16
Between any V

pins (Note 7)

(Note 7)

= 600

(Note 2)

= 1575.42MHz

= 50

(Note 7)

Pin 29 (Notes 1 and 7)
(Notes 1 and 7)
Pins 33 & 34 (Note 8)

= 1224.58MHz (Note 7)

= 175.42MHz

Pins 36 & 37 (Note 8)
Pins 40 & 41 (Note 8)

(Note 6)
F

= 35.42MHz

(Note 3)
Pins 43 & 44 (Note 8)
CW input (Note 3)
Pin 1(Note 8)

(Note 7 and 9)

AGC

= 100nF

15kHz Loop Bandwidth

(Note 7)

14.5

6
5

100

120

+1.0

60
40

SUPPLY CURRENT

Normal mode - Analog interface

- Digital interface

Power down mode - Analog interface

- Digital interface

Power Supply Differential
Power down Response time

IF STRIP

Front End/Mixer 1
Conversion Gain (G1)

Noise Figure
Input Compression (1dB)
Input Impedance

Differential Output Impedance

RF Input Image Rejection

Stage 2/Mixer 2
Conversion Gain (G2)
Input Compression (1dB)
Differential Input Impedance
Differential Output Impedance

Stage 3
High Gain (In terms of total strip)
High Gain (G3)
Gain Control Range
Differential Input Impedance
IF Output amplitude
IF Output impedance
4.3MHz Filter Response
Flatness 4.3

1MHz

Rejection @ 0.5MHz

@ 50MHz

2 BIT QUANTISER

Sign Duty Cycle
Mag Duty Cycle
AGC Time Constant

ON-CHIP PLL SYNTHESISER

Phase Noise

1kHz

10kHz

100kHz

1MHz

5MHZ

50MHz

PLL Spurs

Characteristic

Value

Typ.

Max.

9
3
3

-16

3.6

700

27
14

700
500

75
60

14
70

50
30

-68
-75
-88

-110
-120
-120

-50

Conditions

Units

-22

106-G1-G2

-1.5

40
20

Min.

(Note 10)

(Note 7)

GP2010

MHz

MHz/V

V/rad

V pk-pk

mV p-p

(Note 4)

(Note 7)

Pin 24
(Note 11)

From Power up (Note 7)
(Note 7)

Pins 11, 17, 18

= V

Pins 13, 12
I

= -0.5mA

= 0.5mA

CL = 15pF, RL = 15k

(Note 7)

Pins 14 & 15
(Note 5)
CL = 15pF (GND) (Note 7)
CL = 5pF (Diff) (Note 7)
(Note 7)

Pins 19 and 9
I

= 0.5mA

= -10

Pin 8

1386

3.5

240

1.2

0.5

-0.8

0.5

1.35

Characteristic

Value

Typ.

Max.

Min.

3.3

150

5.3

0.6

150

-1

-0.1

220

0.2

Conditions

Units

1414

0.1

2
0

-300

-1

-1.25

-1

1.1
-10

VCO Maximum Lock Frequency
VCO Minimum Lock Frequency
VCO regulator output voltage
VCO Gain
Phase Detector Gain

10MHz Reference Input
10MHz Reference Input Impedance

PLL Lockup Time
PLL Loop Gain

DIGITAL INTERFACES
Sample Clock, Power Down,
Test Inputs.
V

Input Current High I

Input Current Low I

Sign/Mag Outputs
V

Sample Clock to Sign/Mag Delay

40MHz Clock Output
High Level (V

)

Low Level (V

)

Output (differential)

Duty Cycle

LD (PLL Lock)/PReset Outputs
Low Level (V

)

High Level (V

)

Power-on Reset comparator input
Power Reset Reference Level
Power Reset Reference Input Current

Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)

RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive
inductor value. Measured at 1575.42MHz.

Input matched to 50ohm, output loaded wlth 600ohms differential

Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.

VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.

OPCLK outputs are differential and are referenced to V

Minimum gain requirement expressions:

-7dBm

-174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB

where:

-7dBm

typical IF Output level with AGC active (equivalent to 100mV rms)

-174dBm/Hz

background noise level at RF input

19dB

sum of LNA gain and noise figure

-21dB

total loss in 175MHz and 35MHz filters

63dB

summation of noise over a 2MHz bandwidth

Rearranging the above expression gives G1 + G2 + G3 > 106dB.

This parameter is not production tested.

This impedance is toleranced at +/-30% and is not production tested.

Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.

10. CW input on pins 43 & 44 of 35.42MHz at 7mV rms.
11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.

GP2010

PIN DESCRIPTIONS

All V

and V

pins should be connected to ensure reliable operation

Pin No.

Signal Name

Input/Output

Description

IFOutput

Output

IF Test output.
Connected to output of Stage 3 prior to the A to D converter.
A series 1k

resistor is incorporated for buffering purposes.

PLL Filt1

Output

PLL Filter 1.
Connected to the bias network within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 2 (see below).

PLL Filt2

Output

PLL Filter 2.
Connected to the varactor diodes within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 1 (see above).

4,6

(OSC)

Input

Negative supply to the on-chip VCO. (See Note 1)

(OSC)

Input

Positive supply to the on-chip VCO.

(REG)

Input

Negative supply to the VCO regulator.
This must be connected to GND.

PRef

Input

Power-on Reset Reference input.
An on-chip comparator produces a logic HI when the PRef
input voltage exceeds +1.21V. (Nom) (See Page 3).

PReset

Output

Power-on Reset Output.
A TTL compatible output controlled by the Power-on reset
comparator (See above). This output remains active even
when the chip is powered down. (See pin 17 - PDn).

(IO)

Input

Negative supply to the Digital Interface. (See Note 2)

CLK

Input

Sample Clock input from the correlator chip.
A TTL compatible input (which operates at 5.714MHz if used
with GP2021 correlator device) used to clock the MAG & SIGN
output latches, on the rising edge of the CLK signal.

MAG

Output

Magnitude bit data output.
A TTL compatible signal, representing the

magnitude of the

mixed down IF signal. Derived from the on-chip 2-bit A to D
converter, synchronised to the CLK input clock signal.

SIGN

Output

Sign bit data output.
A TTL compatible signal, representing the

polarity of the mixed

down IF signal. Derived from the on-chip 2-bit A to D converter,
synchronised to the CLK input clock signal.

OPClk-

Output

40MHz Clock output - inverse phase.
One side of a balanced differential output clock, with opposite
polarity to Pin 15 - OPClk+. Used to drive a master-clock signal
within the correlator chip.

OPClk+

Output

40MHz Clock output - true phase.
Other side of a balanced differential output clock set, with
opposite polarity to Pin 14 - OPClk-. Used to drive a master-
clock signal within the correlator chip.

(IO)

Input

Positive supply to the Digital Interface. (See Note 2)

GP2010

Pin No.

Signal Name

Input/Output

Description

PDn

Input

Power-Down control input.
A TTL compatible input, which when set to logic high, will
disable ALL of the GP2010 functions, except the power-on
reset block. Useful to reduce the total power consumption of
the GP2010. If this feature is not required, the pin should be
connected to 0V (V

/GND).

TEST

Input

Test control input - Disable PLL.
A TTL compatible input, which when set to logic high, will
disable the on-chip PLL, by disconnecting the divided-down
VCO signal to the phase-detector. The VCO will free run at its
upper range of frequency operation. If this feature is not
required, the pin should be connected to 0V (V

/GND).

Output

PLL Lock Detect output.
A TTL compatible output, which indicates if the PLL is phase-
locked to the PLL reference oscillator. Will become logic high
only when phase-lock is achieved.

(DIG)

Input

Negative supply to the PLL and A to D converter.

AGC-

Output

AGC Capacitor output - inverse phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.

AGC+

Output

AGC Capacitor output - true phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.

(DIG)

Input

Positive supply to the PLL and A to D converter.

REF 2

Input

10.000MHz PLL Reference signal input .
Input to which an externally generated 10.000MHz PLL
reference signal should be ac coupled, if an external PLL
reference frequency source (e.g TCXO) is used (see fig. 6).
If no external reference is used, this pin forms part of the on-
chip PLL reference oscillator, in conjunction with an external
10.000MHz crystal (see fig. 5).

REF 1

Input

PLL reference oscillator auxillary connection.
Used in conjunction with Pin 24 (REF 2) to allow a 10.000MHz
external crystal to provide the PLL reference signal if no
external PLL reference frequency source (e.g TCXO) is used.
This pin should NOT be connected if an external TCXO is
being used (see fig. 5).

26, 32

(RF)

Input

Positive supply to the RF input and Stage 1 IF mixer.
Both pins 26 & 32 (V

(RF)) are connected internally, but

must both be connected to V

externally, to keep series

inductance to a minimum.

27, 28,

(RF)

Input

Negative supply to the RF input and Stage 1 IF mixer.

30, 31

Pins 27, 28, 30 & 31 are all connected internally, but must ALL
be connected to 0V (V

/GND) externally, to keep series

inductance to a minimum.

GP2010

Pin No.

Signal Name

Input/Output

Description

RF Input

Input

RF input.
The GPS RF input signal @ 1575.42MHz from an external
antenna with LNA and filter is connected to this pin via an
input-matching network (see fig.4).

O/P 1-

Output

Stage 1 mixer output @ 175.42MHz - inverse phase.
One of a balanced output from first stage IF mixer, to which
one input of an external balanced 175MHz bandpass filter is
connected. External dc biasing is required via an inductor
connected to V

(RF) - the value of which is dependent on the

filter used.

O/P 1+

Output

Stage 1 mixer output @ 175.42MHz - true phase.
Second of a balanced output from first stage IF mixer, to which
the second input of an external balanced 175MHz bandpass
filter is connected. External dc biasing is required via an
inductor connected to V

(RF) - the value of which is dependent

on the filter used.

(2)

Input

Positive supply to the Stage 2 IF mixer.

I/P 2-

Input

Stage 2 mixer input @ 175.42MHz - inverse phase.
One of a balanced input to the second stage IF mixer, to which
one of the balanced signal outputs from the external 175MHz
bandpass filter is connected.

I/P 2+

Input

Stage 2 mixer input @ 175.42MHz - true phase.
Second of a balanced input to the second stage IF mixer, to
which the second of the balanced signal outputs from the
external 175MHz bandpass filter is connected.

38,39

(IF)

Input

Negative supply to the Stage 2 IF mixer, and Stage 3 IF block.

O/P 2-

Output

Stage 2 mixer output @ 35.42MHz - inverse phase.
One of a balanced output from second stage IF mixer, to which
one input of an external balanced 35.42MHz bandpass filter is
connected. External dc biasing is required via an Inductor
connected to V

. (See Note 3)

O/P 2+

Output

Stage 2 mixer output @ 35.42MHz - true phase.
Second of a balanced output from second stage IF mixer, to
which the second input of an external balanced 35.42MHz
bandpass filter is connected. External dc biasing is required
via an Inductor connected to V

. (See Note 3)

(3)

Input

Positive supply to the Stage 3 IF mixer.

I/P 3-

Input

Stage 3 mixer input @ 35.42MHz - inverse phase.
One of a balanced input to the third stage IF mixer, to which
one of the balanced signal outputs from the external 35.42MHz
bandpass filter is connected. (See Note 3)

I/P 3+

Input

Stage 3 mixer input @ 35.42MHz - true phase.
Second of a balanced input to the third stage IF mixer, to which
the second of the balanced signal outputs from the external
35.42MHz bandpass filter is connected. (See Note 3)

GP2010

Notes on Pin Descriptions
1).

Both pins 4 & 6 (V

(OSC)) are connected internally. If the VCO regulator is used (V

= +5.00V nominal) then both pins

4 & 6 must be left floating, with either pin de-coupled to V

(OSC) with a 100nF capacitor. In this configuration, the dc output

level of the regulator can be monitored from V

(OSC), with respect to V

(OSC) - NOT 0V (V

/GND). For operation at

<+4.0V, the VCO regulator cannot be used, and both V

(OSC) pins must be shorted to V

(REG) (Pin 7) -

see Fig. 7.

2).

The Digital Interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelihood
of undesirable digital signals interfering with the IF strip. (Note the maximum allowable Power Supply Differential in the
Electrical Characteristics - page 4).

3).

The 35.42MHz Bandpass filter should have a bandwidth of approx 2.0MHz.

Power Down

Normal Operation

Powered Down

TEST

Normal Operation

Test

CONTROL SIGNALS

OPERATING NOTES

A typical application circuit is shown in figure 4 with the

GP2010 front-end interfaced to the GP2021 12 channel
correlator integrated circuit. The RF input has an unmatched
input impedance (see page 4). The RF input matching com-
ponents Cs and Cp should be mounted as close to the RF
input as possible: also the Vee(RF) tracks must be kept as
short as possible. A SAW may be used as a 175.42MHz filter,
but this can be replaced by a simpler coupled-tuned LC filter
if there is no critical out-of band jamming immunity require-
ment. The DC bias to mixer 1 is provided via inductors L1 and
L2, which may form part of the 175.42MHz filter. The output
of mixer 2 requires an external dc bias, achieved with inductors
L3 and L4, which also serve to tune out the input capacitance
of the 35.42MHz SAW filter. The output of the SAW is tuned
with inductor L5. The AGC capacitor (Cagc) determines the
AGC time-constant. The PLL loop filter components are
selected to give a PLL loop bandwidth of approx. 10kHz. The
IF Output is normally used for test-purposes only, but is
available to the user if required. Typically a low noise
preamplifier (gain >+15dB) is used, and may be located with
a remote antenna.

Fig. 3 GP2010 test circuit

Stage

AGC Control

INPUT

Stage 1

Output

175 MHz

Stage 2

Input

175 MHz

Stage 2

Output

35 MHz

Stage 3

Input

35 MHz

Output

CLK

SIGN

MAG

Cagc

OPClk

REF 2

TEST

PDn

PLL

LOOP

FILTER

PRESET PREF

PLL

SYNTHESISER

Power

Down

Power
Detect

AGC Control

ADC

Stage

M1 - 4 = Matching

Networks, incorporating

Balun transformers

C1 = 470nF
C2 = 10nF
R1 = 270

Cagc = 100nF
Cs = 5pF
Cp = 1.5pF

QUALITY AND RELIABILITY

At Zarlink Semiconductor, quality and reliability are

built into products by rigorous control of all processing
operations, and by minimising random, uncontrolled effects in
all manufacturing operations. Process management involves
full documentation of procedures, recording of batch-by-
batch data, using traceability procedures, and the provision of
appropriate equipment and facilities to perform sample screen-
ing and conformance testing on finished product.

A common information management system is used to

monitor the manufacturing on Zarlink Semiconductor CMOS
and Bipolar processes. All products benefit from the use of an
integrated monitoring system throughout all manufacturing
operations, leading to high quality standards for all technolo-
gies.

Further information is contained in the Quality Bro-

chure, available from Zarlink Semiconductor Sales Offices.

GP2010

Fig. 4 GP2010 typical application

Fig. 5 Crystal Reference connections

(25)

(24)

33pF

10.000MHz

CRYSTAL

Ref 1

Ref 2

GP2010

22pF

GP2010 FRONT-END

44 PIN

175MHz

FILTER

SAW

FILTER

Cagc

=0.1uF

GP2021 CORRELATOR

80 PIN

CLK_T

CLK_I

SIGN 0

MAG 0

PLL LOCK

SAMP CLK

27,28,

30,31

33 34

36 37

40 41

43 44

Vcc

REF2

10MHz I/P

PLL LOOP

FILTER

C1 = 0.47uF
R1 = 270

C2 = 10nF

INPUT

RF INPUT

MATCHING

Cs = 4.7pF
Cp = 1.5pF

L3,4 = 560nH
L5 = 2.2uH

POWER-ON REF

Vcc

POWER-ON

REF

LADDER

R3 =2.7k
R2 = 2.7k (Vcc = +3.0V)
= 6.8k (Vcc = +5.0V)

4, 6

Vcc

Creg = 0.1uF

(Vcc = +5.0V only)

VALUES FOR L1, L2, L3, L4 & L5 ARE
DEPENDENT ON FILTER USED

POWER_GOOD

R4, R5 = 470

R6 = 1.5k

GP2010

TYPICAL CHARACTERISTICS OF THE GP2010 GPS RECEIVER RF FRONT-END

The GP2010 has been characterised to guarantee reliable operation over the Industrial Temperature range (-40

C -> +85

ambient). This was achieved by setting the device case temperature to extremes of +110

C and -50

The following charts show the typical variation of key parameters across the extended case temperature range.

NOTE:- ALL Measurements at Vcc = +2.65V made with VCO voltage-regulator DISABLED.

Fig. 8 Supply Current - Analog interface - normal mode

Fig. 9 Supply Current - Analog interface - power-down mode

CASE TEMP(

-60

-40

-20

100

120

Vcc = +2.65V

Vcc = +3.8V

Vcc = +5.55V

CURRENT (mA)

CASE TEMP(

0.5

1.5

2.5

3.5

4.5

-60

-40

-20

100

120

Vcc = +2.65V

Vcc = +3.8V

Vcc = +5.55V

CURRENT (mA)

www.zarlink.com

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application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may

result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under

patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified

that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property

rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the

capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute

any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and

suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does

not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in

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Purchase of Zarlink's I

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