The KESRX01 is a single chip ASK (Amplitude Shift Key)
Receiver IC. It is designed to operate in a variety of low power
radio applications including keyless entry, general domestic
and industrial remote control, RF tagging and local paging
systems.
This single conversion superheterodyne receiver offers
an exceptionally high level of integration and performance.
The unique architecture enables data rates up to 50Kbits/sec
to be supported. All low power radio regulations, including
ETSIETS 300 220, and FCC, part 15, can easily be met.
Local oscillator generation is performed by an onchip PLL
which uses an external crystal reference oscillator (4.5 to
7.2MHz). All popular radio frequencies (315MHz, 433.92MHz,
etc) can then be supported by simply choosing the appropriate
crystal frequency.
Particular emphasis has been placed on low current
consumption, with pulsed ON/OFF operation allowing <1mA
average current consumption to be achieved. The onchip
VCO and IF significantly minimise the external components
needed thus reducing any reradiation effects.
FEATURES
s
Very low supply current (2.30mA typical)
s
Low external part count
s
105dBm sensitivity (typical 315MHz)
s
Integrated VCO and IF Filters.
ABSOLUTE MAXIMUM RATINGS
All voltages relative to V
EE
(0V)
Junction temperature, Tj
55 to +150
C
Storage temperature, Tstg
55 to +150
C
Supply voltage, V
CC
max
V
CC
0.5 to +8.0 V
Voltage on any pin, Vshort
0.5 to +8.0V
ORDERING INFORMATION
KESRX01/IG/QP1T (Tape and Reel)
KESRX01/IG/QP1S (Tubes)
Fig. 1 Pin connections - top view
Fig. 2. Block diagram
DF2
DF1
DF0
IF DC1 IF DC2
IF 2
IF 1
MIXIP RFOP
RFIN
VEERF
DIV 64
VCO
VCO 1
LF
XTAL
OSCILLATOR
PHASE FREQUENCY
DETECTOR
VEE1
VCC
DSN
DATOP
RSSI O/P
PEAK
+
PD
XTAL 1 XTAL 2
VCO 2
PEAK DETECTOR
DATA FILTER
DATA SLICER
LOG
AMP
IF FILTER
600KHz
MIXER
LNA
KESRX01
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IFDC1
IFDC2
IF2
IF1
V
CC
MIXIP
RFOP
VEERF
RFIN
DSN
DATAOP
PEAK
V
EE
PD
VCO1
VCO2
NC
LF
DF0
DF1
DF2
XTAL1
XTAL2
QPA24
1
NC
QP24
KESRX01
290 - 460MHz ASK Receiver
Advance Information
DS3968 5.0 March1998
2
KESRX01
ELECTRICAL CHARACTERISTICS D.C.
T
amb
= -40 to + 85
C, V
CC
= 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Symbol
Value
Units
Conditions
Min
Typ
Max
Supply current
I
CC1
2.30
3.00
mA
Vcc = 5V, all
Supply current
I
CC2
1.90
2.60
mA
V
CC
= 5V, all
(PLL powered down)
Power down pin input logic high
V
ih
V
CC
-0.5
V
CC
+0.5
V
Power down pin input logic low
Vil
V
EE
-0.5
V
EE
+0.5
V
Peak detector source current
I
pk
500
A
Peak detector leakage
I
IK
250
nA
Data output Logic High
V
oh
0.7V
CC
V
IIoad = 10
A
Data output Logic Low
V
ol
0.3V
CC
V
lload = 10
A
Electrostatic discharge (ESD) protection (human body model) 2KV minimum, all pins.
NOTES: Care must be taken not to power up the device with pins 7 and 8 shorted by a solder bridge, as operation with pin 7 grounded can damage
the device and result in low sensitivity.
ELECTRICAL CHARACTERISTICS A.C.
T
amb
= -40 to + 85
C, V
CC
= 4.75V to 7.0V. These characteristics are guaranteed by either production test or design. they
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Symbol
Value
Units
Conditions
Min
Typ
Max
Sensitivity See Note 1
-103
-100
dBm
R
S
= 50
, 434MHz, 2KB/s
Signal handling See Note 2
-23.5
dBm
R
S
= 50
, 434MHz, 2KB/s
LNA input impedance
V
CC
= 5V; 25
C ambient; 434MHz
Parallel combination R
11
/C
11
2.65//2.2
3.61//2.2
K
//pF
Also see note 5
Mixer input impedance
V
CC
= 5V; 25
C ambient; 434MHz
Parallel combination R
11
/C
11
1.15//1.1
1.21//1.62
K
//pF
Also see note 5
Crystal oscillator input
-0.77
-1.8
-2.1
K
C5 = C4 = 18pF
impedance
Integrated IF filter -3dB low
IF
3dB
450
550
750
KHz
All
pass cut off frequency
Spurious reverse isolation to
100
V (rms)
R
S
= 500
RFIN See Note 3
Adjacent channel rejection
ACR
65
dB
10MHz offset from receiver VCO
See Note 4
Notes:
1. Sensitivity is defined as the minimum average signal level measured at the input necessary to achieve a bit error ratio of
10
-2
where the input signal is a return to zero pulse (RZ) with an average duty cycle of 50%. The RF input is assumed to
be matched into 50
.
Measured in test circuit Fig. 6 with data filter bandwidth of 5KHz as shown and for a 2Kbit/s, 50% duty cycle signal.
2. Signal handling is defined as the maximum input signal capable of being succcessfully de-modulated. It is assumed the
input is ASK modulated with an extinction ratio of a least 40dB. The combination of this specification together with the
sensitivity specification gives a minimum signal handling range of 76dB. The RF input is assumed to be matched into 50
.
Measured in test circuit Fig. 6. with data filter bandwidth of 5KHz as shown.
3. -67dBm in 50
measured with the RF input matching network.
4. Adjacent channel rejection is defined for an interfering tone (ACR) dB above threshold and 10MHz offset from the carrier giving a 3dB
reduction in sensitivity i.e. the interfering tone is 4.74mV (rms) @ Fc
10MHz and to achieve the specified sensitivity the wanted signal
will have to be increased to 2.2
V (rms)
5. Please refer to Smith charts Fig.8 through to 10 covering frequency range 250-500MHz.
3
KESRX01
Pin
Symbol
Description
13
VEE
Negative power supply (0V)
14
PD
PLL power down
15
VCO1
VCO maintaining amplifer
16
VCO2
VCO maintaining amplifier
17
NC
Not connected, unless to GND
18
NC
Not connected,unless to GND
19
LF
PLL loop filter O/P output
20
DF0
Data filter external connection
21
DF1
Data filter external connection
22
DF2
Data filter external connection
23
XTAL1
Crystal oscillator
24
XTAL2
Crystal oscillator
PIN LISTING
Pin
Symbol
Description
1
IFDC1
IF amplifier decouple point
2
IFDC2
IF amplifer decouple point
3
IF1
Mixer output
4
IF2
IF amplifer input
5
VCC
Positive power supply
6
MIXIP
RF mixer input (tank)
7
RFOP
RF amplifier output (tank)
8
VEERF
RF amplifier ground
9
RFIN
RF input (antenna)
10
DSN
Bit slicer comparator
negative input
11
DATAOP
Bit slicer comparator output
12
PEAK
Peak detector output
FUNCTION
Phase locked loop
The phase locked loop generates the local oscillator by
frequency multiplication of a crystal referenced oscillator.
Dividers
A divide by 64 prescaler is present in the PLL feedback
loop. The local oscillator frequency is then Fo=64xF
ref
. A
system operating at 433.92MHz (RFIN) with a 270KHz IF
frequency would require a reference of 6.77578MHz
(assuming mixer low side injection). Alternative choice of
crystal and tank components permit operation at specific
frequencies in the range 290 460MHz.
Phase detector
The phase detector used is a phase frequency detector
(PFD) with a current (charge pump) output.
DP
DPb
VCO1
VCO2
Fig. 3 Input circuit of VCO and divider chain
This phase detector has a triangle characteristic for an
input phase error in the range -2
<
<
+2
and has the benefit
of being a true frequency detector (as well as a phase
detector) and hence will always achieve lock for any initial
VCO frequency.
The charge pump provides an output current in the range
30
A and hence gives a phase detector gain of 4.8
A/rad.
The PLL loop characteristics such as lock-up time, capture
range, loop bandwidth and VCO reference sideband
suppression are controlled by the external loop filter.
For the intended application a 2nd order loop should be
sufficient as shown in the test circuit Fig. 6.
VCO
A balanced configuration is used with the LC tank
connected externally across VCO1 and VCO2 Fig. 3.
4
KESRX01
External SAW resonator
For reduced power the PLL based oscillator can be
replaced by a SAW based oscillator. If pin PD is tied low (VEE)
the crystal oscillator, dividers and phase detector/charge
pump are powered down. The VCO can then be used as a
maintaining amplifier for an external SAW based oscillator.
The normal mode of operation is with PD set high (VCC) or
alternatively left unconnected. Note: the power down facility
is intended to be hard wired (either to VCC or VEE) and hence
the PD pin is not specified for operation with normal CMOS or
TTL logic levels.
PD
MODE
V
CC
/NC
PLL Enable
V
EE
PLL Disable
Reference crystal oscillator
A crystal stabilised oscillator provides a reference clock for
the PLL. The oscillator is configured for parallel resonant
operation in the fundamental mode (typical operating
frequency of 47MHz). The crystal is connected between pins
XTAL1, XTAL2 with external components as shown in Fig. 6.
Note that this is a single transistor Colpitts oscillator where the
external load capacitors must be taken into account in
specifying the crystal. See Application Note AN207.
RF amplifier
The RF amplifier consists of a low noise transistor in a
common emitter configuration. A separate emitter connection
is provided (VEERF) to reduce sensitivity to any common
impedance in this path. The amplifier is current source biased
so the signal (RFIN) should be a.c. coupled. The collector is
open circuit so that the gain can be set with an external tuned
load, Fig. 6. Its input impedance is given in Fig. 9 and output
impedance in Fig. 10.
Down converting mixer
The RF input is a.c. coupled into a doubly balanced mixer
configuration. Its input impedance is given in Fig.8.
IF filtering
The IF filter has a (nominal) bandpass response from
25KHz to 550KHz. The single high pass section is provided by
the combination of the external a.c. coupling capacitor
between IF1 and IF2 and an on chip resistor (nominal value
12k
). The low pass section is entirely on chip and to meet the
selectivity requirements (adjacent channel rejection) this filter
has 4 low pass poles with a Butterworth response.
IF amplifiers and demodulator
The majority of the receiver gain is provided in the form of
an IF limiting strip. These amplifiers are all d.c. coupled and
hence differential d.c. feedback is required. This is decoupled
externally at pins IFDC1 and IFDC2. The IF amplifier stages
also combine to provide a Received Signal Strength Indicator
(RSSI) function. Since the modulation is ASK and the RSSI
output has
a linear output for a logarithmic change on its input then the
RSSI output is the demodulated data. The only uncertainty is
the d.c. level.
Data filter
Prior to the data slicer the demodulated data passes through
a low pass filter. This filter is a 2nd order SallenKey section
using an on chip voltage follower. External capacitors set the
cutoff frequency and filter Q. The value of the on chipresistors
is 100K
(nominal). See Fig. 4.
The cut-off frequency of the data filter,o, should be set to
reduce high frequency noise into the data slicer without
distorting the wanted signal. Normally this would be at least
three times the data frequency.
Example
To implement a Bessel response filter with a 10KHz 3dB cutoff
C1 = 106pF
C2 = 80pF
BUTTERWORTH
C1
C2
R
R
BESSEL
Q = 0.577
Y = 1.732
Q = 0.71
Y = 1.0
CUT OFF FREQUENCY = fo
o = 2 .
. fo . y
C1 = 2.Q
R .
o
C2 =
1
2 . Q . R
o.
100K
DF2
DF0
DF1
Fig. 4 Choosing data filter components
5
KESRX01
Fig. 5 Peak detector output
Sensitivity
In digital radio systems, sensitivity is often defined as the
lowest signal level at the receiver input that will achieve a
specified Bit Error Ratio (BER) at the output. The sensitivity of
the KESRX01 receiver, when used in the 434MHz application
shown in Fig. 6, is typically 103dBm average power (ASK
modulated with 2kHz, 50% duty cycle square wave) to achieve
a 0.01 BER. The input was matched for a 50
signal source.
At 315MHz, 105dBm average power is typically achievable.
Consult the Applications Notes refered to at the end of this
Datasheet for detailed PCB design issues to secure
perfomance.
Choice of IF frequency and IF bandwidth
The IF frequency is selected to be nominally 270KHz with
the low frequency cut-off at 25KHz and the high frequency
cut-off at 550KHz (nominal). For worst case tolerances the
transmitter frequency may be 433.92MHz
100KHz. i.e from
433.82MHz to 434.02MHz (see transmitter design
specification application notes)
The local oscillator frequency is set at 433.65MHz with a
required accuracy of at least
100kHz (see section below) i.e
433.55MHz to 433.75MHz.
This guarantees that the IF (70KHz to 470KHz) falls within
the acceptance bandwidth of the IF filter.
The frequency of operation for such products in Europe is
433.05MHz to 434.79MHz. The choice of such a low IF
frequency ensures that any image falls within the regulatory
band. This in turn ensures that the receiver cannot be blocked
by the image response of an unwanted signal outside of this
band.
Frequency Accuracy
The stability of the local oscillator is equal to that of the
crystal reference oscillator. Therefore to obtain a final output
accuracy of
100KHz at 433MHz would require a crystal with
a tolerance specification of
230ppm. This tolerance should
encompass all causes e.g. initial accuracy, temperature
stability and ageing. Choose a tighter tolerance crystal for
increased frequency accuracy.
Bit slicer and Peak Detector
To provide maximum flexibility an independent data
comparator is provided. External circuitry must be provided to
obtain the bit slicer threshold level. Two basic approaches are
supported.
1. For coding schemes with no d.c. content (e.g. Manchester
coding or 33% / 66% pulse width encoding) this can be based
on the integrated d.c. level (using a series R and C). See
Application Note AN207.
2. For coding schemes with d.c. content (e.g. low duty cycle
pulse width modulation) an active peak detector is included.
The output at pin PEAK represents the peak level at the data
filter output (as shown in Fig.5). An external RC time constant
at this pin determines the maximum attack and decay times of
the peak detector. Typical values for the leakage and diode
current source capability are shown in the specifications. The
comparator has relatively low drive capability (push/pull
current source output of 20
A) and hence DATOP should not
be excessively loaded. On chip positive feedback around the
comparator provides a nominal hysteresis level of 20mV.
PEAK LEVEL OUTPUT
+
+
INTERNAL CIRCUIT
PEAK
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