1
14
KESTX02
8
7
XTAL1
VCOTST
VEE1
LF
LF1
TXEN
VCC
VEE2
VCCPA
OUT
OUTB
DATA
PWRC
XTAL2
KESTX02
290MHz - 320MHz ASK Transmitter
Preliminary Information
DS4265
ISSUE 3.5
October 2001
Ordering Information
KESTX02/IG/MPAD (Tape and Reel)
KESTX02/IG/MPAS (Tubes)
Figure 2 - Block diagram
MP14
Figure 1 - Pin connections - top view
Absolute Maximum Ratings
Junction temperature
55 to +150
C
Storage temperature
55 to +150
C
Supply voltage
V
EE
0.5 to +8.0 V
Voltage on any pin
V
EE
0.5 to V
CC
+0.5V
Notes:
1. The voltage on pin OUT and OUTB (open collector outputs)
can support a higher voltage than this (+14V).
The KESTX02 is a single chip ASK (Amplitude Shift Key)
transmitter IC. It is designed to operate in a variety of low
power radio applications including keyless entry, general
domestic and industrial remote control, RF tagging and local
paging systems.
The transmitter offers a high level of integration and
performance, which enables the harmonic rejection and
fundamental power requirements of the FCC part 15, and
other governing bodies, to be met.
The basic architecture utilises a crystal reference
oscillator, an integrated frequency multiplying PLL and a
power output stage. Particular emphasis has been placed on
low current drain, including a powerdown feature which
greatly increases battery life.
Features
Low supply Current
Power down feature
Adjustable output power level
Low external part count
Fully integrated VCO, PLL and Power Amplifier
TXEN
XTAL
OSCILLATOR
XTAL1 XTAL2
LF
V
CC
PLL POWER SUPPLY
1
64
PHASE
DETECTOR
VCO
V
CC
PWRC
DATA
OUT
OUT B
VEE2
VEE1
LF1
VCOTST
VCCPA
2
KESTX02
Preliminary Information
Electrical Characteristics Operating conditions
T amb = 40
C to + 70
C, V
CC
= 3.5V to 6.5V. These characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Parameter
Symbol
Value
Units
Conditions
Min
Typ
Max
Power supply voltage
V
CC
3.5
6.5
V
Ambient temperature
T a
40
+85
C
Electro static discharge 2kV all pins human body model
Electrical Characteristics D.C.
T amb = 40
C to + 70
C, V
CC
= 3.5V to 6.5V. These characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Parameter
Symbol
Value
Units
Condition
Min
Typ
Max
Supply current
I
CC
1
0.7
A
V
TXEN
=0V; V
DATA
=0V;T
a
=25
C
stand by mode
Supply current
I
mod
=150
A; V
CC
=V
TXEN
=3.5V
PLL enable/transmit space
I
CC
2
2.50
4
mA
V
DATA
=LOW; 315MHz
Supply current
PLL enable/transmit mark
I
CC
3
10.5
12.0
mA
I
mod
=150
A; V
CC
=V
TXEN
=3.5V
V
DATA
=HIGH; 315MHz
Supply current
PLL enable/transmit space
I
CC
4
3.25
4
mA
I
mod
=150
A; V
CC
=V
TXEN
=6.5V
V
Data
=LOW; 315MHz
Supply current
I
CC
5
11.3
14.5
mA
I
mod
=150
A; V
CC
=V
TXEN
=6.5A;
PLL enable/transmit mark
V
DATA
=HIGH; 315MHz
see note 1
TXEN transmit enable
Ven
3.5
V
CC
+0.2
V
TXEN transmit
V dis
V
EE
0.2
0.5
V
disable/stand by
Input bias current TXEN
I
txen
150
A
TXEN = V
CC
transmit enable
Bias voltage pin PWRC
1.20
V
I
mod
=150
A
Data pin input logic high
V
ih
0.7V
CC
V
CC
+0.5
V
Data pin input logic low
V
il
V
EE
0.5
0.3V
CC
V
Data pin input current
I
inl
-100
A
logic low
Data pin input current
I
inh
+100
A
logic high
Notes: The maximum supply current is directly related to Imod and hence the output power level (Fig. 4).
3
KESTX02
Preliminary Information
Parameter
Symbol
Value
Units
Condition
Min
Typ
Max
Output current at
IF75
2.1
2.95
3.8
pkpk
I
mod
=75
A, F
o
=315MHz
fundamental, V
CC
=3.5V
mA
Output current at
IF150
2.2
5.3
6.9
pkpk
I
mod
=150
A, F
o
=315MHz
fundamental, V
CC
=3.5V
mA
Output current
IF150
2.6
5.8
7.8
pkpk
I
mod
=150
A, F
o
=315MHz
fundamental, V
CC
=6.5V
(6V5)
mA
Output level at 2 x
22
dBc
I
mod
=150
A, F
o
=315MHz
fundamental see note 1
Output level at 3x
11
dBc
I
mod
=150
A, F
o
=315MHz
fundamental and all other
spurii see note 1
Phase detector gain
PDG
8
A/rad
Extinction ratio
ER
40
80
dB
see note 2
VCO gain
G
VCO
100
MHz/V
TXEN settling time
Txe
5.0
ms
see note 3
Output sidebands due to
SB
40
dBc
I
mod
=150
A, F
o
=315MHz
reference frequency
see note 4
30dB rise time, RF
envelope of Data pulse
T30R
380
ns
30dB fall time, RF
envelope of Data pulse
T30F
430
ns
VCO operating frequency
290
320
MHz
Notes:
1.
The spurii are specified relative to the fundamental measured in a 300KHz resolution bandwidth.
2.
Extinction ratio is defined as the ratio of the output power "SPACE" to output power "MARK" measured at the output
operating frequency.
3.
Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is operating
at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the transmission
of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external loop filter component
values. The specification value above is for the loop filter components shown in the applications diagram (Fig. 6)
4.
Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application. Reducing
the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii.
Electrical Characteristics A.C.
T amb = 40
C to + 70
C, V
CC
= 3.5V to 6.5V. These characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
4
KESTX02
Preliminary Information
PIN Listing
Signal
Description
XTAL1
Crystal oscillator
XTAL2
Crystal oscillator
DATA
Input data
TXEN
Transmit enable/stand by
OUT
Power amplifier output/antenna interface
OUTB
Power amplifier output/antenna interface
(complementary output)
LF
Phase detector output
LF1
VCO control input
PWRC
Output power control
VCCPA
Power amplifier positive supply
VEE2
Power amplifier ground
VEE1
PLL ground
VCC
Positive supply
VCOTST
VCO test control input
Function
When the IC is enabled (TXEN high) a phase locked loop
locks the output of the VCO to a multiple of a crystal defined
reference input. The output of the VCO operates at the final
output frequency and is the input to a power amplifier stage.
The power amplifier directly drives the antenna.
Phase locked loop
Dividers
A divide by 64 prescaler is present in the PLL feedback
loop. The final output frequency is then Fo = 64xFref.
Phase detector
The phase detector used is a phase frequency detector
(PFD) with a current (charge pump) output. This phase
detector has a triangular characteristic for an input phase error
in the range 2
<
e < 2
. The charge pump provides an
output current in the range +50
A and hence gives a phase
detector gain of (50/2
)
A/rad (
8
A/rad).
The advantage of the PFD over a pure phase detector is
that it is also a frequency discriminator and will always lock the
loop irrespective of the initial frequency offset. The PLL loop
characteristics such as lockup time, capture range, loop
bandwidth and VCO reference sideband suppression are
controlled by the external loop filter.
For certain applications spurious sidebands at the
reference frequency must be adequately suppressed and a
3rd order loop is recommended.
VCO
To minimize external component costs the VCO is fully
integrated. The frequency of the VCO is controlled by the
voltage on pin LF.
Reference crystal oscillator
A single transistor Collpits crystal oscillator provides a
reference clock for the PLL. The oscillator is configured for
parallel resonant operation in the fundamental mode (typical
operating frequency of 37MHz). The crystal is connected
between pins XTAL2 and V
EE
1 with external components as
shown in Fig.6.
Alternatively, a reference clock can be provided by an
external source connected to pin XTAL2 Fig. 7.
Output stage (PA)
The input signal at pin DATA produces amplitude shift key
(ASK) modulation of the VCO output. This is achieved by on
off keying of the bias current in the output power amplifier
stage. The output of the PA is a balanced output (pin OUT and
OUTB) and is current source driven (open collector outputs).
The outputs of which should be D.C. referenced to a positive
supply voltage (anticipated to be V
CC
in most applications).
The current source outputs can drive a PCB antenna directly
(Fig. 6) or if a higher output power is required on limited supply
headroom via a simple impedance transforming network.
A balanced output stage is used as it automatically
suppresses the even order harmonics of the fundamental. Of
particular importance for the European application is
suppression of the 2nd harmonic (due to regulatory issues
concerning spurious outputs). In order to obtain the benefits of
this output stage it is essential to use a balanced antenna.
Power up
In the intended application it is expected that the
transmitter will spend a large proportion of time in ``stand by"
not transmitting data. To maximise battery life it is important
that very little quiescent current is taken in this mode.
The ``stand by mode" is selected by setting pin TXEN low
and similarly the transmitter is enabled by setting TXEN high.
To minimize standby current TXEN is used to bias an on
chip npn transistor connected in a common collector
configuration (Fig. 3). This transistor is used to provide the
supply to large portions of the IC. Collapsing the supply when
TXEN is set low results in a very low stand by current. The
voltage on TXEN should not exceed V
CC
by more than 0.2V.
From an application standpoint the TXEN pin must be able
to source the bias current for the input transistor and should
also be decoupled if possible to prevent high frequency noise
directly coupling into the IC power supply. The value of the
decoupling capacitor and the drive capability of the TXEN
source will affect power up delay. Since TXEN enables the
PLL it is therefore essential that it is set high prior to any data
transmission and that it remains high during the transmission.
Therefore three different power drain modes are possible
(i)
Stand by (TXEN low, DATA low)
(ii) PLL Mode/Transmit SPACE (TXEN high, DATA low)
(iii) Transmit MARK (TXEN high, DATA high)
5
KESTX02
Preliminary Information
(
)
p
y
( )
(
g
g )
v
CC
v
EE
v
CC
TXEN
v
EE
ACTIVE CIRCUITS
power up
power dn
Figure 3 - TXEN power up operation
Applications Information
Power control
The bias current for the power amplifier directly controls the output current (and hence the output power). The bias current
is set by the external resistor connected between PWRC and ground. The bias voltage on pin PWRC is nominally 1.20V and
hence the modulation current Imod is given by 1.20/R.
To a first order neither the linearity (harmonic spurii relative to fundamental) or the amplifier efficiency are affected by Imod.
The graph below shows typical simulation results for the amplifier current output with Imod variation.
OUTPUT CURRENT (mA)
9
8
7
6
5
4
3
2
1
37
100
200
300
400
500
600
MODULATION CURRENT Imod (uA)
OUTPUT CURRENT VS Imod
Figure 4 - PWRC power output control
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