Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink's obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y I N F O R M A T I O N
1998 Zarlink Semiconductor, Inc.
1
Rev. 2.1- February, 1999
Distinctive Characteristics
8 independent Ethernet Access Ports
Two 10/100Mbps Fast Ethernet
Ports
Direct interface with 10BaseT
transceiver
IEEE 802.3u compliant MII
(Media Independent Inter-
face) and Serial Management
interface
Direct interface with
100BaseTX, T2, T4, or TF
transceivers
Six 10Mbps Ethernet Ports
Direct interface with 10BaseT
transceiver
0.5 micron 3.3 Volt CMOS process
352-BGA package
Operating frequency
-33
33 MHz maximum
-40
40 MHz maximum
-50
50 MHz maximum
-66 66.66 MHz maxi-
mum
32-bit Local Buffer Memory Interface
Supports 128k to 1M bytes
Utilize high performance 32-bit
Synchronous Burst SRAM
Hardware assisted Buffer and Queue
Management
16-bit Management Bus I/O Interface
Allows host to access Control
Registers & Local Buffer Memory
Big and Little Endian CPUs
Direct interface to standard micro-
processors, including 386, 486
families and Motorola MPC series
embedded processors
32-bit XpressFlow Bus Interface
Uses Granule for frame transfer-
ring between Access Controllers
Unicast, multicast, and broadcast
frames
Also detects IEEE 802.3X MAC
Control frames
EA218 6+2 Ports Ethernet Access Controller
XpressFlow 2020 Ethernet Routing Switch Chipset
Local
Buffer
Memory
MANAGEMENT BUS
XPRESSFLOW BUS
XpressFlow
Bus Interafce
MAC Port #0 to #7
Port 0
2
3
16
32
32
2-Port
100Base-Tx
PHY
4
5
6
7
Management
Bus Interafce
Local
Buffer
Memory
Interface
Automatic
Buffer
Manager
MAC Interface
6-Port
10BaseT PHY
1
Port 0
2
3
4
5
6
7
1
32
32
EA-218
Block Diagram-
EA218 6+2 Ports Ethernet Access Controller
General Description
The EA-208 provides the Ethernet network access interface. It supports 6 ports of 10Mbps
Ethernet and 2 ports of 10/100 Mbps Ethernet. The 10Mbps ports uses serial interface to con-
nect with external 10BaseT or other 10Mbps PHY devices. For 10/100 Mbps ports, MII inter-
face is used to connect external PHY devices.
The EA-208 provides the MAC protocols, handles the local buffer memory interface and man-
agement, arbitrates among multiple priority queues, and interfaces with the XpressFlow Engine
and other Access Controllers through the XpressFlow message passing protocol.
Related Components:
SC220 XpressFlow Engine
EA218E 8-port 10Mb Ethernet Access Controller
EA234 4-port 10/100Mbps Ethernet Access Controller
P R E L I M I N A R Y I N F O R M A T I O N
XpressFlow-2020 Series
EA218
Ethernet Switch Chipset
6+2 Ports 10Mb Ethernet Access Controller
1998 Zarlink Semiconductor, Inc.
2
Rev. 2.1- February, 1999
Characteristics Continue
Works together with SC-220 Xpress-
Flow Engine
Forwards frames at full line-rate
Distributed Flow CachingTM to re-
duce frame forwarding latency
Half and Full Duplex operation
Programmable Flow Control
Jam Collision for Half Duplex
Mode
Transmit Flow Control Frame for
IEEE 802.3x Full Duplex Mode
Supports Store-&-Forward frame for-
warding mode
Multi-Media ready with QoS supports
Four frame transmission priority
queues
Complies with IEEE 802.1 Bridge
Standard
Assigns one unique MAC Address
for each port
VLAN ID Tagging & Stripping
Auto padding if necessary after
stripping
Automatic retry frame transmission
Transmit collision
Transmit buffer under-run
Automatic receive filtering for bad
frames for Store & Forward Mode
Bad FCS
Short events or frames under 64
bytes
Long events or frames over
1518/1522 bytes
Automatic statistic collection for
RMON
Local
Buffer
Memory
MANAGEMENT BUS
XPRESSFLOW BUS
XpressFlow
Bus Interafce
MAC Port #0 to #7
Port 0
2
3
16
32
32
2-Port
100Base-Tx
PHY
4
5
6
7
Management
Bus Interafce
Local
Buffer
Memory
Interface
Automatic
Buffer
Manager
MAC Interface
6-Port
10BaseT PHY
1
Port 0
2
3
4
5
6
7
1
32
32
EA-218
Block Diagram
EA218E 8-Port Ethernet Access Controller
Typical Application
:
A 22-port Ethernet Switch with 2-Fast Ethernet
Address
Mapping
Table
Flash
ROM
SC220
XpressFlow
Engine
EA218E
8-Port
Ethernet
Access
Controller
Management Bus
Buffer
RAM
Switch
Manager
CPU
DRAM
RS232 Local
Control Console
Buffer
RAM
8 Ethernet ports
Buffer
RAM
8 Ethernet ports
XpressFlow Bus
EA218E
8-Port
Ethernet
Access
Controller
Buffer
RAM
Six 10M Ethernet + two
100M Fast Ethernet ports
EA218
8-Port
Ethernet
Access
Controller
System Block Diagram --
22-Ports Ethernet Switch with 2 Fast Ethernet Up-Links
P R E L I M I N A R Y I N F O R M A T I O N
XpressFlow-2020 Series
EA218
Ethernet Switch Chipset
6+2
Ports 10Mb Ethernet Access Controller
1998 Zarlink Semiconductor, Inc.
3
Rev. 2.1- February, 1999
1. PIN ASSIGNMENT
1.1 Logic Symbol
EA-218
TEST
M_MDC
M_MDIO
XpressFlow
Bus Interface
Management Bus
Interface
Test Pin
P_D[15:0]
P_CS#
P_ADS#
P_RWC
P_BS16#
P_RDY#
P_INT
P_RST#
P_CLK
P_A[11:1]
Control Buffer
Memory Interface
MII Serial
Managem't
Mm_RXD[3:0]
Mm_RXDV
Mm_RXC
Mm_RXER
4
Mm_TXER
Mm_TXC
Mm_TXEN
Mm_TXD[0]
Mm_TXD[1]
Mm_TXD[2]
Mm_TXD[3]
Port [1:0]
10/100 MII Interface
Port [7:2]
10M Serial Interface
Mm_COL
Mm_CRS
Mm_LNK
Tm_RXD
Tm_RXC
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
Tm_RXD
Tm_RXC
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
MII Mode
10BaseT
Serial Xface
L_D[31:0]
L_OE[3:0]#
L_ADSC#
L_CLK
L_A[18:2]
L_WE[3:0]#
L_BWE[3:0]#
4
4
4
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
S_HPREQ#
S_REQ#
S_GNT#
S_CLK
P R E L I M I N A R Y I N F O R M A T I O N
XpressFlow-2020 Series
EA218
Ethernet Switch Chipset
6+2
Ports 10Mb Ethernet Access Controller
1998 Zarlink Semiconductor, Inc.
4
Rev. 2.1- February, 1999
1.2 Pin Assignment (Preliminary)
Note:
#
Active low signal
Input
Input signal
In-ST
Input signal with Schmitt-Trigger
Output
Output signal (Tri-State driver)
Out-OD
Output signal with Open-Drain driver
I/O-TS
Input & Output signal with Tri-State driver
I/O-OD
Input & Output signal with Open-Drain driver
5VT
Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Pin No(s).
Symbol
Type
Max
I
OL
/ I
OH
Name and Functions
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
P_D[15:0]
TTL I/O-TS (5VT)
16mA
Management Bus Data Bit [15:0]
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
P_A[11:1]
TTL In (5VT)
Management Bus Address Bit [11:1]
F25
P_ADS#
TTL In (5VT)
Management Bus Address Strobe
H25
P_RWC
TTL In (5VT)
Management Bus Read/Write Control
J24
P_RDY#
TTL Out-OD
16mA
Management Bus Data Ready
G25
P_BS16#
TTL Out-OD
16mA
Management Bus 16 bit Data Bus
G26
P_CS#
TTL In (5VT)
Management Bus Chip Select
H26
P_INT
CMOS Output
4mA
Management Bus Interrupt Request
J26
P_RST#
TTL In-ST (5VT)
Management Bus Master Reset
K24
P_CLK
TTL In (5VT)
Management Bus Bus Clock
XpressFlow Bus Interface
C23,A23,B22,C22,A22
S_D[31:27] /
P_C[0:4]
CMOS I/O-TS
12 mA
XpressFlow Bus Data Bit [31:27] or Manage-
ment Bus Interface Configuration bit [0:4]
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
S_D[26:0]
CMOS I/O-TS
12mA
XpressFlow Bus Data Bit [26:0]
B12
S_MSGEN#
CMOS I/O-TS
12 mA
XpressFlow Bus Message Envelope
A12
S_EOF#
CMOS I/O-TS
12mA
XpressFlow Bus End of Frame
C14
S_IRDY
CMOS I/O-TS
12 mA
XpressFlow Bus Initiator Ready
C13
S_TABT#
CMOS I/O-OD
12 mA
XpressFlow Bus Target Abort
B23
S_HPREQ#
CMOS I/O-OD
12mA
XpressFlow Bus High Priority Request
A24
S_REQ#
CMOS Output
4mA
XpressFlow Bus Bus Request to SC201
B24
S_GNT#
CMOS Input
XpressFlow Bus Bus Grant from SC201
A13
S_OVLD#
CMOS Input
XpressFlow Bus Bus Overload
D13
S_CLK
CMOS Input
XpressFlow Bus Clock
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