Document Outline

• Overview
  • Figure 1 - MT312 functional block diagram
• Additional Features
• Demodulator
• Viterbi
• De-Interleaver
• Reed-Solomon
• De-Scrambler
• Outputs
• Application Support
• 1.0 Application Diagram
  • Figure 2 - Application schematic
• 2.0 Functional Overview
  • 2.1 Introduction
  • 2.2 Analogue-to-Digital converter
  • 2.3 QPSK demodulator
  • 2.4 Forward error correction
    • 2.4.1 Viterbi error count measurement
      • Figure 3 - Viterbi block diagram
      • Figure 4 - Viterbi error count measurement
      • 2.4.1.1 Viterbi error count coarse indication
        • Figure 5 - Viterbi error count coarse indication
    • 2.4.2 The frame alignment block
    • 2.4.3 The De-interleaver block
      • 2.4.3.1 DVB
      • 2.4.3.2 DSS
        • Figure 6 - DVB conceptual diagram of the convolutional de-interleaver block
        • Figure 7 - DSS conceptual diagram of the convolutional de-interleaver block
    • 2.4.4 The ReedSolomon decoder block
    • 2.4.5 The energy dispersal (de-scrambler) block, DVB only
      • Figure 8 - DVB Block Structure
      • Figure 9 - DVB energy dispersal conceptual diagram
      • Figure 10 - DVB energy dispersal conceptual diagram
    • 2.4.6 Output stage
  • 2.5 Control
    • Figure 11 - MT312 control structure
    • 2.5.1 Symbol Rate and Code Rate Search Mode
  • 2.6 DiSEqC� Transmit and Receive Messages
    • 2.6.1 DiSEqC� transmitting messages
    • 2.6.2 DiSEqC� receiving messages
• 3.0 MT312 software control
  • 3.1 MT312 register map overview
    • Table 1 - MT312 register map overview
  • 3.2 Register usage overview
    • Table 2 - Register usage overview
• 4.0 MT312 Initialization
  • 4.1 Initialization sequence
  • 4.2 The configuration register (127)
  • 4.3 Power Supplies
    • Figure 12 - MT312 Power-up Sequence
    • Figure 13 - Initialization sequence in DVB mode.
  • 4.4 Spectral inversion
  • 4.5 Read/write registers
    • 4.5.1 Reset register 21 (R/W)
    • 4.5.2 System clock frequency register 34 (R/W)
  • 4.6 Read registers
    • 4.6.1 Identification register 126 (R)
• 5.0 Tuner Control
  • 5.1 Simple channel change sequence
  • 5.2 Channel change sequence with a new symbol rate
  • 5.3 Channel change sequence with search mode
    • Figure 14 - Simple channel change sequence
    • Figure 15 - Channel change sequence with new symbol rate, DVB mode
    • Figure 16 - Channel change sequence with search mode, DVB mode
    • Figure 17 - Results of symbol rate and code rate search, DVB or DSS mode
  • 5.4 Tuner Control Read/Write Registers
    • 5.4.1 General purpose port control register 20 (R/W)
    • 5.4.2 FR_LIM frequency limit register 37 (R/W)
    • 5.4.3 FR_OFF frequency offset register 38 (R/W)
  • 5.5 Tuner Control Read Registers
    • 5.5.1 Measured LNB frequency error registers 7 - 8 (R)
    • 5.5.2 Frequency error 1 and 2 registers 111 - 115 (R)
• 6.0 DiSEqC Control
  • 6.1 Screen printouts of DiSEqC� waveforms
    • Figure 18 - A DiSEqC� data byte interrupting a continuous 22kHz tone
    • Figure 19 - One DiSEqC� data byte - 0x11 (hex) plus parity bit
  • 6.2 DiSEqC� control read/write registers
    • 6.2.1 DISEQC mode control register 22 (R/W)
    • 6.2.2 DISEQC ratio register 35 (R/W)
    • 6.2.3 DISEQC instruction register 36 (R/W)
    • 6.2.4 DISEQC2 control 1 registers 121 (R/W)
    • 6.2.5 DISEQC2 Control 2 registers 122 (R/W)
  • 6.3 DiSEqC Control Read Registers
    • 6.3.1 DISEQC2 Interrupt Indicators register 118 (R)
    • 6.3.2 DISEQC2 Status Indicators register 119 (R)
    • 6.3.3 DISEQC2 FIFO register 120 (R)
• 7.0 QPSK demodulator
  • 7.1 QPSK Demodulator Read/Write Registers
    • 7.1.1 Symbol rate registers 23 - 24 (R/W)
      • Table 3 - Symbol Sweep Ranges for General Case
      • Table 4 - Symbol Sweep Ranges for 90MHz System Clock
    • 7.1.2 Viterbi mode register 25 (R/W)
    • 7.1.3 QPSK control register 26 (R/W)
    • 7.1.4 Go command register 27 (R/W)
    • 7.1.5 QPSK interrupt output enable registers 28 - 30 (R/W)
    • 7.1.6 QPSK status output enable register 32 (R/W)
  • 7.2 QPSK Demodulator Read Registers
    • 7.2.1 QPSK Interrupt registers 0 - 2 (R)
    • 7.2.2 QPSK Status registers 4 - 5 (R)
    • 7.2.3 Symbol Rate Output registers 116 - 117 (R)
    • 7.2.4 Monitor registers 123 - 124 (R)
• 8.0 Forward Error Correction
  • 8.1 Forward error correction read/write registers
    • 8.1.1 FEC interrupt enable register 31 (R/W)
    • 8.1.2 FEC_STATUS output enable register 33 (R/W)
    • 8.1.3 FEC setup register 97 (R/W)
  • 8.2 Forward Error Correction Read Registers
    • 8.2.1 FEC interrupt register 3 (R)
    • 8.2.2 FEC status register 6 (R)
      • Table 5 - Viterbi Code Rate Indication
    • 8.2.3 Measured Signal-to-Noise-Ratio registers 9 - 10 (R)
    • 8.2.4 Viterbi error count at Viterbi input registers 11 - 13 (R)
    • 8.2.5 Reed-Solomon bit errors corrected registers 14 - 16 (R)
    • 8.2.6 Reed-Solomon uncorrected block errors registers 17 - 18 (R)
• 9.0 Automatic Gain Control
  • 9.1 Automatic gain control read/write registers
    • 9.1.1 AGC control register 39 (R/W)
      • Table 6 - Sigma Delta Clock Decimation Ratio Programming
    • 9.1.2 AGC_REF Reference Value register 41 (R/W)
  • 9.2 Automatic gain control read registers
    • 9.2.1 Measured signal level at MT312 input register 19 (R)
    • 9.2.2 Measured AGC feed back value registers 108 - 110 (R)
• 10.0 MPEG Packet Data Output
  • 10.1 MPEG clock modes
    • Table 7 - MPEG Clock Modes
    • 10.1.1 MANUAL MOCLK = 0 and DIS_SR = 0.
    • 10.1.2 MANUAL MOCLK = 0 and DIS_SR = 1.
    • 10.1.3 MANUAL MOCLK = 1 and DIS_SR = 0
      • Table 8 - MOCLK Input Minimum And Maximum Frequencies
    • 10.1.4 MANUAL MOCLK = 1 and DIS_SR = 1.
  • 10.2 Data Output Header Format - DVB
    • Figure 20 - DVB Transport Packet Header Bytes
  • 10.3 MPEG/DSS Data Output Signals
    • 10.3.1 ERR_IND = 0
      • Figure 21 - BKERR example when ERR_IND is low
    • 10.3.2 ERR_IND = 1
      • Figure 22 - BKERR example when ERR_IND is high.
  • 10.4 Data output timing
    • Figure 23 - MT312 Data Output Timing Diagram
  • 10.5 MPEG Packet Data Output Read/Write Registers
    • 10.5.1 Output data control register 96 (R/W)
    • 10.5.2 Monitor Control register 103 (R/W)
• 11.0 Secondary Registers for Test and De-Bugging
  • 11.1 Read/Write Secondary Register Map
    • Table 9 - Read/write Secondary Register Map
  • 11.2 Secondary Registers for Test and De-Bugging Read/Write Registers
    • 11.2.1 AGC Initial Value register 40 (R/W)
    • 11.2.2 AGC Maximum Value register 42 (R/W)
    • 11.2.3 AGC Minimum Value register 43 (R/W)
    • 11.2.4 AGC Lock Threshold Value register 44 (R/W)
    • 11.2.5 AGC Lock Threshold Value register 45 (R/W)
    • 11.2.6 AGC Power Setting Initial Value register 46 (R/W)
    • 11.2.7 QPSK Miscellaneous register 47 (R/W)
    • 11.2.8 SNR_LOW threshold value register 48 (R/W)
    • 11.2.9 SNR_HIGH threshold value register 49 (R/W)
    • 11.2.10 Timing Synchronisation Sweep Rate register 50 (R/W)
    • 11.2.11 Timing Synchronisation Sweep Limit Low register 51 (R/W)
    • 11.2.12 Timing Synchronisation Sweep Limit High register 52 (R/W)
    • 11.2.13 Carrier Synchronisation Sweep Rate 1 register 53 (R/W)
    • 11.2.14 Carrier Synchronisation Sweep Rate 2 register 54 (R/W)
    • 11.2.15 Carrier Synchronisation Sweep Rate 3 register 55 (R/W)
    • 11.2.16 Carrier Synchronisation Sweep Rate 4 register 56 (R/W)
    • 11.2.17 Carrier Synchronisation Sweep Limit register 57 (R/W)
    • 11.2.18 Timing Synchronisation Coefficients registers 58 - 60 (R/W)
    • 11.2.19 Carrier Synchronisation Proportional Part Coefficients registers 61 - 62 (R/W)
    • 11.2.20 Carrier Synchronisation Integral Coefficients registers 63 - 64 (R/W)
    • 11.2.21 QPSK Output Scale Factor register 65 (R/W)
    • 11.2.22 Timing Lock Detect Threshold out of lock register 66 (R/W)
    • 11.2.23 Timing Lock Detect Threshold in lock register 67 (R/W)
    • 11.2.24 Frequency Lock Detect Threshold register 68
    • 11.2.25 Phase Lock Detect Threshold out of lock registers 69 - 72 (R/W)
    • 11.2.26 Phase Lock Detect Threshold in lock registers 73 - 76 (R/W)
    • 11.2.27 Phase Lock Detect Accumulator Time register 77 (R/W)
    • 11.2.28 Sweep PAR register 78 (R/W)
    • 11.2.29 Start up Time register 79 (R/W)
    • 11.2.30 Loss Lock Threshold register 80 (R/W)
    • 11.2.31 FEC Lock Time register 81 (R/W)
    • 11.2.32 Loss Lock Time register 82 (R/W)
    • 11.2.33 Viterbi Error Period registers 83 - 85 (R/W)
    • 11.2.34 Viterbi Set up register 86 (R/W)
      • Table 10 - Viterbi Code Rate Search Start
    • 11.2.35 Viterbi Reference Byte 0 register 87 (R/W)
    • 11.2.36 Viterbi Reference Byte 1 register 88 (R/W)
    • 11.2.37 Viterbi Reference Byte 2 register 89 (R/W)
    • 11.2.38 Viterbi Reference Byte 3 register 90 (R/W)
    • 11.2.39 Viterbi Reference Byte 4 register 91 (R/W)
    • 11.2.40 Viterbi Reference Byte 5 register 92 (R/W)
    • 11.2.41 Viterbi Reference Byte 6 register 93 (R/W)
    • 11.2.42 Viterbi Maximum Error register 94 (R/W)
    • 11.2.43 Byte Align Set up register 95 (R/W)
    • 11.2.44 Program Synchronising Byte register 98 (R/W)
    • 11.2.45 AFC Frequency Search Threshold register 99 (R/W)
    • 11.2.46 Accumulator Differential Threshold register 100 (R/W)
    • 11.2.47 QPSK Lock Control register 101 (R/W)
    • 11.2.48 QPSK State Control register 102 (R/W)
    • 11.2.49 QPSK Reset register 104 (R/W)
    • 11.2.50 QPSK Test Control register 105 (R/W)
    • 11.2.51 QPSK Test State register 106 (R/W)
    • 11.2.52 Test Mode register 125 (R/W)
  • 11.3 Read only Secondary Register Map
  • 11.4 Secondary Registers for Test and De-Bugging Read Register
    • 11.4.1 Test Read register 107 (R)
• 12.0 Microprocessor Control
  • 12.1 Primary 2wire Bus Address
  • 12.2 RADD: 2wire Register Address (W)
  • 12.3 Primary 2wire Bus Interface
  • 12.4 Secondary 2wire bus for tuner control
  • 12.5 Examples of 2wire Bus Messages
  • 12.6 Primary 2wire Bus Timing
    • Figure 24 - Primary 2wire Bus Timing
    • Table 11 - Primary 2wire bus timing
• 13.0 Electrical Characteristics
  • 13.1 Recommended Operating Conditions
    • Recommended Operating Conditions
  • 13.2 Absolute Maximum Ratings
    • Maximum Operating Conditions
  • 13.3 Crystal Specification
    • Figure 25 - Crystal Oscillator Circuit
  • 13.4 Electrical Characteristics
    • DC Electrical Characteristics
  • 13.5 MT312 Pinout Description
    • Pin Description Table
  • 13.6 Alphabetical Listing of Pin-Out
    • Alphabetical Listing of Pin-Out
• 14.0 MT312 Register Map
  • 14.1 Read/Write Register Map
    • Read/Write Register Map
  • 14.2 Read Only Register Map
• 15.0 References