Document Outline

• Overview
• Key Features
• Applications
• Additional Features
• Abbreviations and Symbols
• MT351 Applications Information
• Application Support
• 1.0 Functional Overview
  • 1.1 Analogue-to-Digital Converter
  • 1.2 COFDM overview
    • 1.2.1 IF input to baseband signal
    • 1.2.2 Timing recovery
    • 1.2.3 Fast Fourier Transformation
    • 1.2.4 Pilot carrier processing
    • 1.2.5 AGC signals
  • 1.3 FEC overview
    • 1.3.1 Viterbi decoder
    • 1.3.2 Frame/byte Align Block
    • 1.3.3 Byte De-interleaver Block
    • 1.3.4 Reed-Solomon Decoder
    • 1.3.5 Energy Dispersal (de-scrambler)
    • 1.3.6 Transport Stream Output
  • 1.4 Control
• 2.0 MT351 Register Overview
  • 2.1 Initialisation Read/Write Registers
  • 2.2 Tuner
    • 2.2.1 Tuner Read/Write Registers
    • 2.2.2 Tuner Read Registers
  • 2.3 COFDM
    • 2.3.1 COFDM Read/Write Registers
    • 2.3.2 COFDM Read Registers
  • 2.4 Forward Error Correction
    • 2.4.1 FEC Read/Write Registers
    • 2.4.2 FEC Read Registers
  • 2.5 Automatic Gain Control
    • 2.5.1 AGC Read/Write Registers
    • 2.5.2 AGC Read Registers
  • 2.6 MPEG Read/Write Registers
  • 2.7 ID Read Register
  • 2.8 Secondary registers for test and de-bugging.
    • 2.8.1 COFDM De-bugging Read/Write Registers
    • 2.8.2 COFDM De-bugging Read Register
    • 2.8.3 FEC De-bugging Read/Write Registers
    • 2.8.4 AGC, ADC and Test Mode De-bugging Read/Write Registers
• 3.0 MT351 Initialisation
  • 3.1 Power Supplies
  • 3.2 Operational States
  • 3.3 Primary 2-wire Bus Address
  • 3.4 RADD: 2-wire Bus Register Address
  • 3.5 Initialisation Read/write Registers
    • 3.5.1 Configuration Set-up byte 2. Register 0x7E (R/W)
    • 3.5.2 Software reset selection. Register 0x22 (R/W)
  • 3.6 Software Initialisation
    • 3.6.1 Basic Configuration.
    • 3.6.2 COFDM Environment.
    • 3.6.3 Tuner Programming.
• 4.0 Tuner Control
• 5.0 Tuner Read/write Registers
  • 5.1 General Purpose Port Control. Register 0x3E (R/W)
    • 5.1.1 Tuner 2-wire Bus Address. Register 0x23 (R/W)
    • 5.1.2 Tuner Start Division Ratio. Registers 0x24 - 0x25 (R/W)
    • 5.1.3 Tuner Control Data. Registers 0x26 � 0x27 (R/W)
    • 5.1.4 Tuner Start Commands. Register 0x30 (R/W)
  • 5.2 Tuner Read Registers
    • 5.2.1 Tuner events. Register 0x02 (R)
    • 5.2.2 Tuner Status. Register 0x07 (R)
    • 5.2.3 2-wire Bus Status. Register 0x08 (R)
• 6.0 COFDM Demodulator
  • 6.1 COFDM Read/Write Registers
    • 6.1.1 Interrupt Enable for COFDM. Register 0x31 (R/W)
    • 6.1.2 COFDM Output Control. Register 0x33 (R/W)
    • 6.1.3 Co-channel interference suppression filter Control. Register 0x34 (R/W)
    • 6.1.4 Co-channel interference suppression filter frequency. Register 0x35 (R/W)
    • 6.1.5 Nominal input frequency. Registers 0x36 � 0x37 (R/W)
    • 6.1.6 Timing Recovery Loop nominal rate. Registers 0x38 � 0x39 (R/W)
    • 6.1.7 Transmission Parameter Signalling Set byte 1. Register 0x3A (R/W)
    • 6.1.8 Transmission Parameter Signalling Set byte 2. Register 0x3B (R/W)
    • 6.1.9 Transmission Parameter Signalling Set byte 3. Register 0x3C (R/W)
    • 6.1.10 Transmission Parameter Signalling Set byte 4. Register 0x3D (R/W)
    • 6.1.11 Swap real and imaginary components. Register 0x48 (R/W)
    • 6.1.12 Symbol timing Recovery Control. Register 0x49 (R/W)
    • 6.1.13 PPM Control byte 1. Register 0x4C (R/W)
    • 6.1.14 Channel Corrector Control byte 1. Register 0x50 (R/W)
    • 6.1.15 COFDM state override control. Register 0x55 (R/W)
  • 6.2 COFDM Read Registers
    • 6.2.1 COFDM events. Register 0x00 (R)
    • 6.2.2 COFDM Status. Register 0x05 (R)
    • 6.2.3 Symbol Timing Recovery Status. Register 0x0B (R)
    • 6.2.4 PPM pilot correlator amplitude. Register 0x0C (R)
    • 6.2.5 Timing Recovery Loop Time. Registers 0x0D � 0x0E (R)
    • 6.2.6 Carrier Recovery Loop Frequency. Registers 0x0F � 0x11 (R)
    • 6.2.7 Channel Corrector Signal to Noise Ratio. Register 0x12 (R)
    • 6.2.8 Transmission Parameter Signalling received byte 1. Register 0x13 (R)
    • 6.2.9 Transmission Parameter Signalling received byte 2. Register 0x14 (R)
    • 6.2.10 Transmission Parameter Signalling received byte 3. Register 0x15 (R)
    • 6.2.11 Transmission Parameter Signalling received byte 4. Register 0x16 (R)
    • 6.2.12 Transmission Parameter Signalling received bytes 5-6. Registers 0x17 � 0x18 (R)
    • 6.2.13 Co and Adjacent channel interference suppression AGC. Register 0x19 (R)
• 7.0 Forward Error Correction
  • 7.1 FEC Read/Write Registers
    • 7.1.1 Interrupt Enable for FEC. Register 0x32 (R/W)
    • 7.1.2 FEC Status output enable. Register 0x3F (R/W)
    • 7.1.3 Viterbi Error Period. Registers 0x40 � 0x42 (R/W)
    • 7.1.4 Viterbi Error Count Control. Register 0x43 (R/W)
    • 7.1.5 Reed Solomon error period. Registers 0x44 � 0x45 (R/W)
    • 7.1.6 Viterbi Maximum Error. Register 0x5D (R/W)
    • 7.1.7 De-gapper mode. Register 0x62 (R/W)
    • 7.1.8 FEC set-up. Register 0x65 (R/W)
  • 7.2 FEC Read Registers
    • 7.2.1 FEC Events. Register 0x01 (R)
    • 7.2.2 FEC Status. Register 0x06 (R)
    • 7.2.3 Viterbi Error Count. Registers 0x1A � 0x1C (R)
    • 7.2.4 Reed Solomon Bit Error Count. Registers 0x1D � 0x1F (R)
    • 7.2.5 Reed Solomon Uncorrected Block Count. Registers 0x20 � 0x21 (R)
• 8.0 Automatic Gain Control
  • 8.1 Read/Write Registers
    • 8.1.1 AGC output Control. Register 0x46 (R/W)
    • 8.1.2 AGC target value. Register 0x47 (R/W)
    • 8.1.3 AGC2 offset value. Register 0x76 (R/W)
    • 8.1.4 AGC2 maximum value. Register 0x77 (R/W)
    • 8.1.5 AGC2 minimum value. Register 0x78 (R/W)
  • 8.2 AGC Read Registers
    • 8.2.1 AGC gain. Registers 0x09 � 0x0A (R)
• 9.0 MPEG Packet Data Output.
  • 9.1 MPEG Output Control Read/Write Registers
    • 9.1.1 Configuration Set-up byte 1. Register 0x7D (R/W)
    • 9.1.2 MPEG output clock ratio. Register 0x7C (R/W)
  • 9.2 Data Output Header Format
  • 9.3 MPEG Data Output Signals
  • 9.4 Data Output Timing
• 10.0 Chip Identification Read Register
  • 10.1 Chip Identification. Register 0x7F (R)
• 11.0 Secondary Registers for Test and De-bugging
  • 11.1 COFDM De-bugging Read/Write Registers
    • 11.1.1 FFT Control. Register 0x4A (R/W)
    • 11.1.2 Symbol Carrier Recovery Control. Register 0x4B (R/W)
    • 11.1.3 PPM Control byte 2. Register 0x4D (R/W)
    • 11.1.4 Timing Recovery Loop Control. Register 0x4E (R/W)
    • 11.1.5 Carrier Recovery Loop Control. Register 0x4F (R/W)
    • 11.1.6 Channel Corrector Control byte 2. Register 0x51 (R/W)
    • 11.1.7 Symbol De-mapper Control. Register 0x52 (R/W)
    • 11.1.8 Transmission Signalling Parameters Control. Register 0x53 (R/W)
    • 11.1.9 Control FFT Output Symbol Number Counter. Register 0x54 (R/W)
    • 11.1.10 Symbol Timing Recovery NCO. Registers 0x56 � 0x57 (R/W)
    • 11.1.11 Symbol Timing Recovery Offset. Registers 0x58 � 0x59 (R/W)
    • 11.1.12 Test. Register 0x5A (R/W)
    • 11.1.13 Test mode. Register 0x69 (R/W)
    • 11.1.14 COFDM memory access select. Registers 0x6B � 0x71 (R/W)
  • 11.2 COFDM De-bugging Read Register
    • 11.2.1 COFDM revision number. Register 0x6A (R)
  • 11.3 FEC De-bugging Read/Write Registers
    • 11.3.1 Viterbi Bit Error Rate Period. Register 0x5B (R/W)
    • 11.3.2 Viterbi Bit Error Rate Limit. Register 0x5C (R/W)
    • 11.3.3 De-gapper Offset Error. Registers 0x5E � 0x5F (R/W)
    • 11.3.4 De-gapper programmable start offset. Register 0x60 (R/W)
    • 11.3.5 De-gapper programmable period factor. Register 0x61 (R/W)
    • 11.3.6 Byte Align set-up byte 1. Register 0x63 (R/W)
    • 11.3.7 Byte Align set-up byte 2. Register 0x64 (R/W)
    • 11.3.8 Program sync byte. Register 0x66 (R/W)
  • 11.4 FEC De-bugging Read Register
    • 11.4.1 De-gapper Test Outputs. Register 0x72 (R)
  • 11.5 AGC, ADC and Test Mode De-bugging Read/Write Registers
    • 11.5.1 AGC manual setting. Registers 0x67 � 0x68 (R/W)
    • 11.5.2 ADC test modes. Registers 0x73 � 0x74 (R/W)
    • 11.5.3 Test Mode Control. Register 0x75 (R/W)
    • 11.5.4 COFDM Re-acquisition Time-out. Register 0x79 (R/W)
    • 11.5.5 FEC Re-acquisition Time-out. Register 0x7A (R/W)
    • 11.5.6 FEC Loss Time-out. Register 0x7B (R/W)
• 12.0 Microprocessor Control.
  • 12.1 Primary 2-wire Bus Interface.
  • 12.2 Secondary 2-wire Bus for Tuner Control: Master Mode
  • 12.3 Examples of 2-wire Bus Messages:
  • 12.4 Primary 2-wire bus timing.
• 13.0 Electrical Characteristics
  • 13.1 Recommended Operating Conditions
  • 13.2 Absolute Maximum Ratings
  • 13.3 Crystal Specification
  • 13.4 DC Electrical Characteristics
  • 13.5 Pinout Description
  • 13.6 Alphabetical Pin List
• 14.0 Application Diagram
• 15.0 MT351 Register Map
  • 15.1 Read Only Registers
  • 15.2 Read/Write registers