ChipFind - документация

Электронный компонент: MT8870DNR

Скачать:  PDF   ZIP
4-11
MT8870D/MT8870D-1
Integrated DTMF Receiver
Features
Complete DTMF Receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
Central office quality
Power-down mode
Inhibit mode
Backward compatible with
MT8870C/MT8870C-1
Applications
Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
Paging systems
Repeater systems/mobile radio
Credit card systems
Remote control
Personal computers
Telephone answering machine
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses
digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
Ordering Information
MT8870DE/DE-1
18 Pin Plastic DIP
MT8870DS/DS-1
18 Pin SOIC
MT8870DN/DN-1
20 Pin SSOP
-40
C to +85
C
Figure 1 - Functional Block Diagram
PWDN
IN +
IN -
GS
OSC1
OSC2
St/GT
ESt
STD
TOE
Q1
Q2
Q3
Q4
VDD
VSS
VRef
INH
Bias
Circuit
Dial
Tone
Filter
High Group
Filter
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
St
GT
Steering
Logic
Chip
Power
Chip
Bias
VRef
Buffer
Zero Crossing
Detectors
to all
Chip
Clocks
ISSUE 5
March 1997
ISO
2
-CMOS
MT8870D/MT8870D-1
ISO
2
-CMOS
4-12
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18
20
1
1
IN+
Non-Inverting Op-Amp
(Input)
.
2
2
IN-
Inverting Op-Amp
(Input)
.
3
3
GS
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
V
Ref
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
5
5
INH
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
6
6
PWDN
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
OSC1
Clock
(Input)
.
8
9
OSC2
Clock
(Output)
. A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
V
SS
Ground
(Input)
. 0V typical.
10
11
TOE
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11-
14
12-
15
Q1-Q4
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15
17
StD
Delayed Steering (Output).
Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
16
18
ESt
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
17
19
St/GT
Steering Input/Guard time (Output) Bidirectional.
A voltage greater than V
TSt
detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18
20
V
DD
Positive power supply (Input)
. +5V typical.
7,
16
NC
No Connection.
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN PLASTIC DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NC
ISO
2
-CMOS
MT8870D/MT8870D-1
4-13
Functional Description
The MT8870D/MT8870D-1 monolithic DTMF
receiver offers small size, low power consumption
and high performance. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection (see Figure 3). Each
filter output is followed by a single order switched
capacitor filter section which smooths the signals
prior to limiting. Limiting is performed by high-gain
comparators which are provided with hysteresis to
prevent detection of unwanted low-level signals. The
outputs of the comparators provide full rail logic
swings at the frequencies of the incoming DTMF
signals.
Decoder Section
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
Figure 4 - Basic Steering Circuit
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the "signal condition" in
some industry specifications) the "Early Steering"
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see "Steering Circuit").
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 4) to
rise as the capacitor discharges. Provided signal
V
DD
C
v
c
V
DD
St/GT
ESt
StD
MT8870D/
MT8870D-1
R
t
GTA
=(RC)In(V
DD
/V
TSt
)
t
GTP
=(RC)In[V
DD
/(V
DD
-V
TSt
)]
Figure 3 - Filter Response
0
10
20
30
40
50
ATTENUATION
(dB)
X
Y
A B
C
D
1kHz
E
F
G
H
PRECISE
DIAL TONES
X=350 Hz
Y=440 Hz
DTMF TONES
A=697 Hz
B=770 Hz
C=852 Hz
D=941 Hz
E=1209 Hz
F=1336 Hz
G=1477 Hz
H=1633 Hz
FREQUENCY (Hz)
MT8870D/MT8870D-1
ISO
2
-CMOS
4-14
condition is maintained (ESt remains high) for the
validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the
steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v
c
to V
DD
. GT continues to drive
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 4 is applicable. Component
values are chosen according to the formula:
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see Figure
11) and t
REC
is the minimum signal duration to be
recognized by the receiver. A value for C of 0.1
F is
Figure 5 - Guard Time Adjustment
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON`T CARE
recommended for most applications, leaving R to be
selected by the designer.
Different steering arrangements may be used to
select independently the guard times for tone
present (t
GTP
) and tone absent (t
GTA
). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters
such as talk off and noise immunity. Increasing t
REC
improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short t
REC
with
a long t
DO
would be appropriate for extremely noisy
environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 5.
V
DD
St/GT
ESt
C
1
R
1
R
2
a) decreasing t
GTP
; (t
GTP
<t
GTA
)
t
GTP
=(R
P
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
t
GTA
=(R
1
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
V
DD
St/GT
ESt
C
1
R
1
R
2
t
GTP
=(R
1
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
t
GTA
=(R
P
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
b) decreasing t
GTA
; (t
GTP
>t
GTA
)
Digit
TOE
INH
ESt
Q
4
Q
3
Q
2
Q
1
ANY
L
X
H
Z
Z
Z
Z
1
H
X
H
0
0
0
1
2
H
X
H
0
0
1
0
3
H
X
H
0
0
1
1
4
H
X
H
0
1
0
0
5
H
X
H
0
1
0
1
6
H
X
H
0
1
1
0
7
H
X
H
0
1
1
1
8
H
X
H
1
0
0
0
9
H
X
H
1
0
0
1
0
H
X
H
1
0
1
0
*
H
X
H
1
0
1
1
#
H
X
H
1
1
0
0
A
H
L
H
1
1
0
1
B
H
L
H
1
1
1
0
C
H
L
H
1
1
1
1
D
H
L
H
0
0
0
0
A
H
H
L
undetected, the output code
will remain the same as the
previous detected code
B
H
H
L
C
H
H
L
D
H
H
L
ISO
2
-CMOS
MT8870D/MT8870D-1
4-15
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (V
Ref
) which is used to bias the
inputs at mid-rail. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the op-amp connected for unity gain and V
Ref
biasing the input at
1
/
2
V
DD
. Figure 6 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R
5
.
Crystal Oscillator
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single-
Ended Input Configuration). However, it is possible to
configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with unbalanced
loading are not a concern with the arrangement
shown, i.e., precision balancing capacitors are not
required.
Figure 6 - Differential Input Configuration
Figure 7 - Oscillator Connection
Table 2. Recommended Resonator Specifications
Note: Qm=quality factor of RLC model, i.e., 1/2
R1C1.
Parameter
Unit
Resonator
R1
Ohms
10.752
L1
mH
.432
C1
pF
4.984
C0
pF
37.915
Qm
-
896.37
f
%
0.2%
C
1
R
1
C
2
R
4
R
3
IN+
IN-
+
-
R
5
GS
R
2
V
Ref
MT8870D/
MT8870D-1
Differential Input Amplifier
C
1
=C
2
=10 nF
R
1
=R
4
=R
5
=100 k
R
2
=60k
, R
3
=37.5 k
All resistors are
1% tolerance.
All capacitors are
5% tolerance.
R
3
=
R
2
R
5
R
2
+R
5
VOLTAGE GAIN (A
v
diff)=
R
5
R
1
INPUT IMPEDANCE
(Z
INDIFF
) = 2
R
1
2
+
1
c
2
OSC1
OSC2
OSC2
OSC1
C
X-tal
C
To OSC1 of next
MT8870D/MT8870D-1
C=30 pF
X-tal=3.579545 MHz
MT8870D/MT8870D-1
ISO
2
-CMOS
4-16
Applications
RECEIVER SYSTEM FOR BRITISH TELECOM
SPEC POR 1151
The circuit shown in Fig. 9 illustrates the use of
MT8870D-1 device in a typical receiver system. BT
Spec defines the input signals less than -34 dBm as
the non-operate level. This condition can be attained
by choosing a suitable values of R
1
and R
2
to
provide 3 dB attenuation, such that -34 dBm input
signal will correspond to -37 dBm at the gain setting
pin GS of MT8870D-1. As shown in the diagram, the
component values of R
3
and C
2
are the guard time
requirements when the total component tolerance is
6%. For better performance, it is recommended to
use the non-symmetric guard time circuit in Fig. 8.
Figure 8 - Non-Symmetric Guard Time Circuit
t
GTP
=(R
P
C
1
)In[V
DD
/(V
DD
-V
TSt
)]
t
GTA
=(R
1
C
1
)In(V
DD
/V
TSt
)
R
P
=(R
1
R
2
)/(R
1
+R
2
)
V
DD
St/GT
ESt
C
1
R
2
R
1
Notes:
R
1
=368K
1%
R
2
=2.2M
1%
C
1
=100nF
5%
Figure 9 - Single-Ended Input Configuration for BT or CEPT Spec
IN+
IN-
GS
V
Ref
INH
PWDN
OSC 1
OSC 2
V
SS
TOE
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
DTMF
Input
C
1
R
1
R
2
X
1
V
DD
C
2
R
3
MT8870D-1
NOTES:
R
1
= 102K
1%
R
2
= 71.5K
1%
R
3
= 390K
1 %
C
1
,C
2
= 100 nF
5%
X
1
= 3.579545 MHz
0.1%
V
DD
= 5.0V
5%
ISO
2
-CMOS
MT8870D/MT8870D-1
4-17
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate above 75
C at 16 mW /
C. All leads soldered to board.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
1
DC Power Supply Voltage
V
DD
7
V
2
Voltage on any pin
V
I
V
SS
-0.3
V
DD
+0.3
V
3
Current at any pin (other than supply)
I
I
10
mA
4
Storage temperature
T
STG
-65
+150
C
5
Package power dissipation
P
D
500
mW
Recommended Operating Conditions -
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
DC Power Supply Voltage
V
DD
4.75
5.0
5.25
V
2
Operating Temperature
T
O
-40
+85
C
3
Crystal/Clock Frequency
fc
3.579545
MHz
4
Crystal/Clock Freq.Tolerance
fc
0.1
%
DC Electrical Characteristics -
V
DD
=5.0V
5%, V
SS
=0V, -40
C
T
O
+85
C, unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
S
U
P
P
L
Y
Standby supply current
I
DDQ
10
25
A
PWDN=V
DD
2
Operating supply current
I
DD
3.0
9.0
mA
3
Power consumption
P
O
15
mW
fc=3.579545 MHz
4
I
N
P
U
T
S
High level input
V
IH
3.5
V
V
DD
=5.0V
5
Low level input voltage
V
IL
1.5
V
V
DD
=5.0V
6
Input leakage current
I
IH
/I
IL
0.1
A
V
IN
=V
SS
or V
DD
7
Pull up (source) current
I
SO
7.5
20
A
TOE (pin 10)=0,
V
DD
=5.0V
8
Pull down (sink) current
I
SI
15
45
A
INH=5.0V, PWDN=5.0V,
V
DD
=5.0V
9
Input impedance (IN+, IN-)
R
IN
10
M
@ 1 kHz
10
Steering threshold voltage
V
TSt
2.2
2.4
2.5
V
V
DD
= 5.0V
11
O
U
T
P
U
T
S
Low level output voltage
V
OL
V
SS
+0.03
V
No load
12
High level output voltage
V
OH
V
DD
-0.03
V
No load
13
Output low (sink) current
I
OL
1.0
2.5
mA
V
OUT
=0.4 V
14
Output high (source) current
I
OH
0.4
0.8
mA
V
OUT
=4.6 V
15
V
Ref
output voltage
V
Ref
2.3
2.5
2.7
V
No load, V
DD
= 5.0V
16
V
Ref
output resistance
R
OR
1
k
MT8870D/MT8870D-1
ISO
2
-CMOS
4-18
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
*
NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by
1.5 %
2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz)
2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
Operating Characteristics
- V
DD
=5.0V
5%, V
SS
=0V, -40
C
T
O
+85
C ,unless otherwise stated.
Gain Setting Amplifier
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Input leakage current
I
IN
100
nA
V
SS
V
IN
V
DD
2
Input resistance
R
IN
10
M
3
Input offset voltage
V
OS
25
mV
4
Power supply rejection
PSRR
50
dB
1 kHz
5
Common mode rejection
CMRR
40
dB
0.75 V
V
IN
4.25 V biased
at V
Ref
=2.5 V
6
DC open loop voltage gain
A
VOL
32
dB
7
Unity gain bandwidth
f
C
0.30
MHz
8
Output voltage swing
V
O
4.0
V
pp
Load
100 k to V
SS
@ GS
9
Maximum capacitive load (GS)
C
L
100
pF
10
Resistive load (GS)
R
L
50
k
11
Common mode range
V
CM
2.5
V
pp
No Load
MT8870D AC Electrical Characteristics
-
V
DD
=5.0V
5%, V
SS
=0V, -40
C
T
O
+85
C , using Test Circuit shown in
Figure 10.
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Valid input signal levels (each
tone of composite signal)
-29
+1
dBm
1,2,3,5,6,9
27.5
869
mV
RMS
1,2,3,5,6,9
2
Negative twist accept
8
dB
2,3,6,9,12
3
Positive twist accept
8
dB
2,3,6,9,12
4
Frequency deviation accept
1.5% 2 Hz
2,3,5,9
5
Frequency deviation reject
3.5%
2,3,5,9
6
Third tone tolerance
-16
dB
2,3,4,5,9,10
7
Noise tolerance
-12
dB
2,3,4,5,7,9,10
8
Dial tone tolerance
+22
dB
2,3,4,5,8,9,11
ISO
2
-CMOS
MT8870D/MT8870D-1
4-19
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
*
NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by
1.5 %
2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz)
2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.
13. Guaranteed by design and characterization.
MT8870D-1 AC Electrical Characteristics
- V
DD
=5.0V
5%, V
SS
=0V, -40
C
T
O
+85
C , using Test Circuit shown
in Figure 10.
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Valid input signal levels (each
tone of composite signal)
-31
+1
dBm
Tested at V
DD
=5.0V
1,2,3,5,6,9
21.8
869
mV
RMS
2
Input Signal Level Reject
-37
dBm
Tested at V
DD
=5.0V
1,2,3,5,6,9
10.9
mV
RMS
3
Negative twist accept
8
dB
2,3,6,9,13
4
Positive twist accept
8
dB
2,3,6,9,13
5
Frequency deviation accept
1.5% 2 Hz
2,3,5,9
6
Frequency deviation reject
3.5%
2,3,5,9
7
Third zone tolerance
-18.5
dB
2,3,4,5,9,12
8
Noise tolerance
-12
dB
2,3,4,5,7,9,10
9
Dial tone tolerance
+22
dB
2,3,4,5,8,9,11
MT8870D/MT8870D-1
ISO
2
-CMOS
4-20
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
Used for guard-time calculation purposes only.
2.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, t
PU
equals time from PDWN going low until ESt going high.
Figure 10 - Single-Ended Input Configuration
AC Electrical Characteristics
- V
DD
=5.0V
5%, V
SS
=0V, -40
C
To +85
C , using Test Circuit shown in Figure 10.
Characteristics
Sym
Min
Typ
Max
Units
Conditions
1
T
I
M
I
N
G
Tone present detect time
t
DP
5
11
14
ms
Note 1
2
Tone absent detect time
t
DA
0.5
4
8.5
ms
Note 1
3
Tone duration accept
t
REC
40
ms
Note 2
4
Tone duration reject
t
REC
20
ms
Note 2
5
Interdigit pause accept
t
ID
40
ms
Note 2
6
Interdigit pause reject
t
DO
20
ms
Note 2
7
O
U
T
P
U
T
S
Propagation delay (St to Q)
t
PQ
8
11
s
TOE=V
DD
8
Propagation delay (St to StD)
t
PStD
12
16
s
TOE=V
DD
9
Output data set up (Q to StD)
t
QStD
3.4
s
TOE=V
DD
10
Propagation delay (TOE to Q ENABLE)
t
PTE
50
ns
load of 10 k
,
50 pF
11
Propagation delay (TOE to Q DISABLE)
t
PTD
300
ns
load of 10 k
,
50 pF
12
P
D
W
N
Power-up time
t
PU
30
ms
Note 3
13
Power-down time
t
PD
20
ms
14
C
L
O
C
K
Crystal/clock frequency
f
C
3.5759
3.5795
3.5831
MHz
15
Clock input rise time
t
LHCL
110
ns
Ext. clock
16
Clock input fall time
t
HLCL
110
ns
Ext. clock
17
Clock input duty cycle
DC
CL
40
50
60
%
Ext. clock
18
Capacitive load (OSC2)
C
LO
30
pF
IN+
IN-
GS
V
Ref
INH
PDWN
OSC 1
OSC 2
V
SS
TOE
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
DTMF
Input
C
1
R
1
R
2
X-tal
V
DD
C
2
R
3
NOTES:
R
1
,R
2
=100K
1%
R
3
=300K
1%
C
1
,C
2
=100 nF
5%
X-tal=3.579545 MHz
0.1%
MT8870D/MT8870D-1
ISO
2
-CMOS
MT8870D/MT8870D-1
4-21
Figure 11 - Timing Diagram
EXPLANATION OF EVENTS
EXPLANATION OF SYMBOLS
A)
TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B)
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS
C)
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID
TONE.
D)
OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E)
TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH
IMPEDANCE).
F)
ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G)
END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID
TONE.
V
in
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q
1
-Q
4
4-BIT DECODED TONE OUTPUT.
StD
DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE
TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q
1
-Q
4
TO ITS HIGH IMPEDANCE STATE.
t
REC
MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID
t
REC
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION
t
ID
MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.
t
DO
MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
t
DP
TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
t
DA
TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
t
GTP
GUARD TIME, TONE PRESENT.
t
GTA
GUARD TIME, TONE ABSENT.
V
in
ESt
St/GT
Q
1
-Q
4
StD
TOE
EVENTS
A
B
C
D
E
F
G
t
REC
t
REC
t
ID
t
DO
TONE #n
TONE
#n + 1
TONE
#n + 1
t
DP
t
DA
t
GTP
t
GTA
t
PQ
t
QStD
t
PSrD
t
PTD
t
PTE
# n
# (n + 1)
HIGH IMPEDANCE
DECODED TONE # (n-1)
V
TSt
MT8870D/MT8870D-1
ISO
2
-CMOS
4-22
Notes:
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
A
2
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
C
0.008
(0.203)
0.014 (0.356)
0.008 (0.203)
0.014(0.356)
0.008 (0.203)
0.014 (0.356)
0.008 (0.203)
0.014 (0.356)
D
0.355 (9.02)
0.400 (10.16)
0.780 (19.81)
0.800 (20.32)
0.880 (22.35)
0.920 (23.37)
0.980 (24.89)
1.060 (26.9)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
E
1
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
L
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
e
B
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
e
C
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
e
C
General-8
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin
24-Pin
28-Pin
40-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.250 (6.35)
0.250 (6.35)
0.250 (6.35)
A
2
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.15)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
C
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
D
1.050 (26.67)
1.120 (28.44)
1.150 (29.3)
1.290 (32.7)
1.380 (35.1)
1.565 (39.7)
1.980 (50.3)
2.095 (53.2)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.390 (9.91)
0.430 (10.92)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
E
0.290 (7.37)
.330 (8.38)
E
1
0.330 (8.39)
0.380 (9.65)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
E
1
0.246 (6.25)
0.254 (6.45)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.400 BSC (10.16)
0.600 BSC (15.24)
0.600 BSC (15.24)
0.600 BSC (15.24)
e
A
0.300 BSC (7.62)
e
B
0.430 (10.92)
L
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
15
15
15
15
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
Shaded areas for 300 Mil Body Width 24 PDIP only
Package Outlines
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
DIM
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A
1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.030
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.4625
(11.75)
0.496
(12.60)
0.512
(13.00)
0.5985
(15.2)
0.614
(15.6)
0.697
(17.7)
0.7125
(18.1)
E
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
e
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Pin 1
A
1
B
e
E
A
L
H
C
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
D
L
4 mils (lead coplanarity)
General-7
Package Outlines
Small Shrink Outline Package (SSOP) - N Suffix
Pin 1
A
1
B
e
D
E
A
L
H
C
A
2
Dim
20-Pin
24-Pin
28-Pin
48-Pin
Min
Max
Min
Max
Min
Max
Min
Max
A
0.079
(2)
-
0.079
(2)
0.079
(2)
0.095
(2.41)
0.110
(2.79)
A
1
0.002
(0.05)
0.002
(0.05)
0.002
(0.05)
0.008
(0.2)
0.016
(0.406)
B
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.008
(0.2)
0.0135
(0.342)
C
0.008
(0.21)
0.008
(0.21)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.42
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
A
2
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.26)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
General-11
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
A
2
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
C
0.008
(0.203)
0.014 (0.356)
0.008 (0.203)
0.014(0.356)
0.008 (0.203)
0.014 (0.356)
0.008 (0.203)
0.014 (0.356)
D
0.355 (9.02)
0.400 (10.16)
0.780 (19.81)
0.800 (20.32)
0.880 (22.35)
0.920 (23.37)
0.980 (24.89)
1.060 (26.9)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
E
1
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
L
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
e
B
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
e
C
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
e
C
General-8
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin
24-Pin
28-Pin
40-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.250 (6.35)
0.250 (6.35)
0.250 (6.35)
A
2
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.15)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
C
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
D
1.050 (26.67)
1.120 (28.44)
1.150 (29.3)
1.290 (32.7)
1.380 (35.1)
1.565 (39.7)
1.980 (50.3)
2.095 (53.2)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.390 (9.91)
0.430 (10.92)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
E
0.290 (7.37)
.330 (8.38)
E
1
0.330 (8.39)
0.380 (9.65)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
E
1
0.246 (6.25)
0.254 (6.45)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.400 BSC (10.16)
0.600 BSC (15.24)
0.600 BSC (15.24)
0.600 BSC (15.24)
e
A
0.300 BSC (7.62)
e
B
0.430 (10.92)
L
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
15
15
15
15
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
Shaded areas for 300 Mil Body Width 24 PDIP only
Package Outlines
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
DIM
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A
1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.030
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.4625
(11.75)
0.496
(12.60)
0.512
(13.00)
0.5985
(15.2)
0.614
(15.6)
0.697
(17.7)
0.7125
(18.1)
E
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
e
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Pin 1
A
1
B
e
E
A
L
H
C
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
D
L
4 mils (lead coplanarity)
General-7
Package Outlines
Small Shrink Outline Package (SSOP) - N Suffix
Pin 1
A
1
B
e
D
E
A
L
H
C
A
2
Dim
20-Pin
24-Pin
28-Pin
48-Pin
Min
Max
Min
Max
Min
Max
Min
Max
A
0.079
(2)
-
0.079
(2)
0.079
(2)
0.095
(2.41)
0.110
(2.79)
A
1
0.002
(0.05)
0.002
(0.05)
0.002
(0.05)
0.008
(0.2)
0.016
(0.406)
B
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.008
(0.2)
0.0135
(0.342)
C
0.008
(0.21)
0.008
(0.21)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.42
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
A
2
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.26)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
General-11
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
0.210 (5.33)
A
2
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
C
0.008
(0.203)
0.014 (0.356)
0.008 (0.203)
0.014(0.356)
0.008 (0.203)
0.014 (0.356)
0.008 (0.203)
0.014 (0.356)
D
0.355 (9.02)
0.400 (10.16)
0.780 (19.81)
0.800 (20.32)
0.880 (22.35)
0.920 (23.37)
0.980 (24.89)
1.060 (26.9)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
E
1
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
L
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.150 (3.81)
e
B
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
0.430 (10.92)
e
C
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
0
0.060 (1.52)
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
e
C
General-8
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin
24-Pin
28-Pin
40-Pin
Plastic
Plastic
Plastic
Plastic
Min
Max
Min
Max
Min
Max
Min
Max
A
0.210 (5.33)
0.250 (6.35)
0.250 (6.35)
0.250 (6.35)
A
2
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b
2
0.045 (1.15)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
C
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
D
1.050 (26.67)
1.120 (28.44)
1.150 (29.3)
1.290 (32.7)
1.380 (35.1)
1.565 (39.7)
1.980 (50.3)
2.095 (53.2)
D
1
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
E
0.390 (9.91)
0.430 (10.92)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
E
0.290 (7.37)
.330 (8.38)
E
1
0.330 (8.39)
0.380 (9.65)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
E
1
0.246 (6.25)
0.254 (6.45)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
e
A
0.400 BSC (10.16)
0.600 BSC (15.24)
0.600 BSC (15.24)
0.600 BSC (15.24)
e
A
0.300 BSC (7.62)
e
B
0.430 (10.92)
L
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
0.115 (2.93)
0.200 (5.08)
15
15
15
15
E
1
3
2
1
E
n-2 n-1 n
L
D
D
1
b
2
A
2
e
b
C
e
A
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
e
B
Shaded areas for 300 Mil Body Width 24 PDIP only
Package Outlines
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
DIM
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A
1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.030
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.4625
(11.75)
0.496
(12.60)
0.512
(13.00)
0.5985
(15.2)
0.614
(15.6)
0.697
(17.7)
0.7125
(18.1)
E
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
e
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Pin 1
A
1
B
e
E
A
L
H
C
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
D
L
4 mils (lead coplanarity)
General-7
Package Outlines
Small Shrink Outline Package (SSOP) - N Suffix
Pin 1
A
1
B
e
D
E
A
L
H
C
A
2
Dim
20-Pin
24-Pin
28-Pin
48-Pin
Min
Max
Min
Max
Min
Max
Min
Max
A
0.079
(2)
-
0.079
(2)
0.079
(2)
0.095
(2.41)
0.110
(2.79)
A
1
0.002
(0.05)
0.002
(0.05)
0.002
(0.05)
0.008
(0.2)
0.016
(0.406)
B
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.008
(0.2)
0.0135
(0.342)
C
0.008
(0.21)
0.008
(0.21)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.42
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
A
2
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.26)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
General-11
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively
"Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the
application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may
result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under
patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified
that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property
rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I
2
C components conveys a licence under the Philips I
2
C Patent rights to use these components in an I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products
visit our Web Site at