4-71
Features
Complete DTMF transmitter/receiver
Low voltage operation (2.7-3.6V)
Adaptive micro interface enables compatibility
with Intel and Motorola processors
DTMF transmitter/receiver power-down via
register control or power-down pin
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Pay phones
Remote monitor/Control systems
Description
The MT88L85 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call
progress filter can be selected allowing a
microprocessor to analyze call progress tones.
The MT88L85 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L85 provides enhanced power-down
features. The transmitter and receiver may
independently be powered down via register control.
Ordering Information
MT88L85AE
24 Pin Plastic DIP (300 mil)
MT88L85AN
24 Pin SSOP
MT88L85AP
28 Pin PLCC
-40
C to +85
C
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
V
DD
V
Ref
V
SS
ESt
St/GT
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
PWDN
DS5032
ISSUE 3
January 1999
MT88L85
3V Integrated DTMF Transceiver with
Power-Down and Adaptive Micro Interface
MT88L85
4-72
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
24
28
1
1
IN+
Non-inverting
op-amp input.
2
2
IN-
Inverting
op-amp input.
3
4
GS
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
6
V
Ref
Reference Voltage
output (V
DD
/2).
5
7
V
SS
Ground (0V).
6
8
OSC1
Oscillator
input. This pin can also be driven directly by an external clock. CMOS
compatible.
7
9
OSC2
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
10
12
TONE
Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register
A (CRA) is set to low. Requires resistive termination to Vss.
11
13 R/W
(
WR
)
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
12
14
CS
Chip Select
input must be gated externally by either address strobe (AS), valid memory
address (VMA) or address latch enable (ALE) signal, depending on processor used. See
Figure 12. Must not be tied low. CMOS compatible.
13
15
RS0
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
14
17
DS
(
RD) (Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is only
required when the device is being accessed. CMOS compatible.
15
18
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See
Figure 10.
16
19
PWDN
Power-down
(input). Active High. Powers down the device and inhibits the oscillator. IRQ
and TONE output are high impedance. Data bus is held in tri-state. This pin has no internal
pulldown resistor. Therefore, must be tied to logic low when not used.
18-
21
21-
24
D0-D3
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). CMOS compatible.
22
26
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
24 PIN DIP/SSOP
27
4
3
2
1
28
26
5
6
7
8
9
10
11
25
24
23
22
21
20
19
17
12
13
14
15
16
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
GS
NC
IN-
IN+
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
NC
TONE
R/W
/W
R
C
S
RS0
NC
DS/RD
I
R
Q
/CP
28 PIN PLCC
MT88L85
4-73
Functional Description
The MT88L85 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an internal
gain setting amplifier and a DTMF generator, which
employs a burst counter to synthesize precise tone
bursts and pauses. A call progress mode can be
selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows various microcontrollers to access
the MT88L85 internal registers.
Power-Down
The MT88L85 provides enhanced power-down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks can be independently powered down
via register control. When asserted, the RxEN
control bit powers down all analog and digital circuitry
associated solely with the DTMF and Call Progress
receiver. The TOUT control bit is used to disable the
transmitter and put all circuitry associated only with
the DTMF transmitter in power-down mode. With the
TOUT control bit asserted, the TONE output pin is
held in a high impedance (floating) state. When both
power-down control bits are asserted, circuits utilized
by both the DTMF transmitter and receiver are also
powered down. This power-down control disables the
crystal oscillators, and the VRef generator. In
addition, the IRQ, TONE output and DATA pins are
held in a high impedance state. Finally, the whole
device is put in a power-down state when the PWDN
pin is asserted.
Input Configuration
The input arrangement of the MT88L85 provides a
differential-input operational amplifier as well as a
bias source (V
Ref
), which is used to bias the inputs at
V
DD
/2. Provision is made for connection of a feedback
resistor to the op-amp output (GS) for gain
adjustment.
For applications which are required to meet a
guaranteed RX input level of -29dBm over the full
temperature and supply voltage range, a unity gain
input configuration as shown in Figures 3 and 4 can be
used.
For applications which require signal detection lower
than -29dBm, the external resistors can be configured
to give adequate gain. For example, if the application
requires tone detection of -31dB, the input gain can
be set to +2dB with the external resistors (see Figures
13 and 14 for value of resistors). However, when +2dB
gain is used, the corresponding maximum input signal
level must not exceed -6dBm.
Receiver Section
Separation of the low and high group tones is achieved
by applying the DTMF signal to the inputs of two sixth-
order switched capacitor bandpass filters, the
bandwidths of which correspond to the low and high
group frequencies (see Table 1). The filters also
incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which
are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the
comparators provide full rail logic swings at the
frequencies of the incoming DTMF signals.
Figure 3 - Single-Ended Input Configuration
C
R
IN
R
F
IN+
IN-
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT88L85
23
27
St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
24
28
V
DD
Positive power supply (3V typ.).
8,9
17
3,5,
10,11
16,
20,
25
NC
No Connection.
Pin Description
Pin #
Name
Description
24
28
MT88L85
4-74
Figure 4 - Differential Input Configuration
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the "signal condition" in
some industry specifications) the "Early Steering"
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT continues
to drive high as long as ESt remains high. Finally,
after a short delay to allow the output latch to settle,
the delayed steering output flag goes high, signalling
that a received tone pair has been registered. The
status of the delayed steering flag can be monitored
by checking the appropriate bit in the status register.
If Interrupt mode has been selected, the IRQ/CP pin
will pull low when the delayed steering flag is
active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
C1
C2
R1
R2
R3
R4
R5
IN+
IN-
GS
V
Ref
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2
R1 = R4
R3 = (R2R5)/(R2 + R5)
FOR UNITY
R5=R1
INPUT IMPEDANCE
(Z
IN
diff) = 2
R1
2
+ (1/
C)
2
MT88L85
VOLTAGE GAIN
(A
V
diff) = R5/R1
MT88L85
4-75
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
t
REC
t
DPmax
+ t
GTPmax
- t
DAmin
t
REC
t
DPmin
+ t
GTPmin
- t
DAmax
t
ID
t
DAmax
+ t
GTAmax
- t
DPmin
t
DO
t
DAmin
+ t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1
F is recommended for most
Figure 6 - Guard Time Adjustment
V
DD
V
DD
St/GT
ESt
C1
Vc
R1
MT88L85
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
V
DD
St/GT
ESt
V
DD
St/GT
ESt
C1
R1
R2
C1
R1
R2
t
GTA
= (R1C1) In (V
DD
/V
TSt
)
t
GTP
= (R
P
C1) In [V
DD
/ (V
DD
-V
TSt
)]
R
P
= (R1R2) / (R1 + R2)
t
GTA
= (R
p
C1) In (V
DD
/V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
R
P
= (R1R2) / (R1 + R2)
b) decreasing
t
GTA
; (
t
GTP
>
t
GTA
)
a) decreasing
t
GTP
; (
t
GTP
<
t
GTA
)
Figure 7 - Receiver Timing Diagram
V
in
ESt
St/GT
RX
0
-RX
3
b3
b2
Read
Status
Register
IRQ/CP
EVENTS
A
B
C
D
E
F
t
REC
t
REC
t
ID
t
DO
TONE #n
TONE
#n + 1
TONE
#n + 1
t
DP
t
DA
t
GTP
t
GTA
t
PStRX
t
PStb3
DECODED TONE # (n-1)
# n
# (n + 1)
V
TSt
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