4-29
Features
D3/D4 or ESF framing and SLC-96 compatible
2 frame elastic buffer with 32
sec jitter buffer
Insertion and detection of A, B,C,D bits.
Signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow alarm and blue alarm signal capabilities
Bipolar violation count, F
T
error count, CRC
error count
Selectable
robbed bit signalling
Frame and superframe sync. signals, Tx and Rx
AMI encoding and decoding
Per channel, overall, and remote loop around
Digital phase detector between T1 line & ST-
BUS
One uncommitted scan point and drive point
Pin compatible with MT8977 and MT8979
ST-BUS compatible
Applications
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
Description
The MT8976 is Zarlink's second generation T1
interface solution. The MT8976 meets the Extended
Super Frame format (ESF), the current D3/D4 format
and is compatible with SLC-96 systems.
The MT8976 interfaces to DS1 1.544 Mbit/sec digital
trunk.
Figure 1 - Functional Block Diagram
TxSF
C2i
F0i
RxSF
DSTo
DSTi
CSTi0
CSTi1
CSTo
XCtl
XSt
ST-BUS
Timing
Data
Interface
Serial
Control
Interface
Control Logic
2 Frame
Elastic Buffer
with Slip
Control
2048-1544
Converter
ABCD
Signalling RAM
DS1
Link
Phase
Detector
DS1
Counter
Remote &
Digital
Loopbacks
C1.5i
RxFDLClk
RxFDL
RxA
RxB
TxA
TxB
TxFDLClk
TxFDL
RxD
E1.5i
E8Ko
V
SS
V
DD
Circuitry
Interface
Ordering Information
MT8976AE
28 Pin Plastic DIP
MT8976AP
44 Pin PLCC
-40
C to 85
C
ISSUE 11
October 1997
MT8976
T1/ESF Framer Circuit
ISO-CMOS ST-BUS
FAMILY
S
FAMILY
MT8976
ISO-CMOS
4-30
Figure 2 - Pin Connections
.
Pin Description
Pin #
Name
Description
DIP
PLCC
1
2
TxA
Transmit A Output
. Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
2
3
TxB
Transmit B Output.
Unipolar output that can be used in conjunction with TxA and
external line driver circuitry to generate the bipolar DS1 signal.
3
5
DSTo
Data ST-BUS Output.
A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
4
4
NC
No Connection.
5
9
RxA
Receive A Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxB,
detects bipolar violations in the received signal.
6
10
RxB
Receive B Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxA,
detects bipolar violations in the received signal.
7
11
RxD
Receive Data Input.
Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
8
13
CSTi1
Control ST-BUS Input #1.
A 2048 kbit/s serial control stream which carries 24 per-
channel control words.
9
14
TxFDL
Transmit Facility Data Link (Input).
A 4 kHz serial input stream that is multiplexed
into the FDL position in the ESF mode, or the F
s
pattern when in SLC-96 mode. It is
clocked in on the rising edge of TxFDLClk.
10
16
TxFDLClk
Transmit Facility Data Link Clock (Output).
A 4 kHz clock used to clock in the FDL
data.
11
NC
No connection.
VSS
DSTo
TxB
NC
TxA
IC
NC
F0i
NC
E1.5i
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
VSS
CSTi0
E8Ko
NC
VSS
XSt
NC
CSTo
RxFDLClk
DSTi
XCtl
VDD
28 PIN PDIP
TxA
TxB
DSTo
NC
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
NC
CSTi0
E8Ko
VSS
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
1
6 5 4 3 2
44 43 42 41 40
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
23
18 19 20 21 22
24 25 26 27 28
17
29
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
ISO-CMOS
MT8976
4-31
12
19
CSTi0
Control ST-BUS Input #0.
A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
13
20
E8Ko
Extracted 8 kHz Output.
The E1.5i clock is internally divided by 193 to produce an 8
kHz clock which is aligned with the received DS1 frame and output at this pin. The 8
kHz signal is derived from C1.5 in Digital Loopback mode.
14
6,
18,
22
V
SS
System Ground
.
15
23
XCtl
External Control (Output).
This is an uncommitted external output pin which is set
or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated
once per frame.
16
24
XSt
External Status (Schmitt Trigger Input).
The state of this pin is sampled once per
frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.
17
26
CSTo
Control ST-BUS Output.
This is a 2048 kbit/s serial control stream which provides
the 24 per-channel status words, and two master status words.
18
27
RxFDLClk
Receive Facility Data Link Clock (Output).
A 4 kHz clock signal used to clock out
FDL information. The data is clocked out on the rising edge of RxFDLClk.
19
28
DSTi
Data ST-BUS Input.
This pin accepts a 2048 kbit/s serial stream which contains the
24 PCM or data channels to be transmitted on the T1 trunk.
20
29
RxFDL
Received Facility Data Link (Output).
A 4 kHz serial output stream that is
demultiplexed from the FDL in ESF mode, or the received F
S
bit pattern in SLC-96
mode. It is clocked out on the rising edge of RxFDLClk.
21
34
C2i
2.048 MHz Clock Input.
This is the master clock used for clocking serial data into
DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.
22
37
TxSF
Transmit Superframe Pulse Input.
A low going pulse applied at this pin will make
the next transmit frame the first frame of a superframe. The device will free run if this
pin is held high.
23
38
RxSF
Received Superframe Pulse Output.
A pulse output on this pin designates that the
next frame of data on the ST-BUS is from frame 1 of the received superframe. The
period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are
output only when the device is synchronized to the received DS1 signal.
24
39
C1.5i
1.544 MHz Clock Input
. This is the DS1 transmit clock and is used to output data on
TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising
edge of C1.5i.
25
40
E1.5i
1.544 MHz Extracted Clock (Input).
This clock which is extracted from the received
data is used to clock in data at RxA, RxB and RxD . The falling edge of the clock is
nominally aligned with the center of the received bit on RxD, RxA and RxB.
26
42
F0i
Frame Pulse Input.
This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
27
44
IC
Internal Connection.
Tied to V
SS
for normal operation.
28
1
V
DD
Positive Power Supply Input.
+5V
5%.
Pin Description (Continued)
Pin #
Name
Description
DIP
PLCC
MT8976
ISO-CMOS
4-32
Functional Timing Diagrams
Figure 3 - ST-BUS Timing
Figure 4 - DS1 Receive Timing
Figure 5 - DS1 Transmit Timing
C2i
DSTi
DSTo
CSTi0/CSTi1
CSTo
7
6
5
4
3
2
1
0
3
4
5
6
7
2
1
0
125
Sec
7
7
E1.5i
INT DATA
DS1 AMI
LINE SIGNAL
RxA
RxB
RxD
E8Ko
1
1
0
0
1
1
0
1
125
Sec
C1.5i
INT DATA
TxA
TxB
DS1 AMI
LINE SIGNAL
ISO-CMOS
MT8976
4-33
ST
-B
US CHANNEL
VERSUS DS1 CHANNEL
TRANSMITTED
ST
-B
US CHANNEL
VERSUS DS1 CHANNEL RECEIVED
PCCW =PER CHANNEL CONTR
OL
W
ORD
MCW1/2 =MASTER CONTR
OL
W
ORD 1/2
ST
-B
US CHANNEL
VERSUS DS1 CHANNEL CONTR
OLLED
PCCW =PER CHANNEL CONTR
OL
W
ORD
ST
-B
US CHANNEL
VERSUS DS1 CHANNEL CONTR
OLLED
PCSW =PER CHANNEL ST
A
TUS
W
ORD
PSW =PHASE ST
A
TUS
W
ORD
MSW =MASTER ST
A
TUS
W
ORD
ST
-B
US
VERSUS DS1 CHANNEL ST
A
TUS
Figure 6 - ST
-B
US Channel Allocations
X=UNUSED CHANNEL
DSTi
0
X
1234
X
5678
X
9
1
01
11
2
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
29
30
31
DS1
1
2
3
4
5
6
7
8
9
1
01
11
2
1
31
41
5
1
61
71
8
1
92
02
1
2
22
32
4
DST
o
0
X
1234
X
5678
X
91
0
1
1
1
2
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
29
30
31
DS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CSTi0
0
PC
CW
1
1
PC
CW
1
2
PC
CW
1
3
X
4
PC
CW
1
5
PC
CW
1
6
PC
CW
1
7
X
8
PC
CW
1
9
PC
CW
1
10
PC
CW
1
11
X
12
PC
CW
1
13
PC
CW
1
14
PC
CW
1
15
MC
W1
16
PC
CW
1
17
PC
CW
1
18
PC
CW
1
19
X
20
PC
CW
1
21
PC
CW
1
22
PC
CW
1
23
X
24
PC
CW
1
25
PC
CW
1
26
PC
CW
1
27
X
28
PC
CW
1
29
PC
CW
1
30
PC
CW
1
31
MC
W2
DS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CSTi1
0
PC
CW
2
1
PC
CW
2
2
PC
CW
2
3
X
4
PC
CW
2
5
PC
CW
2
6
PC
CW
2
7
X
8
PC
CW
2
9
PC
CW
2
10
PC
CW
2
11
X
12
PC
CW
2
13
PC
CW
2
14
PC
CW
2
15
X
16
PC
CW
2
17
PC
CW
2
18
PC
CW
2
19
X
20
PC
CW
2
21
PC
CW
2
22
PC
CW
2
23
X
24
PC
CW
2
25
PC
CW
2
26
PC
CW
2
27
X
28
PC
CW
2
29
PC
CW
2
30
PC
CW
2
31
X
DS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CST
o
0
PCS
W
1
PCS
W
2
PCS
W
3
PS
W
4
PCS
W
5
PCS
W
6
PCS
W
7
X
8
PCS
W
9
PCS
W
10
PCS
W
11
X
12
PCS
W
13
PCS
W
14
PCS
W
15
MS
W1
16
PCS
W
17
PCS
W
18
PCS
W
19
X
20
PCS
W
21
PCS
W
22
PCS
W
23
X
24
PCS
W
25
PCS
W
26
PCS
W
27
X
28
PCS
W
29
PCS
W
30
PCS
W
31
MS
W2
DS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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