ChipFind - документация

Электронный компонент: MT8979AP

Скачать:  PDF   ZIP

Document Outline

1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Single chip primary rate 2048 kbit/s CEPT
transceiver with CRC-4 option
Meets CCITT Recommendation G.704
Selectable HDB3 or AMI line code
Tx and Rx frame and multiframe synchronization
signals
Two frame elastic buffer with 32
sec jitter buffer
Frame alignment and CRC error counters
Insertion and detection of A, B, C, D signalling
bits with optional debounce
On-chip attenuation ROM with option for ADI
codecs
Per channel, overall and remote loop around
ST-BUS compatible
Applications
Primary rate ISDN network nodes
Multiplexing equipment
Private network: PBX to PBX links
High speed computer to computer links
Description
The MT8979 is a single chip CEPT digital trunk
transceiver that meets the requirements of CCITT
Recommendation G.704 for digital multiplex
equipment.
The MT8979 is fabricated in Zarlink's low power ISO-
CMOS technology.
February 2005
Ordering Information
MT8979AE
28 Pin PDIP
Tubes
MT8979AP
44 Pin PLCC
Tubes
MT8979APR
44 Pin PLCC
Tape & Reel
MT8979AE1
28 Pin PDIP*
Tubes
MT8979AP1
44 Pin PLCC*
Tubes
MT8979APR1
44 Pin PLCC*
Tape & Reel
*Pb Free Matte Tin
-40
C to +85C
ISO-CMOS ST-BUS
TM
Family
MT8979
CEPT PCM 30/CRC-4 Frame & Interface
Data Sheet
Figure 1 - Functional Block Diagram
V
DD
RxD
RxA
RxB
TxA
TxB
E2i
E8Ko
V
SS
CEPT
Link
Interface
Digital
Attenuator
ROM
ST-BUS
Timing
Circuitry
PCM/Data
Interface
Serial
Control
Interface
ABCD Bit RAM
Control Logic
Phase
Detector
CEPT
Counter
TxMF
C2i
F0i
RxMF
DSTi
DSTo
ADI
CSTi0
CSTi1
CSTo
XCtl
XSt
Remote
&
Digital
Loop-
backs
2 Frame
Elastic Buffer
with Slip
Control
MT8979
Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
DIP PLCC
1
2
TxA
Transmit A (Output): A split phase unipolar signal suitable for use with TxB and an
external line driver and transformer to construct the bipolar line signal.
2
3
TxB
Transmit B (Output:) A split phase unipolar signal suitable for use with TxA and an
external line driver and transformer to construct the bipolar line signal.
3
5
DSTo
Data ST-BUS (Output): A 2048 kbit/s serial output stream which contains the 30 PCM or
data channels received from the CEPT line.
4
4
NC
No Connection.
5
9
RxA
Receive A (Input): Received split phase unipolar signal decoded from a bipolar line
receiver.
6
10
RxB
Receive B (Input): Received split phase unipolar signal decoded from a bipolar line
receiver.
7
11
RxD
Received Data (Input): Input of the unipolar data generated from the line receiver. This
data may be NRZ or RZ.
8
13
CSTi1
Control ST-BUS Input #1: A 2048 kbit/s stream that contains channel associated
signalling, frame alignment and diagnostic functions.
9
NC
No Connection.
10
NC
No Connection.
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
28 PIN PDIP
TxA
TxB
NC
RxA
RxB
RxD
CSTi1
NC
NC
ADI
CSTi0
E8Ko
VSS
VDD
IC
F0i
E2i
NC
RxMF
TxMF
C2i
NC
DSTi
NC
CSTo
XSt
XCtl
DSTo
VSS
DSTo
TxB
TxA
IC
NC
F0
i
NC
E2i
NC
RxMF
TxMF
NC
NC
C2i
NC
NC
NC
NC
NC
NC
NC
RxA
RxB
RxD
NC
CSTi1
NC
NC
NC
ADI
VS
S
CST
i
0
E8Ko
NC
VS
S
XSt
NC
CST
o
NC
DSTi
XCt
l
VD
D
1
6 5 4 3 2
44 43 42 41 40
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
23
18 19 20 21 22
24 25 26 27 28
17
29
NC
MT8979
Data Sheet
3
Zarlink Semiconductor Inc.
11
17
ADI
Alternate Digit Inversion (Input): If this input is high, the CEPT timeslots which are
specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low it
disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs to
be used on DSTi and DSTo.
12
19
CSTi0
Control ST-BUS Input #0: A 2048 kbit/s stream that contains 30 per channel control
words and two Master Control Words.
13
20
E8Ko
Extracted 8 kHz Clock (Output): An 8 kHz output generated by dividing the extracted
2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal
can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only
valid when device achieves synchronization (goes low during a loss of signal or a loss
of basic frame synchronization condition).
E8Ko goes high impedance when 8 kHzSEL = 0 in MCW2.
15
23
XCtl
External Control (Output): An uncommitted external output pin which is set or reset
via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per
frame.
16
24
XSt
External Status: The state of this pin is sampled once per frame and the status is
reported in bit 1 of the Master Status Word 1 on CSTo.
17
26
CSTo
Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16
signalling words, two Master Status Words, Phase Status Word and CRC Error Count.
18
NC
No Connection.
19
28
DSTi
Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 30
PCM or data channels to be transmitted on the CEPT trunk.
20
NC
No Connection.
21
34
C2i
2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the
chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on
the rising edge. The falling edge of C2i is also used to clock out data on the CEPT
transmit link.
22
37
TxMF
Transmit Multiframe Boundary (Input): This input can be used to set the channel
associated and CRC transmitted multiframe boundary (clear the frame counters). The
device will generate its own multiframe if this pin is held high.
23
38
RxMF
Received Multiframe Boundary (Output): An output pulse delimiting the received
Multiframe boundary. (This multiframe is not related to the received CRC multiframe.)
The next frame output on the data stream (DSTo) is received as frame 0 on the CEPT
link.
24
NC
No Connection.
25
40
E2i
Extracted 2048 kHz Clock (Input): The falling edge of this 2048 kHz clock is used to
latch the received data (RxD). This clock input must be derived from the CEPT
received data and must have its falling edge aligned with the center of the received bit
(RxD).
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
MT8979
Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
The MT8979 is a CEPT trunk digital link interface conforming to CCITT Recommendation G.704 for PCM 30 and
I.431 for ISDN. It includes features such as: insertion and detection of synchronization patterns, optional cyclical
redundancy check and far end error performance reporting, HDB3 decoding and optional coding, channel
associated or common channel signalling, programmable digital attenuation and a two frame received elastic
buffer. The MT8979 can also monitor several conditions on the CEPT digital trunk, which include, frame and
multiframe synchronization, received all 1's alarms, data slips as well as framing and CRC errors, both near and
far end.
The system interface to the MT8979 is a TDM bus structure that operates at 2048 kbit/s known as the ST-BUS.
This serial stream is divided into 125
s frames that are made up of 32 x 8 bit channels.
The line interface to the MT8979 consists of split phase unipolar inputs and outputs which are supplied from/to a
bipolar line receiver/driver, respectively.
Figure 3 - CEPT Link Frame & Multiframe Format
CEPT Interface
The CEPT frame format consists of 32, 8 bit timeslots. Of the 32 timeslots in a frame, 30 are defined as
information channels, timeslots 1-15 and 17-31 which correspond to telephone channels 1-30. An additional
voice/data channel may be obtained by placing the device in common channel signalling mode. This allows use of
timeslot 16 for 64 kbit/s common channel signalling.
26
42
F0i
Frame Pulse Input: The ST-BUS frame synchronization signal which defines the
beginning of the 32 channel frame.
27
44
IC
Internal Connection: Tie to V
SS
(Ground) for normal operation.
28
1
V
DD
Positive Power Supply Input (+5 Volts).
14 6,8,
22
V
SS
Negative Power Supply Input (Ground).
Pin Description (continued)
Pin #
Name
Description
DIP PLCC
Frame
15
0
14
15
0
Timeslot
0
1
30
31
Most
Significant
Bit (First)
Least
Significant
Bit (Last)
Bit
1
2
3
4
5
6
7
8
Frame
Frame
Frame
Frame
Timeslot
Timeslot
Timeslot
Bit
Bit
Bit
Bit
Bit
Bit
Bit
2.0 ms
(8/2.048)
s
125
s
MT8979
Data Sheet
5
Zarlink Semiconductor Inc.
Synchronization is included within the CEPT bit stream in the form of a bit pattern inserted into timeslot 0. The
contents of timeslot 0 alternate between the frame alignment pattern and the non-frame alignment pattern as
described in Figure 4. Bit 1 of the frame alignment and non-frame alignment bytes have provisions for additional
protection against false synchronization or enhanced error monitoring. This is described in more detail in the
following section.
In order to accomplish multiframe synchronization, a 16 frame multiframe is defined by sending four zeros in the
high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 5). The CEPT format has four
signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frames
1 to 15. These timeslots are subdivided into two quartets (see Table 6).
Figure 4 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored.
Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15
Note 3 : Reserved for National use
.
Figure 5 - Allocation of Bits in Timeslot 16 of the CEPT Link
Cyclic Redundancy Check (CRC)
An optional cyclic redundancy check (CRC) has been incorporated within CEPT bit stream to provide additional
protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error
monitoring capability. The CRC process treats the binary string of ones and zeros contained in a submultiframe
(with CRC bits set to binary zero) as a single long binary number. This string of data is first multiplied by x
4
then
divided by the generating polynomial x
4
+x+1. This division process takes place at both the transmitter and receiver
end of the link. The remainder calculated at the receiver is compared to the one received with the data over the
link. If they are the same, it is of high probability that the previous submultiframe was received error free.
The CRC procedure is based on a 16 frame multiframe, which is divided into two 8 frame submultiframes (SMF).
The frames which contain the frame alignment pattern contain the CRC bits, C
1
to C
4
respectively, in the bit 1
position. The frames which contain the non-frame alignment pattern contain within the bit 1 position, a 6 bit CRC
multiframe alignment signal and two spare bits (in frames 13 and 15), which are used for CRC error performance
reporting (refer to Figure 6). During the CRC encoding procedure the CRC bit positions are initially set at zero. The
remainder of the calculation is stored and inserted into the respective CRC bits of the next SMF. The decoding
process repeats the multiplication division process and compares the remainder with the CRC bits received in the
next SMF.
Bit Number
1
2
3
4
5
6
7
8
Timeslot 0 containing the
frame alignment signal
Reserved for
International
use
(1)
0
0
1
1
0
1
1
Timeslot 0 containing the non-
frame alignment signal
Reserved for
International
use
(2)
1
Alarm indication to the
remote PCM multiplex
equipment
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
Timeslot 16 of frame 0
Timeslot 16 of frame 1
Timeslot 16 of frame 15
0000
XYXX
ABCD bits for
telephone
channel 1
(timeslot 1)
ABCD bits for
telephone
channel 16
(timeslot 17)
ABCD bits for
telephone
channel 15
(timeslot 15)
ABCD bits for
telephone
channel 30
(timeslot 31)