2-3
Features
3.3 volt supply
5V tolerant inputs and TTL compatible outputs.
256 x 256 channel non-blocking switch
Accepts serial streams at 2.048Mb/s
Per-channel three-state control
Patented per channel message mode
Non-multiplexed microprocessor interface
Mitel ST-BUS compatible
Low power consumption: typical 15mW
Pin compatible with the MT8980DP
Applications
Key telephone systems
PBX systems
Small and medium voice switching systems
Description
This VLSI CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or
Central Office. It provides simultaneous connections
for up to 256 64 kbit/s channels. Each of the eight
serial inputs and outputs consist of 32 64 kbit/s
channels multiplexed to form a 2048 kbit/s ST-BUS
stream. In addition, the MT89L80 provides
microprocessor read and write access to individual
ST-BUS channels.
Figure 1 - Functional Block Diagram
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
CS R/W A5/
A0
DTA D7/
D0
CSTo
C4i
F0i
V
DD
V
SS
**
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
DS
RESET
** for 48-pin SSOP only
DS5196
ISSUE 3
July 2002
MT89L80
Digital Switch
CMOS ST-BUS
TM
FAMILY
Ordering Information
MT89L80AP
44 Pin PLCC
MT89L80AN
48 Pin SSOP
-40
C to +85
C
Advance Information
MT89L80
Advance Information
2-4
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
44
PLCC
48
SSOP
2
2
DTA
Data Acknowledgment (5V Tolerant Three-state Output). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
3-5
3-5
STi0-2 ST-BUS Inputs 0 to 2 (5V-tolerant Inputs). Serial data input streams. These streams
have data rates of 2.048Mbit/s with 32 channels.
7-11
7-11
STi3-7 ST-BUS Inputs 3 to 7 (5V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048Mbit/s with 32channels.
12
12,36
V
DD
+3.3 Volt Power Supply.
13
RESET Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP
package.This active low input puts the device in its reset state. It clears the internal
counters and registers. All ST-BUS outputs are set to the high impedance state. In
normal operation. The RESET pin must be held low for a minimum of 100nsec to reset
the device. Internal pull-up.
13
14
F0i
Frame Pulse (5V-tolerant Input). This is the input for the frame synchronization
pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal
counter to reset on
the next negative transition of C4i.
14
15
C4i
4.096 MHz Clock (5V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate
falling edges of this clock.
15-17 16-18
A0-2
Address 0-2 / Input Streams 8-10 (5V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
1
6
5
4
3
2
4
4
4
3
4
2
4
1
4
0
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
2
3
1
8
1
9
2
0
2
1
2
2
2
4
2
5
2
6
2
7
2
8
17
29
STi3
STi4
STi5
STi6
STi7
V
DD
F0i
C4i
A0
A1
A2
STo3
STo4
STo5
STo6
STo7
V
SS
D0
D1
D2
D3
D4
N
C
S
T
i
1
D
T
A
O
D
E
S
T
o
1
N
C
N
C
A
4
D
S
C
S
D
6
N
C
A
3
A
5
R
/
W
D
7
D
5
44 PIN PLCC
S
T
i
2
S
T
i
0
C
S
T
o
S
T
o
0
S
T
o
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
48 PIN SSOP
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
V
SS
V
DD
D0
D1
D2
D3
D4
NC
D5
D6
DTA
STi0
STi1
STi2
NC
STi3
STi4
STi5
STi6
STi7
V
DD
RESET
F0i
C4i
A0
A1
A2
NC
A3
A4
48
CSTo
V
SS
21
27
D7
A5
22
26
CS
DS
23
25
V
SS
R/W
24
(JEDEC MO-118, 300mil Wide)
Advance Information
MT89L80
2-5
19-21 20-22
A3-5
Address 3-5 / Input Streams 11-13 (5V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
22
23
DS
Data Strobe (5V-tolerant Input). This is the input for the active high data strobe on the
microprocessor interface.
23
24
R/W
Read/Write (5V-tolerant Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
24
26
CS
Chip Select (5V-tolerant Input). This is the input for the active low chip select on the
microprocessor interface
25-27 27-29
D7-D5 Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor
interface.
29-33 31-35
D4-D0 Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor
interface.
34
1,
25,37
V
SS
Ground.
35-39 38-42
STo7-3 ST-BUS Outputs 7 to 3 (5V-Tolerant Three-state Outputs). These are the pins for the
eight 2048 kbit/s ST-BUS output streams.
41-43 44-46
STo2-0 ST-BUS Outputs 2to 0 (5V-Tolerant Three-state Outputs). These are the pins for the
eight 2048kbit/s ST-BUS output streams.
44
47
ODE
Output Drive Enable (5V-tolerant Input). If this input is held high, the STo0-STo7
output drivers function normally. If this input is low, the STo0-STo7 output drivers go
into their high impedance state.
NB: Even when ODE is high, channels on the STo0-
STo7 outputs can go high impedance under software control.
1
48
CSTo
Control ST-BUS Output (5V-Tolerant Output). Each frame of 256 bits on this ST-BUS
output contains the values of bit 1 in the 256 locations of the Connection Memory High.
6, 18,
28, 40
6, 19,
30, 43
NC
No Connection.
Pin Description (continued)
Pin #
Name
Description
44
PLCC
48
SSOP
MT89L80
Advance Information
2-6
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.
In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus). This bus
architecture can be used both in software-controlled
digital voice and data switching, and for
interprocessor communications. The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
s wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT89L80 chip.
The MT89L80 can switch data from channels on ST-
BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT89L80 looks like a
memory peripheral. The microprocessor can write to
the MT89L80 to establish switched connections
between input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-
BUS channels. By reading from the MT89L80, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT89L80 allows systems to
use distributed processing and to switch voice or
data in an ST-BUS architecture.
Hardware Description
Serial data at 2048 kbit/s is received at the eight ST-
BUS inputs (STi0 to STi7), and serial data is
transmitted at the eight ST-BUS outputs (STo0 to
STo7). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL's
MT8964).
This serial input word is converted into parallel data
and stored in the 256 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams.
These locations can be read by the microprocessor
which controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS,
DTA, R/W and DS. There are two parts to any
address in the Data Memory or Connection Memory.
Figure 3- Address Memory Map
A5
A4
A3
A2
A1
A0
Hex Address
Location
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
00 - 1F
20
21
3F
Control Register *
Channel 0
Channel 1
Channel 31
* Writing to the Control Register is the only fast transaction.
Memory and stream are specified by the contents of the Control Register.
Advance Information
MT89L80
2-7
The higher order bits come from the Control
Register, which may be written to or read from via
the Control Interface. The lower order bits come
from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory and
writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT89L80s to be constructed. It also controls the
CSTo pin.
All ST-BUS timing is derived from the two
signals C4i and F0i.
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1, regardless
of the actual values.
Figure 4 - Control Register Bits
Bit
Name
Description
7
Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
6
Message
Mode
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
5
(unused)
4-3
Memory
Select Bits
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0
Stream
Address Bits
The number expressed in binary notation on these bits refers to the input or output ST-
BUS stream which corresponds to the subsection of memory made accessible for
subsequent operations.
7
6
5
4
3
2
1
0
Mode
Control
Bits
(unused)
Memory
Select
Bits
Stream
Address
Bits
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