Document Outline

• Features
  • IMA
  • TC and UNI
  • Standards Compliant
  • General
• Applications
• Preamble
• Description
  • Figure 1 - MT90222/3/4 Block Diagram (with Built-in IMA functions for up to 8 IMA Groups over 4/8/16 links)
• Pin Diagram - MT90222
  • Figure 2 - MT90222 Pinout (Bottom View)
• Pin Diagram - MT90223
  • Figure 3 - MT90223 Pinout (Bottom View)
• Pin Diagram - MT90224
  • Figure 4 - MT90224 Pinout (Bottom View)
  • MT90222 Pin Description
  • MT90223 Pin Description
  • MT90224 Pin Description
• 1.0 Device Architecture
  • 1.1 Software Functions
    • 1.1.1 Link State Machines
    • 1.1.2 IMA Group State Machines
    • 1.1.3 Link Addition, Removal or Restoration
    • 1.1.4 Interrupts
    • 1.1.5 Signalling and Rate Adjustment
    • 1.1.6 Performance Monitoring
  • 1.2 Hardware Functions
• 2.0 The ATM Transmit Path
  • 2.1 Cell In Control
    • Figure 5 - MT90224 Functional Block Diagram -Transmitter in IMA Mode
  • 2.2 The ATM Transmission Convergence
    • 2.2.1 TX Cell RAM and TX FIFO Length
  • 2.3 Parallel to Serial TDM Interface
  • 2.4 ATM Transmit Path in IMA Mode
    • 2.4.1 IMA Frame Length (M)
    • 2.4.2 Position of the ICP Cell in the IMA Frame
    • 2.4.3 Transmit Clock Operation
    • 2.4.4 Stuff Cell Rate
    • 2.4.5 IMA Data Cell Rate
      • Table 1 - IDCR Integration Register Value
    • 2.4.6 IMA Controller (RoundRobin Scheduler)
      • Table 2 - ICP Cell Description
    • 2.4.7 ICP Cell Generator
    • 2.4.8 IMA Frame Programmable Interrupt
    • 2.4.9 Filler Cell Definition
    • 2.4.10 TX IMA Group Start-Up
    • 2.4.11 TX Link Addition
    • 2.4.12 TX Link Deletion
      • Figure 6 - Functional Block Diagram of the Transmitter in TC Mode (For Link[N], 0 � N � 15)
  • 2.5 ATM Transmit Path in TC Mode
• 3.0 The ATM Receive Path
  • 3.1 Cell Delineation Function
    • Figure 7 - Cell Delineation State Diagram
    • Table 3 - Cell Acquisition Time
    • Figure 8 - SYNC State Block Diagram
    • 3.1.1 Cell Delineation with Sync signal
    • 3.1.2 Cell Delineation without Sync signal
    • 3.1.3 De-Scrambling and ATM Cell Filtering
      • Figure 9 - MT90224 Receiver Circuit in IMA Mode
  • 3.2 ATM Receive Path in IMA Mode
    • 3.2.1 ICP Cell Processor
    • 3.2.2 IMA Frame Synchronization
    • 3.2.3 Link Information
    • 3.2.4 RX OAM Label
    • 3.2.5 Out of IMA Frame (OIF) Condition
    • 3.2.6 Loss of IMA Frame (LIF) Synchronization
    • 3.2.7 Filler Cell Handling
    • 3.2.8 Stuff Cell Handling
    • 3.2.9 Received ICP Cell Buffer
    • 3.2.10 Rate Recovery
    • 3.2.11 Cell Buffer/RAM Controller
      • Table 4 - Differential Delay for Various Memory Configuration
    • 3.2.12 Cell Sequence Recovery
    • 3.2.13 Delay Between Links
      • Table 5 - Conversion Factors Time/Cell (msec)
      • 3.2.13.1 RX Recombiner Delay Value
      • 3.2.13.2 RX Maximum Operational Delay Value
      • 3.2.13.3 Link Out of Delay Synchronization (LODS)
      • 3.2.13.4 Negative Delay Values
      • 3.2.13.5 Measured Delay Between Links
      • 3.2.13.6 Incrementing/Decrementing the Recombiner Delay
    • 3.2.14 RX IMA Group Start-Up
    • 3.2.15 Link Addition
    • 3.2.16 Link Deletion
    • 3.2.17 Disabling an IMA Group
  • 3.3 The ATM Receive Path in TC Mode
    • Figure 10 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports)
• 4.0 Description of the TDM Interface
  • 4.1 Single Mode
    • 4.1.1 Single Mode - Generic 1.544 MHz
      • Figure 11 - Single Mode - Generic 1.544 MHz
    • 4.1.2 Single mode - Generic 2.048 MHz
      • Figure 12 - Single Mode - Generic 2.048 MHz
    • 4.1.3 Single Mode -ST-BUS
      • Figure 13 - Single Mode - ST-BUS
  • 4.2 Wire-OR Mode
    • 4.2.1 Wire-OR Mode - 2 Link Grouping
    • 4.2.2 Wire-OR Mode - 4 Link Grouping
  • 4.3 Multiplex Mode
    • 4.3.1 Multiplex Mode - 2 Link Multiplexing
    • 4.3.2 Multiplex Mode - 4 Link Multiplexing
  • 4.4 Non-Framed Mode
    • 4.4.1 Non-Framed Mode - 2.5 Mbps
    • 4.4.2 Non-Framed Mode - 5.0 Mbps
    • 4.4.3 Non-Framed Mode - 10.0 Mbps
  • 4.5 Clock formats
  • 4.6 TDM Loopback Mode
  • 4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters
  • 4.8 Clocking Options
    • Figure 14 - TXCK and TXSYNC Output Pin Source Options
    • 4.8.1 Verification of the RXSYNC Period
    • 4.8.2 Verification of the TXSYNC Period
    • 4.8.3 Primary and Secondary Reference Signals
    • 4.8.4 Verification of Clock Activity
    • 4.8.5 Clock Selection
• 5.0 UTOPIA Interface Operation
  • 5.1 ATM Input Port
  • 5.2 ATM Output Port
  • 5.3 UTOPIA Operation with a Single PHY
  • 5.4 UTOPIA Operation with Multiple PHY
  • 5.5 UTOPIA Operation in TC Mode
  • 5.6 UTOPIA Operation in IMA Mode
  • 5.7 UTOPIA Loopback
  • 5.8 Examples of UTOPIA Operations Modes
    • Figure 15 - ATM Interface to MT90224
    • Figure 16 - ATM Interface to Multiple MT90224s
    • Figure 17 - ATM Mixed-Mode Interface to One MT90224
• 6.0 Support Blocks
  • 6.1 Counter Block
    • 6.1.1 UTOPIA Input I/F counters
    • 6.1.2 Transmit TDM I/F Counters
    • 6.1.3 Receive TDM I/F Counters
    • 6.1.4 Access to the Counters
    • 6.1.5 Latching counter mode
      • Figure 18 - IRQ Register Hierarchy
  • 6.2 Interrupt Block
    • 6.2.1 IRQ Master Status and IRQ Master Enable Registers
    • 6.2.2 IRQ Link Status and IRQ Link Enable Registers
      • 6.2.2.1 Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers
    • 6.2.3 IRQ Link TC Overflow Status Registers
    • 6.2.4 IRQ IMA Group Overflow Status and Enable Registers
    • 6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers
  • 6.3 Microprocessor Interface Block
    • 6.3.1 Access to the Various Registers
    • 6.3.2 Direct Access
    • 6.3.3 Indirect Access
    • 6.3.4 Clearing of Status Bits
      • 6.3.4.1 Toggle Bit
  • 6.4 Cell Preprocessor Block
    • Figure 19 - Processed RX Cell FIFO Word Format
  • 6.5 TDM Ring Block
  • 6.6 SRAM Decoding for MT90222/223
• 7.0 Register Descriptions:
  • 7.1 Register Summary
    • Table 6 - Register Summary
  • 7.2 Detailed Register Description
    • Table 7 - UTOPIA Output Link Address Registers
    • Table 8 - UTOPIA Output Group Address Registers
    • Table 9 - UTOPIA Output Link PHY Enable Registers
    • Table 10 - UTOPIA Output Group PHY Enable Register
    • Table 11 - UTOPIA Output User Defined Byte
    • Table 12 - UTOPIA Input Link Address Registers
    • Table 13 - UTOPIA Input Group Address Registers
    • Table 14 - UTOPIA Input Link PHY Enable Register
    • Table 15 - UTOPIA Input Group PHY Enable Register
    • Table 16 - UTOPIA Input Control Register
    • Table 17 - UTOPIA Input Parity Error Register
    • Table 18 - TX Cell RAM Control Register
    • Table 19 - TX ICP Cell Handler Register
    • Table 20 - TX IMA Frame Indication Register
    • Table 21 - TX ICP Cell Interrupt Enable Register
    • Table 22 - TX IMA Frame Interrupt Enable Register
    • Table 23 - TX Link FIFO Length Definition Register
    • Table 24 - TX IMA Group FIFO Length Definition Register
    • Table 25 - TX FIFO Length Status Register
    • Table 26 - RX Link Control Registers
    • Table 27 - Loss of Delineation Register
    • Table 28 - Cell Delineation Register
    • Table 29 - IMA Frame Delineation Register
    • Table 30 - User Defined RX OAM Label Register
    • Table 31 - RX OIF Status Register
    • Table 32 - RX OIF Counter Clear Command Register
    • Table 33 - RX Wrong Filler Status Register
    • Table 34 - RX Load Values/Link Select Register
    • Table 35 - RX OAM Label Register
    • Table 36 - RX Link IMA ID Registers
    • Table 37 - RX ICP Cell Offset Register
    • Table 38 - RX Link Frame Sequence Number Register
    • Table 39 - RX Link SCCI Sequence Number Register
    • Table 40 - RX Link OIF Counter Value Register
    • Table 41 - RX Link ID Number Register
    • Table 42 - RX State Register
    • Table 43 - IMA Frame State Machine Status Register
    • Table 44 - Cell Delineation Status Register
    • Table 45 - RX Cell Type RAM Register 1
    • Table 46 - RX Cell Type RAM Register 2
    • Table 47 - RX Cell Process Enable Register
    • Table 48 - RX Cell Buffer Increment Read Pointer Register
    • Table 49 - RX Cell Level FIFO Status Register
    • Table 50 - Processed RX Cell Link FIFO Status Register
    • Table 51 - ICP Cell RAM DEBUG Register
    • Table 52 - Processed RX Cell link FIFO Register
    • Table 53 - Ring Tx Control Register
    • Table 54 - Ring Tx Link Registers
    • Table 55 - Ring Rx Link Registers
    • Table 56 - RX Recombiner Registers
    • Table 57 - RX Reference Link Control Registers
    • Table 58 - RX IDCR Integration Registers
    • Table 59 - RX External SRAM Access Control Register
    • Table 60 - Increment Delay Control Register
    • Table 61 - Decrement Delay Control Register
    • Table 62 - RX Recombiner Delay Control Registers
    • Table 63 - RX External SRAM Read/Write Data
    • Table 64 - RX Delay Register
    • Table 65 - RX Delay Link Number Register
    • Table 66 - RX Guardband/Delta Delay Register
    • Table 67 - RX External SRAM Read/Write Address
    • Table 68 - RX External SRAM Read/Write Address 1
    • Table 69 - SRAM Control Register
    • Table 70 - RX Maximum Operational Delay Register
    • Table 71 - RX Delay Select Register
    • Table 72 - Enable Recombiner Status Register
    • Table 73 - TX Group Control Mode Registers
    • Table 74 - TX ICP Cell Offset Registers
    • Table 75 - TX Link Control Registers
    • Table 76 - TX IMA Control Registers
    • Table 77 - TX Add Link Control Register
    • Table 78 - TX Link ID Registers
    • Table 79 - TX Link Active Status Register
    • Table 80 - TX IMA Mode Status Register
    • Table 81 - UTOPIA Input Cell Counter Groups Register
    • Table 82 - UTOPIA Input Cell Counter Links Register
    • Table 83 - TX IDCR Integration Registers
    • Table 84 - IRQ IMA Group Overflow Enable Register
    • Table 85 - RX UTOPIA IMA Group FIFO Overflow IRQ Enable Register
    • Table 86 - General Status Register
    • Table 87 - Counter Transfer Command Register
    • Table 88 - IRQ Link TC Overflow Status Registers
    • Table 89 - IRQ IMA Overflow Status Registers
    • Table 90 - Counter Upper Byte
    • Table 91 - Counter Bytes 2 and 1 Register
    • Table 92 - Select Counter Register
    • Table 93 - IRQ Master Enable Register
    • Table 94 - IRQ Link TC Overflow Enable Register
    • Table 95 - IRQ Link Status Registers
    • Table 96 - IRQ Link Enable Registers
    • Table 97 - IRQ Master Status Register
    • Table 98 - IRQ IMA Group Overflow Status Register
    • Table 99 - TX IMA ICP Cell Registers
    • Table 100 - TDM TX Link Control Register
    • Table 101 - TDM TX Mapping (timeslots 15:0) Register
    • Table 102 - TDM TX Mapping (timeslots 31:16) Register
    • Table 103 - TXCK Status Register
    • Table 104 - RXCK Status Register
    • Table 105 - REFCK Status Register
    • Table 106 - TX Sync. Status Register
    • Table 107 - PLL Reference Control Register
    • Table 108 - TDM RX Link Control Register
    • Table 109 - TDM RX Mapping (timeslots 15:0) Register
    • Table 110 - TDM RX Mapping (timeslots 31:16) Register
    • Table 111 - RX Sync. Status Register
    • Table 112 - RX Automatic ATM Synchronization Register
    • Table 113 - RX IMA ICP Cell
• 8.0 Application Notes
  • 8.1 Connecting the MT90222/3/4 to Various T1/E1/J1 Framers
    • Figure 20 - Synchronous ST-BUS Mode (Using ST-BUS/2.048 Mbps Backplane Compatible Framers)
    • Figure 21 - CTC Mode (Using MT9076B T1/E1/J1 Single Chip Transceivers)
    • Figure 22 - ITC Mode with ST-BUS (Using Zarlink MT9076B T1/E1/J1 Single Chip Transceivers)
    • Figure 23 - ITC Mode with Generic TDM Interface (Using MT9076B T1/E1/J1 Framer/LIU)
    • Figure 24 - Asynchronous Operations (Using Two MT9072 Octal T1/E1/J1 Framers)
  • 8.2 Connecting the MT90222/3/4 to SHDSL Framers
    • 8.2.1 Modes of Operation
      • Figure 25 - Interface to SHDSL Device
• 9.0 AC/DC Characteristics
  • Absolute Maximum Conditions*
  • Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
  • DC Electrical Characteristics* - Voltages are with respect to ground (Vss) unless otherwise stated.
  • AC Electrical Characteristics - Utopia Interface Transmit Timing (� 50 MHz)1
  • - Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
  • AC Electrical Characteristics - UTOPIA Interface Receive Timing (� 50 MHz)1
  • - Multi-PHY operation with up to 4 input loads of 10 pF each (40 pF total).
  • AC Electrical Characteristics - Utopia Interface Transmit Timing (� 25 MHz)
  • - Multi-PHY operation with up to 8 input loads of 10 pF each (80 pF total).
  • AC Electrical Characteristics - UTOPIA Interface Receive Timing (� 25 MHz)
  • - Multi-PHY operation with up to 8 input loads of 10 pF each (80 pF total).
  • Figure 26 - Setup and Hold Time Definition
  • Figure 27 - Tri-State Timing
  • Figure 28 - Output Delay Timing
  • AC Electrical Characteristics - External Memory Interface Timing - Read Access
  • Figure 29 - External Memory Interface Timing - Read Cycle
  • AC Electrical Characteristics - External Memory Interface Timing - Write Access
  • Figure 30 - External Memory Interface Timing - Write Cycle
  • 9.1 CPU Interface Timing
    • AC Electrical Characteristics - CPU Interface Motorola Timing - Read Cycle
    • Figure 31 - CPU Interface Motorola Timing - Read Access
    • AC Electrical Characteristics - CPU Interface Intel Timing - Read Cycle
    • Figure 32 - CPU Interface Intel Timing - Read Access
    • AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
    • Figure 33 - CPU Interface Motorola Timing - Write Access
    • AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle
    • Figure 34 - CPU Interface Intel Timing - Write Access
    • AC Electrical Characteristics - Serial Streams Frame Pulse and CLK
    • AC Electrical Characteristics - Serial Streams for ST-BUS and Generic Interface
    • Figure 35 - ST-BUS Timing
    • Figure 36 - Generic Bus Timing
    • AC Electrical Characteristics� - TDM Ring Bus
    • Figure 37 - TDM Ring TX Timing Diagram
    • Figure 38 - TDM Ring RX Timing Diagram
    • AC Electrical Characteristics - JTAG Port and RESET Pin Timing
    • Figure 39 - JTAG Port Timing
    • AC Electrical Characteristics - System Clock and Reset
    • Figure 40 - System Clock and Reset
• 10.0 List of Abbreviations and Acronyms
• 11.0 ATM Glossary