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Электронный компонент: MT90225AG

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1
MT90225/226
16/8 Port TC PHY Device
Data Sheet
Features
General
Supports unframed serial streams up to 10 Mb/s
per T1/E1 or DSL link
Single chip ATM TC (Transmission Convergence)
processor
Versatile TDM Interface compatible with most
popular T1, E1 or DSL framers
Supports primary rate ISDN lines and Fractional
T1/E1
MT90225 supports up to 16 serial links &
MT90226 supports up to 8 serial links
MT90225/226 and MT90222/223/224 share the
same product package and pinout configuration.
Standards Compliant
ATM Forum - ATM over Fractional T1/E1
(AF-PHY-0130.00)
ITU G.804 cell mapping into T1 and E1
transmission systems & ITU I.432 cell delineation
TC and UNI
ATM framing using cell delineation
HEC (header error control) verification &
generation, error detection, and idle/unassigned
cell filtering
TC layer statistics and error counts i.e. HEC
errors with MIB support
Provides 8 & 16-bit UTOPIA Level 1 and 2 MPHY
Interface (MT90225/226 device slaved to ATM
device)
16 bit Microprocessor Interface, compatible with
Intel and Motorola busses
Loopback modes for diagnosis & testing
JTAG Test Support,
2.5V core, 3.3V I/O with 5V tolerant inputs
384 pin PGBA with 1.0 mm pitch balls
April 2003
Ordering Information
MT90225AG
384 Pin PBGA
MT90226AG
384 Pin PBGA
-40 to 85
C
Figure 1 - MT90225/226 Functional Block Diagram
Utopia
Level 2
BUS
Utopia
I/F CTRL
Processor I/F
Cell
CD Circuits (1 per link)
Transmission
Convergence
TC Circuits (1 per link)
S/P
P/S
T1/E1/DSL
Serial TDM Ports
RX
TX
(1 per link, up to 10Mb/s
Delineator
Rx Utopia
FIFo
Tx Utopia
FIFo
T1/E1/DSL
T1/E1/DSL
per link)
15
0
15
0
MT90225/226
Data Sheet
2
Zarlink Semiconductor Inc.
Applications
Provides cost effective solutions to implement TC (Transmission Convergence) functions over T1, E1, J1 or DSL
transport facilities in broadband access networks. Typical applications are for trunking or subscriber access in:
Integrated multi-service access platforms
Access multiplexers
Next-generation DLCs
Wireless local loop
3G wireless base-stations
Overview
The MT90226 and MT90225 form a family of similar devices, differing only in the maximum number of serial links,
and are collectively referred to as MT90225/226. It should be noted throughout this document whenever reference
is made to the number of serial links that the MT90225 offers a maximum of 16 serial links (links 15:0), while the
MT90226 offers a maximum of 8 serial links (links 14,12,10,8,6,4,2 and 0). Pin and register compatibility has been
maintained to offer interchangeability.
Description
The MT90225/226 device is targeted to systems implementing TC or UNI (User Network Interface) specifications
for T1/E1 rates or DSL rates. In the MT90225/226 architecture, up to 16/8 physical and independent serial links can
be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs and DSL chip sets.
The MT90225/226 device provides ATM system designers with a flexible architecture when implementing ATM
access over existing trunk interfaces, allowing a migration towards ATM service technology. The MT90225/226 is
compliant with ATM TC/UNI specifications for T1/E1 rates. The MT90225/226 can be configured to operate in
different TDM modes to facilitate the implementation of ATM over T1/E1/DSL at both CPE and Central Office sites.
The device allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 1 and Level 2 specification
at rates up to 52Mhz.
Main functions that are implemented in the MT90225/226 device are:
Utopia Level 1 or 2 PHY Interface
Incoming HEC verification and correction (optional),
Generation of a new HEC byte
Format outgoing bytes into multi-vendor TDM formats
Retrieve ATM Cells from the incoming multi-vendor TDM format
Perform cell delineation
Provide various counters to assist in performance monitoring
Generation and insertion of Idle Cells; The Idle cells are pre-defined.
Provide structured Interrupt scheme to report various events
16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
loopbacks
Data Sheet
MT90225/226
3
Zarlink Semiconductor Inc.
Table of Contents
1.0 Device Architecture .........................................................................................................22
1.1 MT90225/6 Main Functions ...................................................................................................................... 22
2.0 The ATM Transmit Path...................................................................................................22
2.1 Cell In Control ........................................................................................................................................... 23
2.2 The ATM Transmission Convergence ...................................................................................................... 24
2.2.1 TX Cell RAM and TX Link FIFO Length .......................................................................................... 24
2.3 Parallel to Serial TDM Interface ................................................................................................................ 24
3.0 The ATM Receive Path ....................................................................................................25
3.1 Cell Delineation Function .......................................................................................................................... 25
3.1.1 Cell Delineation with Sync signal..................................................................................................... 27
3.1.2 Cell Delineation without Sync signal................................................................................................ 27
3.2 De-Scrambling and ATM Cell Filtering...................................................................................................... 27
4.0 Description of the TDM Interface....................................................................................27
4.1 Single mode .............................................................................................................................................. 27
4.1.1 Single mode - Generic 1.544MHz ................................................................................................... 28
4.1.2 Single mode - Generic 2.048MHz ................................................................................................... 28
4.1.3 Single mode -ST-BUS ..................................................................................................................... 29
4.2 Wire-OR mode .......................................................................................................................................... 30
4.2.1 Wire-OR mode - 2 link grouping ...................................................................................................... 30
4.2.2 Wire-OR mode - 4 link grouping ...................................................................................................... 30
4.3 Multiplex mode.......................................................................................................................................... 31
4.3.1 Multiplex mode - 2 link multiplexing................................................................................................. 31
4.3.2 Multiplex mode - 4 link multiplexing................................................................................................. 31
4.4 Non-framed mode ..................................................................................................................................... 32
4.4.1 Non-framed mode - 2.5Mbps........................................................................................................... 32
4.4.2 Non-framed mode - 5.0Mbps........................................................................................................... 32
4.4.3 Non-framed mode - 10.0Mbps......................................................................................................... 33
4.5 Clock formats ............................................................................................................................................ 33
4.6 TDM Loopback Mode................................................................................................................................ 33
4.7 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters................................................................. 34
4.8 Clocking Options....................................................................................................................................... 34
4.8.1 Verification of the RXSYNC Period ................................................................................................. 35
4.8.2 Verification of the TXSYNC Period.................................................................................................. 35
4.8.3 Primary and Secondary Reference Signals..................................................................................... 35
4.8.4 Verification of Clock Activity ............................................................................................................ 35
4.8.5 Clock Selection................................................................................................................................ 36
5.0 UTOPIA Interface Operation ...........................................................................................36
5.1 ATM Input Port.......................................................................................................................................... 36
5.2 ATM Output Port ....................................................................................................................................... 37
5.3 UTOPIA Operation.................................................................................................................................... 37
5.4 UTOPIA Operation With a Single PHY ..................................................................................................... 37
5.5 UTOPIA Operation with Multiple PHY....................................................................................................... 38
5.6 UTOPIA Loopback .................................................................................................................................... 38
5.7 Examples of UTOPIA Operation Modes ................................................................................................... 38
6.0 Support Blocks ................................................................................................................39
6.1 Counter Block ........................................................................................................................................... 39
6.1.1 UTOPIA Input I/F counters .............................................................................................................. 39
6.1.2 Transmit TDM I/F Counters ............................................................................................................. 40
6.1.3 Receive TDM I/F Counters .............................................................................................................. 40
6.1.4 Access to the Counters ................................................................................................................... 40
6.1.5 Latching counter mode .................................................................................................................... 40
6.2 Interrupt Block........................................................................................................................................... 41
MT90225/226
Data Sheet
4
Zarlink Semiconductor Inc.
Table of Contents
6.2.1 IRQ Master Status and IRQ Master Enable Registers .................................................................... 41
6.2.2 IRQ Link Status and IRQ Link Enable Registers ............................................................................. 42
6.2.3 IRQ Link TC Overflow Status Registers .......................................................................................... 42
6.3 Microprocessor Interface Block................................................................................................................. 43
6.3.1 Access to the Various Registers...................................................................................................... 43
6.3.2 Direct Access................................................................................................................................... 43
6.3.3 Indirect Access ................................................................................................................................ 43
6.3.4 Clearing of Status Bits ..................................................................................................................... 43
6.3.4.1 Toggle Bit............................................................................................................................... 43
7.0 Register Descriptions..................................................................................................... 44
7.1 Register Summary .................................................................................................................................... 44
7.2 Detailed Register Description: .................................................................................................................. 45
8.0 Application Notes ............................................................................................................ 64
8.1 Connecting the MT90225/226 to Various T1/E1/J1 Framers.................................................................... 64
9.0 AC/DC Characteristics .................................................................................................... 68
9.1 CPU Interface Timing................................................................................................................................ 73
10.0 List of Abbreviations and Acronyms ........................................................................... 83
11.0 ATM Glossary................................................................................................................. 84
Data Sheet
MT90225/226
5
Zarlink Semiconductor Inc.
List of Figures
Figure 1 - MT90225/226 Functional Block Diagram ................................................................................................1
Figure 2 - MT90226 Pinout (Bottom View) ..............................................................................................................9
Figure 3 - MT90225 Pinout (Bottom View) ........................................................................................................... 10
Figure 4 - MT90225/226 Functional Block Diagram -Transmitter ........................................................................ 23
Figure 5 - Example of TC Mode Operation (Using Four of Sixteen Possible UTOPIA-Output Ports) .................. 25
Figure 6 - Cell Delineation State Diagram............................................................................................................ 25
Figure 7 - SYNC State Block Diagram ................................................................................................................. 26
Figure 8 - Single mode - Generic 1.544 MHz....................................................................................................... 28
Figure 9 - Single mode - Generic 2.048 MHz....................................................................................................... 29
Figure 10 - Single mode - ST-BUS....................................................................................................................... 29
Figure 11 - TXCK and TXSYNC Output Pin Source Options ............................................................................... 35
Figure 12 - ATM Interface to MT90225/226 ......................................................................................................... 38
Figure 13 - ATM Interface to Multiple MT90225/226............................................................................................ 39
Figure 14 - IRQ Register Hierarchy...................................................................................................................... 41
Figure 15 - MT90225 interfacing MT9076 ST-BUS mode with all links synchronous. ......................................... 64
Figure 16 - MT90225 interfacing MT9076 ST-BUS mode with asynchronous links............................................. 65
Figure 17 - MT90225 interfacing MT9076 Generic mode with asynchronous links. ............................................ 66
Figure 18 - MT90225 interfacing MT9072 ............................................................................................................ 67
Figure 19 - Setup and Hold Time Definition ......................................................................................................... 72
Figure 20 - Tri-State Timing ................................................................................................................................. 72
Figure 21 - Output Delay Timing .......................................................................................................................... 72
Figure 22 - CPU Interface Motorola Timing - Read Access ................................................................................. 74
Figure 23 - CPU Interface Intel Timing - Read Access ........................................................................................ 75
Figure 24 - CPU Interface Motorola Timing - Write Access ................................................................................. 76
Figure 25 - CPU Interface Intel Timing - Write Access......................................................................................... 77
Figure 26 - ST-BUS Timing .................................................................................................................................. 79
Figure 27 - Generic Bus Timing ........................................................................................................................... 80
Figure 28 - JTAG Port Timing .............................................................................................................................. 81
Figure 29 - System Clock and Reset.................................................................................................................... 82