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Электронный компонент: MT9040

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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
JTAG Boundary Scan
Applications
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
November 2003
Ordering Information
MT9040AN 48 pin SSOP
-40
C to +85
C
MT9040
T1/E1 Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
IEEE
1149.1a
Feedback
Control State Machine
DPLL
Frequency
Select
MUX
Input
Impairment
Monitor
Output
Interface
Circuit
MS
FS1
FS2
TCK
RST
VDD
VSS
C1.5o
C19o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
OSCo
OSCi
Master Clock
TDO
TDI
TMS
TRST
C6o
RSP
TSP
FLOCK
LOCK
IM
REF
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
MT9040
Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1,10,
23,31
V
SS
Ground. 0 Volts. (Vss pads).
2
RST
Reset (Input). A logic low at this input resets the MT9040. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low for a minimum of 300ns. While the RST pin is low, all frame pulses except
RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST,
TSP, C6o and C16o are at logic low during reset. The C19o is free-running during reset.
Following a reset, the input reference source and output clocks and frame pulses are phase
aligned as shown in Figure 9.
3,4,5,
38,43
IC
Internal Connection. Leave open circuit.
6
REF
Reference (Input). This is the input reference source (falling edge) used for synchronization.
One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used.
7,17
28,35
V
DD
Positive Supply Voltage. +3.3V
DC
nominal.
8
OSCo
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 6. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected, see Figure 5.
9
OSCi
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected
from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is connected to a
clock source, see Figure 5.
11
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 11.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
TRST
TDI
TDO
IC
IC
FS1
FS2
IC
IC
IC
MS
Vdd
IC
IC
NC
Vss
IC
IM
Vdd
RST
IC
IC
REF
Vdd
OSCo
OSCi
Vss
F16o
TSP
F8o
C1.5o
C2o
C4o
C19o
48
TMS
V
SS
21
27
C6o
FLOCK
22
26
Vss
23
25
C8o
IC
24
C16o
MT9040AN
TCK
RSP
F0o
IC
Vdd
LOCK
MT9040
Data Sheet
3
Zarlink Semiconductor Inc.
12
F0o
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.
13
RSP
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which
marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens
MUNICH-32 device. See Figure 12.
14
TSP
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 12.
15
F8o
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks
the beginning of a frame. See Figure 11.
16
C1.5o
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
18
LOCK
Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
19
C2o
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
20
C4o
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
21
C19o
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
22
FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
24
IC
Internal Connection. Tie low for normal operation.
25
C8o
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
26
C16o
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384MHz clock.
27
C6o
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29
IM
Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
30
IC
Internal Connection. Tie high for normal operation.
32
NC
No Connection. Leave open circuit.
33,34,
42
IC
Internal Connection. Tie low for normal operation.
36
MS
Mode/Control Select (Input). This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
37, 39
IC
Internal Connection. Tie low for normal operation.
40
FS2
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the REF input. See
Table 1.
41
FS1
Frequency Select 1 (Input). See pin description for FS2.
44
TDO
Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
Pin Description (continued)
Pin #
Name
Description
MT9040
Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
The MT9040 is a T1/E1 Trunk Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Frequency Select MUX Circuit
The MT9040 operates on the falling edge of the reference. It operates with one of four possible input reference
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine
which of the four frequencies may be used at the reference input. A reset (RST) must be performed after every
frequency select input change. See Table 1.
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled
Oscillator and a Control Circuit.
Phase Detector - the Phase Detector compares the reference signal with the feedback signal from the Frequency
Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally
selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
45
TDI
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
46
TRST
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
47
TCK
Test Clock (Input). Provides the clock to the JTAG test logic.
48
TMS
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller.
FS2
FS1
Input Frequency
0
0
19.44MHz
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
Pin Description (continued)
Pin #
Name
Description
MT9040
Data Sheet
5
Zarlink Semiconductor Inc.
Figure 3 - DPLL Block Diagram
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the network
jitter transfer requirements are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the MT9040.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference
sinal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to
the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock
Indicator design recommendations, see the Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and five frame pulse outputs. The
C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
Reference