1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports AT&T TR62411 and Bellcore GR-
1244-CORE Stratum 4 Enhanced and Stratum 4
timing for DS1 Interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 Interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C8 and C16 output
clock signals
Provides 3 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
Applications
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Description
The MT9041B T1/E1 System Synchronizer contains
a digital phase-locked loop (DPLL), which provides
timing and synchronization signals for multitrunk T1
and E1 primary rate transmission links.
The MT9041B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9041B is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 4 Enhanced,
Stratum 4, and ETSI ETS 300 011. It will meet the
jitter tolerance, jitter transfer, intrinsic jitter, frequency
accuracy, capture range and phase change slope
requirements for these specifications.
November 2003
Ordering Information
MT9041BP
28 Pin PLCC
-40
C to +85
C
MT9041B
T1/E1 System Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
Mode Select
Divider
Output
Interface
Circuit
MS
FS1
FS2
RST
VDD
VSS
C3o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
REF
OSCi
OSCo
Phase
Detector
Filter
DCO
Loop
MT9041B
Data Sheet
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Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
V
SS
Ground. 0 Volts.
2
IC0
Internal Connect. Connect to Vss
3
NC
No Connect. Connect to Vss
4
REF
Reference (TTL Input). PLL reference clock.
5
V
DD
Positive Supply Voltage. +5V
DC
nominal.
6
OSCo
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 6. For clock oscillator operation, this pin is left
unconnected, see Figure 5.
7
OSCi
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected
from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is connected to a
clock source, see Figure 5.
8
F16o
Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 16.384Mb/s. See Figure 11.
9
F0o
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.
10
F8o
Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS operation at
8.192Mb/s. See Figure 11.
11
C1.5o
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
12
C3o
Clock 3.088MHz (CMOS Output). This optional output is used in T1 applications.
13
C2o
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
14
C4o
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
1
6
5
4 3 2
7
8
9
10
11
23
19
20
21
22
24
25
26
27
28
VSS
IC
0
NC
RE
F
VDD
OSCo
OSCi
F16o
F0o
F8o
C1.5o
IC0
IC1
IC0
IC0
MS
IC0
IC0
FS2
FS1
RS
T
12 13 14 15 16 17 18
C2
o
VSS
C8
o
C16
o
VDD
C4
o
C3
o
MT9041B
MT9041B
Data Sheet
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Zarlink Semiconductor Inc.
Functional Description
The MT9041B is a System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface
circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 is a functional block diagram which is described in the following sections.
Frequency Select MUX Circuit
The MT9041B operates on the falling edges of one of three possible input reference frequencies (8kHz, 1.544MHz
or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at
the reference input (REF). A reset (RST) must be performed after every frequency select input change. Operation
with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1.
Table 1 - Input Frequency Selection
15
V
SS
Ground. 0 Volts.
16
C8o
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
17
C16o
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/s.
18
V
DD
Positive Supply Voltage. +5V
DC
nominal.
19
IC0
Internal Connect. Connect to Vss
20
IC1
Internal Connect. Leave open Circuit
21
IC0
Internal Connect. Connect to Vss
22
IC0
Internal Connect. Connect to Vss
23
MS
Mode/Control Select (TTL Input). This pin, determines the device's state (Normal, or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
24
IC0
Internal Connect. Connect to Vss
25
IC0
Internal Connect. Connect to Vss
26
FS2
Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three
possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See
Table 1.
27
FS1
Frequency Select 1 (TTL Input). See pin description for FS2.
28
RST
Reset (Schmitt Input). A logic low at this input resets the MT9041B. To ensure proper
operation, the device must be reset after reference signal frequency changes and power-up.
The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame
and clock outputs are at logic high. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 10.
FS2
FS1
Input Frequency
0
0
Reserved
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
Pin Description (continued)
Pin #
Name
Description
MT9041B
Data Sheet
4
Zarlink Semiconductor Inc.
Digital Phase Lock Loop (DPLL)
The DPLL of the MT9041B consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a
Control Circuit (see Figure 3).
Phase Detector - the Phase Detector compares the primary reference signal (REF) with the feedback signal from
the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the
two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal
to be externally selected (e.g., 8kHz, 1.544MHz or 2.048MHz).
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum
phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by Bellcore GR-1244-CORE Stratum 4E.
Figure 3 - DPLL Block Diagram
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three
reference frequency selections (8kHz, 1.544MHz or 2.048MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit sets the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9041B.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider
Circuit to generate the required output signals.
Two tapped delay lines are used to generate a 16.384MHz and a 12.352MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by
dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.
Control
Circuit
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
REF Reference
Limiter
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
MT9041B
Data Sheet
5
Zarlink Semiconductor Inc.
Figure 4 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o,
C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the
selected input reference in Normal Mode. See Figures 11 and 12.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g. 30pF) loads.
Master Clock
The MT9041B can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Modes of Operation
The MT9041B can operate either in Normal or Freerun modes.
As shown in Table 2, pin MS selects between NORMAL and FREERUN modes.
MS
Description of Operation
0
NORMAL
1
FREERUN
Table 2 - Operating Modes
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C3o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Tapped
Delay
Line
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