1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports AT&T TR62411 and Bellcore GR-1244-
CORE Stratum 3, Stratum 4 Enhanced and
Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048
kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1,544
kbit/s interfaces and 2,048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different 8KHz framing pulses
Holdover frequency accuracy of 0.05 PPM
Holdover indication
Attenuates wander from 1.9Hz
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
Applications
Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
November 2003
Ordering Information
MT9044AP
44 Pin PLCC
MT9044AL
44 Pin MQFP
-40
C to +85
C
MT9044
T1/E1/OC3 System Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
MS1
MS2
GTo
GTi
FS1
FS2
TCK
SEC
RST
RSEL
LOS1
LOS2
VDD
VSS
TCLR
C3o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
OSCo
OSCi
C19o
TDO
PRI
TDI
TMS
TRST
C6o
RSP
TSP
ACKi
ACKo
HOLDOVER
Output
Interface
Circuit
Frequency
Select
MUX
Master Clock
APLL
Feedback
Guard Time
Circuit
State
Select
Input
Impairment
Monitor
Virtual
Reference
DPLL
TIE
Corrector
Circuit
State
Select
IEEE
1149.1a
Automatic/Manual
Control State Machine
Reference
Select
MUX
Reference
Select
TIE
Corrector
Enable
Selected
Reference
MT9044
Data Sheet
2
Zarlink Semiconductor Inc.
Description
The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz,
or 8kHz input reference.
The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and
Stratum 4; and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander
tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope,
holdover frequency and MTIE requirements for these specifications.
Figure 2 - Pin Connections
1
8
7
4 3
9
10
11
12
37
33
34
35
36
38
39
40
41
42
VSS
TCLR
SEC
PRI
VDD
OSCo
OSCi
F16o
F0o
F8o
C1.5o
GTi
GTo
LOS2
LOS1
MS2
MS1
RSEL
FS2
FS1
RS
T
18 19 20 21 22 23 24
ACKi
VSS
C8
o
C16
o
C4
o
C1
9o
MT9044AP
2
5
6
43
44
32
31
30
29
25 26 27 28
13
14
15
16
17
TC
K
TR
ST
TMS
TD
I
IC
VSS
TDO
C2
o
C6
o
AC
Ko
VD
D
C3
o
AVDD
TSP
RSP
VSS
HOLDOVER
39
2
1
42 41
3
4
5
6
31
27
28
29
30
32
33
34
35
36
VSS
TC
LR
SEC
PR
I
VDD
OSCo
OSCi
F16o
F0o
F8o
C1.5o
GTi
GTo
LOS2
LOS1
MS2
MS1
RSEL
FS
2
FS1
RST
12 13 14 15 16 17 18
ACKi
VSS
C8
o
C1
6
o
C4
o
C1
9o
MT9044AL
40
43
44
37
38
26
25
24
19 20 21 22
7
8
9
10
11
TC
LK
TR
ST
TMS
TD
I
HOLDOVER
IC
VSS
TDO
C2
o
C6
o
ACKo
VD
D
C3
o
AVDD
TSP
RSP
VSS
23
MT9044
Data Sheet
3
Zarlink Semiconductor Inc.
Pin Description
Pin #
PLCC
Pin #
MQFP
Name
Description
1,10,
23,31
39,4,17
,25
V
SS
Ground. 0 Volts.
2
40
TCK
Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is
internally pulled up to V
DD
.
3
41
TCLR
TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a re-alignment of input phase with output
phase as shown in Figure 19. The TCLR pin should be held low for a minimum of
300ns. This pin is internally pulled down to VSS.
4
42
TRST
Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.
5
43
SEC
Secondary Reference (TTL Input). This is one of two (PRI & SEC) input
reference sources (falling edge) used for synchronization. One of three possible
frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of
the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi
control inputs (Automatic or Manual). This pin is internally pulled up to V
DD
.
6
44
PRI
Primary Reference (TTL Input). See pin description for SEC. This pin is
internally pulled up to V
DD
.
7,28
1,22
V
DD
Positive Supply Voltage. +5V
DC
nominal.
8
2
OSCo
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz
crystal is connected from this pin to OSCi, see Figure 10. For clock oscillator
operation, this pin is left unconnected, see Figure 9.
9
3
OSCi
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal
is connected from this pin to OSCo, see Figure 10. For clock oscillator operation,
this pin is connected to a clock source, see Figure 9.
11
5
F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s. See Figure 20.
12
6
RSP
Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing
pulse, which marks the end of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
13
7
F0o
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active
low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.
14
8
TSP
Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for
connection to the Siemens MUNICH-32 device. See Figure 21.
15
9
F8o
Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse,
which marks the beginning of a frame. See Figure 20.
16
10
C1.5o
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
17
11
AVDD
Analog Vdd. +5V
DC
nominal.
18
12
C3o
Clock 3.088MHz (CMOS Output). This output is used in T1 applications.
MT9044
Data Sheet
4
Zarlink Semiconductor Inc.
19
13
C2o
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s.
20
14
C4o
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at
2.048Mb/s and 4.096Mb/s.
21
15
C19o
Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.
22
16
ACKi
Analog PLL Clock Input (CMOS Input). This input clock is a reference for an
internal analog PLL. This pin is internally pulled down to VSS.
24
18
ACKo
Analog PLL Clock Output (CMOS Output). This output clock is generated by
the internal analog PLL.
25
19
C8o
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at
8.192Mb/s.
26
20
C16o
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation
with a 16.384MHz clock.
27
21
C6o
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29
23
HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital
PLL goes into holdover mode.
30
24
GTi
Guard Time (Schmitt Input). This input is used by the MT9044 state machine in
both Manual and Automatic modes. The signal at this pin affects the state
changes between Primary Holdover Mode and Primary Normal Mode, and
Primary Holdover Mode and Secondary Normal Mode. The logic level at this input
is gated in by the rising edge of F8o. See Tables 4 and 5.
32
26
GTo
Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,
buffered and output on GTo. This pin is typically used to drive the GTi input
through an RC circuit.
33
27
LOS2
Secondary Reference Loss (TTL Input). This input is normally connected to the
loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the
SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs
control the MT9044 state machine when operating in Automatic Control. The logic
level at this input is gated in by the rising edge of F8o. This pin is internally pulled
down to VSS.
34
28
LOS1
Primary Reference Loss (TTL Input). Typically, external equipment applies a
logic high to this input when the PRI reference signal is lost or invalid. The logic
level at this input is gated in by the rising edge of F8o. See LOS2 description. This
pin is internally pulled down to VSS.
35
29
TDO
Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enabled.
36
30
MS2
Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,
determines the device's mode (Automatic or Manual) and state (Normal, Holdover
or Freerun) of operation. The logic level at this input is gated in by the rising edge
of F8o. See Table 3.
Pin Description (continued)
Pin #
PLCC
Pin #
MQFP
Name
Description
MT9044
Data Sheet
5
Zarlink Semiconductor Inc.
Functional Description
The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links.
Figure 1 shows the functional block diagram which is described in the following sections.
Reference Select MUX Circuit
The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables
1, 4 and 5.
Frequency Select MUX Circuit
The MT9044 operates with one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The
frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference
inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be
performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and
must not be used. See Table 1.
37
31
MS1
Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by
the rising edge of F8o. See pin description for MS2. This pin is internally pulled
down to VSS.
38
32
RSEL
Reference Source Select (TTL Input). In Manual Control, a logic low selects the
PRI (primary) reference source as the input reference signal and a logic high
selects the SEC (secondary) input. In Automatic Control, this pin must be at logic
low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
This pin is internally pulled down to VSS.
39
33
IC
Internal Connection. Tie low for normal operation.
40
34
FS2
Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects
which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input
to the PRI and SEC inputs. See Table 1.
41
35
FS1
Frequency Select 1 (TTL Input). See pin description for FS2.
42
36
TDI
Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted
in on this pin. This pin is internally pulled up to V
DD
.
43
37
RST
Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure
proper operation, the device must be reset after changes to the method of control,
reference signal frequency changes and power-up. The RST pin should be held
low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs
are at logic high. Following a reset, the input reference source and output clocks
and frame pulses are phase aligned as shown in Figure 19.
44
38
TMS
Test Mode Select (TTL Input). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
.
Pin Description (continued)
Pin #
PLCC
Pin #
MQFP
Name
Description
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