1
Features
AAL2 Segmentation Reassembly device
capable of simultaneously processing up to
1023 active CIDs (AAL2 Channel Identifier) and
1023 active VCs (Virtual Circuits).
Support for up to 255 CIDs per VC. Maximum of
1023 CIDs.
Implements AAL2 Common Part Sub-layer
(CPS) functions specified in ITU I.363.2.
Implements AAL2 Service Specific
Convergence Sub-layer (SSCS) functions for
G.711 PCM and G.726 ADPCM voice.
Supports 44-byte PCM or ADPCM packet
profiles specified in AF-VMOA-0145.00.
CPS packet payload can support up to
64-bytes.
Supports over-subscription of 10:1.
H.100/H.110 compatible TDM bus for PCM or
ADPCM data. Supports both master and slave
TDM bus clock operation.
TDM bus also supports compressed voice such
as ITU G.723, G.728 and G.729 through HDLC
encapsulation.
Three UTOPIA Level 1 ports configurable as
PHY or ATM allowing for connection to an
external AAL5 SAR processor, or for chaining
multiple MT90502 devices. Ports A & B are
configurable as a single 8-bit UTOPIA Level 2
PHY port with 5 ADDR lines.
UTOPIA module provides a cell switching
function with a header translation.
Performs silence suppression for PCM and
ADPCM.
Comfort noise generation.
Capability to inject and recover CPS packets
through the CPU host processor bus.
8-bit or 16-bit microprocessor port, configurable
to Motorola or Intel timing.
Single rail 3.3 V, 456 PBGA.
IEEE 1149 (JTAG) interface.
DS5420
ISSUE 1
November 2001
Ordering Information
MT90502AG
456 Pin Plastic BGA
0 to +70
C
MT90502
Multi-Channel AAL2 SAR
Preliminary Datasheet
Figure 1 - MT90502 Functional Block
Memory Bank A
Memory Bank B (Optional)
Dual Memory Controller
UTOPIA
Port
A
Port
B
Port
C
RxA Port
TxA Port
RxB Port
TxB Port
RxC Port
TxC Port
TDM
RX
AAL2 SAR
Receiver
AAL2 SAR
Transmitter
Clock
Recovery
CPU Interface
JTAG Interface
Clock and
Frame
Pulse
TDM Bus
4096 x 64 kbps
Module
MT90502
and
Generation
Module
SSRAM
(max: 1M x18)
SDRAM
(max: 8M x16)
SSRAM
(max: 1M x18)
SDRAM
(max: 8M x16)
CPS Packets
TX
CPS Packets
MT90502
Preliminary Datasheet
2
Applications
Gateway
ATM Edge Switch
Next Generation Digital Loop Carrier
Multiservice Switching Platform
3rd Generation Mobile System Equipment
Description
The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a
standard ATM (Asynchronous Transfer Mode) bus. The device provides the CPS (Common Part Sublayer) and
SAR (Segmentation and Reassembly) engines. The MT90502 has the capability of simultaneously processing
1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits). The device
can be connected directly to an H.110 compatible bus. The TDM bus consists of 32 bi-directional serial data
streams operating at 2.048, 4.096, or 8.192 Mbits/s.
The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential
Pulse Code Modulation) traffic for packetisation. For these two data formats, the device also implements
silence suppression and comfort noise generation. To support other voice compression algorithms, the
MT90502 connects directly to commercially available DSPs through synchronous serial data streams. The
Variable Bit Rate (VBR) traffic is HDLC encapsulated and carried over the serial data streams.
The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the
UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a
compliant UTOPIA Level 2 Multi-PHY port. The MT90502 provides the capability of routing ATM cells to
different UTOPIA interfaces, SAR engine or CPU. This feature can be used to connect another MT90502 (to
support up to 2046 CID channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR.
Preliminary Datasheet
MT90502
3
1.0 Pin-out..................................................................................................................................7
1.1 Pin Description Tables ................................................................................................................................ 8
2.0 Functional Description .....................................................................................................15
2.1 CPU Interface............................................................................................................................................ 15
2.1.1 CPU Interrupts ..................................................................................................................................... 15
2.1.1.1 Example Interrupt Flow .................................................................................................................. 15
2.1.1.1.1 Interrupt Initialisation ................................................................................................................ 16
2.1.1.1.2 Interrupt Servicing ................................................................................................................... 16
2.1.2 Intel/Motorola Interface ........................................................................................................................ 16
2.1.2.1 Extended Indirect Accessing .......................................................................................................... 18
2.1.2.1.1 Extended Indirect Writes ......................................................................................................... 18
2.1.2.1.2 Extended Indirect Reads ......................................................................................................... 19
2.1.2.2 Extended Direct Accessing ............................................................................................................ 19
2.1.2.2.1 Extended Direct Writes ............................................................................................................ 19
2.1.2.2.2 Extended Direct Reads ............................................................................................................ 19
2.1.3 MT90502 Reset Procedure.................................................................................................................. 20
2.2 TDM Transmission .................................................................................................................................... 21
2.2.1 Low-Latency Loopback Channels........................................................................................................ 22
2.2.2 Treatment of PCM/ADPCM Data ......................................................................................................... 22
2.2.2.1 CPS-Packet Length ........................................................................................................................ 24
2.2.2.2 TDM Data Formats ......................................................................................................................... 24
2.2.2.3 Phase Alignment ............................................................................................................................ 29
2.2.2.4 PCM/ADPCM CPS-Packet Assembly Structure ............................................................................ 31
2.2.3 Treatment of HDLC Data ..................................................................................................................... 32
2.2.3.1 HDLC Streams ............................................................................................................................... 32
2.2.3.2 Address Bytes ................................................................................................................................ 32
2.2.3.3 Control Bytes and Length ............................................................................................................... 34
2.2.3.4 "Raw" AAL2 CPS-Packets ............................................................................................................. 34
2.2.4 CPS-Packet Final Assembly ................................................................................................................ 35
2.2.4.1 CPU CPS-Packets ......................................................................................................................... 36
2.2.4.2 CPS-Packet Descriptor Queue ...................................................................................................... 38
2.2.4.3 TDM Frame Buffer ......................................................................................................................... 39
2.3 TX SAR ..................................................................................................................................................... 40
2.3.1 Overview .............................................................................................................................................. 40
2.3.2 AAL2 Cell Assembly Process .............................................................................................................. 40
2.3.2.1 AAL2 Cell Assembly Procedure ..................................................................................................... 42
2.3.3 AAL0 Cells ........................................................................................................................................... 43
2.4 RX SAR ..................................................................................................................................................... 44
2.4.1 RX AAL2 VC Structure ........................................................................................................................ 44
2.4.2 CID Structure ....................................................................................................................................... 45
2.4.3 CPS-Packet Disassembly Structures .................................................................................................. 46
2.4.4 CPS-Packet Loss Compensation ........................................................................................................ 52
2.4.5 CPU CPS-Packets ............................................................................................................................... 52
2.4.6 Treatment of Data Cells ....................................................................................................................... 53
2.4.7 Errors and Events ................................................................................................................................ 53
2.5 TDM Reception ......................................................................................................................................... 56
2.5.1 Overview .............................................................................................................................................. 56
2.5.2 RX Channel Association Memory ........................................................................................................ 57
2.5.3 RX Channel Underrun Condition ......................................................................................................... 57
2.5.4 Compression........................................................................................................................................ 59
2.5.5 HDLC ................................................................................................................................................... 60
2.6 UTOPIA ..................................................................................................................................................... 62
2.6.1 Overview .............................................................................................................................................. 62
MT90502
Preliminary Datasheet
4
2.6.2 UTOPIA Interfaces............................................................................................................................... 63
2.6.3 LED Operation ..................................................................................................................................... 63
2.6.4 Errors on Received Cells ..................................................................................................................... 63
2.6.5 Cell Routing ......................................................................................................................................... 64
2.6.5.1 Mask & Match Process .................................................................................................................. 64
2.6.5.2 Look-Up Tables Entries ................................................................................................................. 65
2.6.5.3 LUT Addressing ............................................................................................................................. 66
2.6.6 UTOPIA Clocks.................................................................................................................................... 67
2.6.7 External Interface Signals.................................................................................................................... 69
2.6.8 UTOPIA Flow Control .......................................................................................................................... 69
2.7 H.100/H.110 Interface ................................................................................................................................70
2.7.1 Overview.............................................................................................................................................. 70
2.7.2 Bus Signaling....................................................................................................................................... 70
2.7.3 H.100/H.110 Slave............................................................................................................................... 70
2.7.4 Operating as a Slave ........................................................................................................................... 71
2.7.5 Operating as a Master ......................................................................................................................... 71
2.7.6 H.100/H.110 Clock Selection Guide .................................................................................................... 72
2.8 Clock Recovery ..........................................................................................................................................75
2.8.1 Overview.............................................................................................................................................. 75
2.8.1.1 Adaptive Clock Recovery Modules ................................................................................................ 75
2.8.1.1.1 adapx_ref clock generation ...................................................................................................... 75
2.8.1.2 Multiplexers .................................................................................................................................... 75
2.8.2 Adaptive Clock Recovery Modules ...................................................................................................... 75
2.8.2.1 adapx_ref Clock Generation .......................................................................................................... 78
2.8.3 Multiplexers.......................................................................................................................................... 78
2.9 Silence Suppression ..................................................................................................................................83
2.9.1 Overview.............................................................................................................................................. 83
2.9.2 Simple Silent Suppression................................................................................................................... 83
2.9.2.1 Silent Bit Indication ........................................................................................................................ 83
2.9.2.2 Last Byte Indication ........................................................................................................................ 83
2.9.2.3 Match and Mask Determines Silence ............................................................................................ 83
2.9.3 Complex Silent Suppression................................................................................................................ 84
2.9.3.1 Complex Silent Suppression Operation ......................................................................................... 85
2.9.3.1.1 PCM Law Table ........................................................................................................................ 85
2.9.3.1.2 DC Offset Calculation ............................................................................................................... 86
2.9.3.1.3 Signal Energy Calculation ........................................................................................................ 86
2.9.3.2 CPS-Packet Silence State ............................................................................................................. 87
2.9.3.2.1 Silence Suppression State Table ............................................................................................. 87
2.9.3.2.2 SID Transmission Operation .................................................................................................... 87
2.9.3.2.3 SID Reception Operation ......................................................................................................... 87
2.9.4 Voice/Silence Timer............................................................................................................................. 90
2.10 HDLC .......................................................................................................................................................94
2.10.1 HDLC Overview ................................................................................................................................. 94
2.10.2 HDLC Format..................................................................................................................................... 94
2.10.3 HDLC Bit-Wise Format ...................................................................................................................... 97
2.10.4 HDLC Byte-Wise Format ................................................................................................................... 97
2.11 Memory ....................................................................................................................................................97
2.11.1 Memory Map ...................................................................................................................................... 97
2.11.2 Memory Structures ............................................................................................................................ 98
2.11.3 Mem_Clk and Upclk......................................................................................................................... 103
2.11.4 Memory Controller ........................................................................................................................... 104
2.11.4.1 Overview .................................................................................................................................... 104
2.11.4.2 Functionality ............................................................................................................................... 104
2.11.5 Initializing SSRAM and SDRAM ...................................................................................................... 104
2.11.6 Memory Configuration ..................................................................................................................... 105
Preliminary Datasheet
MT90502
5
3.0 Register List ....................................................................................................................107
3.1 CPU Register .......................................................................................................................................... 107
3.2 Main Registers ........................................................................................................................................ 110
3.3 TX Registers............................................................................................................................................ 125
3.4 RX Registers ........................................................................................................................................... 126
3.5 TX TDM Registers................................................................................................................................... 131
3.6 UTOPIA Registers................................................................................................................................... 136
3.7 H.100/H.110 Registers ............................................................................................................................ 152
3.8 Miscellaneous Registers ......................................................................................................................... 166
3.9 RX TDM Registers .................................................................................................................................. 169
4.0 Electrical Specification...................................................................................................171
4.1 DC Characteristics .................................................................................................................................. 171
4.2 AC Characteristics................................................................................................................................... 173
4.3 Intel/Motorola Interface............................................................................................................................ 173
4.3.1 UTOPIA Interface .............................................................................................................................. 181
4.3.2 External Memory Interface................................................................................................................. 181
4.3.3 H.100/H.110 Interface........................................................................................................................ 182
5.0 Glossary of Terminology................................................................................................186
5.1 Standard Terms and Abbreviations......................................................................................................... 186
5.2 Terms specific to AAL2 ........................................................................................................................... 187
5.3 Terms specific to this specification.......................................................................................................... 187
5.4 Register types ......................................................................................................................................... 187
5.5 Units and Conventions ............................................................................................................................ 188
6.0 Mechanical Drawing .......................................................................................................189
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