Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

�

AAL1 Segmentation and Reassembly device
compliant with Circuit Emulation Services (CES)
standard (af-vtoa-0078.000)

�

Supports both Unstructured and Structured
Circuit Emulation of 28 independent DS1/E1/ST-
BUS interfaces

�

Supports AAL1 trunking, with up to 128 TDM
channels per VC (af-vtoa-0089.001)

�

Supports CAS transmission and reception in all
structured modes of operation

�

Supports simultaneous processing of up to 896
bidirectional Virtual Circuits

�

Supports mixed DS1/E1 operation

�

Supports mixed Unstructured and Structured
CES operation

�

Fully flexible DS0 assignment

�

Complete clock recovery solution provided on-
chip: Synchronous, Adaptive, or Synchronous
Residual Time Stamp (SRTS) via 28 independent
PLLs

�

Dual-mode (ATM-end or PHY-end) UTOPIA port
operates in Level 1 or Level 2 mode for
connection to external PHY or ATM devices with
UTOPIA clock rate up to 52 MHz

�

TDM bus provides 28 bidirectional serial streams
at 1.544, 2.048, or 4.096 MHz - compatible with
Generic (1.544 Mbps or 2.048 Mbps) and ST-
BUS (2.048 Mbps) interfaces

�

Supports master and slave TDM backplane bus
clock operation

�

Supports TDM and UTOPIA loopback functions

�

16-bit microprocessor port, configurable to
Motorola or Intel timing

�

Master clock rate of 66.0 MHz

Figure 1 - MT90528 Block Diagram

Segmentation / Reassembly

Circular Buffers

VC Look-Up

Table

External
Synchronous
SRAM (ZBT)

External Memory Controller

UTOPIA

INPUT

BLOCK

JTAG

Interface

16-bit Microprocessor

Interface

Boundary-

Scan Logic

Microprocessor

Interface Logic

UTOPIA
Interface

UTOPIA

OUTPUT

BLOCK

Local

Memory

TDM

INPUT

BLOCK

Tx/Segmentation (X 28)

SAR

Local

Memory

TDM

OUTPUT

BLOCK

RX SARs

(UDT, SDT,

Data)

Rx/Reassembly (X 28)

PLL

Clock

Management

TDM Input
Interface

TDM Output
Interface

MT90528

Clock Control
/Recovery
Interface

October 2003

Ordering Information

MT90528AG

456 Pin Plastic BGA

-40 to +85�C

MT90528

28-Port Primary Rate

Circuit Emulation AAL1 SAR

Data Sheet

MT90528

Data Sheet

Zarlink Semiconductor Inc.

Applications

�

B-ISDN (Broadband ISDN) systems requiring flexible N x 64kbps transport

�

Systems requiring af-vtoa-0078.000 (ATM Forum CES v2.0) "DS1 or E1 Nx64 Basic Service", "DS1 or E1
Nx64 Service with CAS", or "DS1 or E1 Unstructured Service" - flexible CES allows one-board solution to
support multiple CES modes

�

Systems requiring af-vtoa-0089.001 (ATM Forum - ATM Trunking Using AAL1 for Narrowband Services) -
transport of up to 128 channels per VC

�

Ideal for carrier-class WAN access products, especially channelized DS3 or E3 interfaces

�

ATM Edge Switches

�

Carrier Class Voice over ATM systems

�

ATM Public Network access for PBX or CO

�

TDM traffic transfer over an asynchronous cell bus

Description

The MT90528 28-Port Primary Rate Circuit Emulation AAL1 SAR allows primary rate TDM circuits to be carried
over ATM networks using Circuit Emulation Services. Up to 896 bidirectional ATM VC connections can be
simultaneously processed by the MT90528 CES AAL1 SAR device.

The MT90528 supports several modes of Circuit Emulation Services for DS1 and E1 rates. These include
Unstructured CES and Structured CES with and without Channel Associated Signalling (CAS).

On the TDM bus side, the MT90528 interfaces with 28 primary rate TDM ports operating at 1.544 Mbps or 2.048
Mbps. The configurable TDM ports interface directly with DS1 or E1 framers for Nx64 Structured operation, or with
DS1 or E1 LIUs in Unstructured mode.

On the ATM interface side, the MT90528 device meets the ATM Forum standard for UTOPIA Bus Level 2. The
MT90528 is capable of operating as a UTOPIA "master" (ATM-end), "slave" (PHY-end), or "multi-PHY slave" (PHY-
end). The UTOPIA port can operate in 8-bit or 16-bit mode, with a clock rate up to 52 MHz.

Each of the twenty-eight ports of the device contains a PLL, allowing independent timing of each TDM port. Each
PLL supports four modes of clock recovery: SRTS, Adaptive, Synchronous (from the Physical layer), or from the
TDM line clock. Although a complete clock recovery solution is provided internally, an optional external PLL or
external clock source is also supported.

PURCHASE OF THIS PRODUCT DOES NOT GRANT THE PURCHASER ANY RIGHTS UNDER PATENT NO.
5,260,978. USE OF THIS PRODUCT OR ITS RE-SALE AS A COMPONENT OF ANOTHER PRODUCT MAY
REQUIRE A LICENSE UNDER THE PATENT WHICH IS AVAILABLE FROM TELCORDIA TECHNOLOGIES,
INC., 445 SOUTH STREET, MORRISTOWN, NEW JERSEY 07960.

ZARLINK ASSUMES NO RESPONSIBILITY OR LIABILITY THAT MAY RESULT FROM ITS CUSTOMERS' USE
OF ZARLINK PRODUCTS WITH RESPECT TO THIS PATENT. IN PARTICULAR, ZARLINK'S PATENT
INDEMNITY IN ITS TERMS AND CONDITIONS OF SALES WHICH ARE SET OUT IN ITS SALES
ACKNOWLEDGEMENTS AND INVOICES DOES NOT APPLY TO THIS PATENT.

MT90528

Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 1 - Microprocessor Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2 - External Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3 - TDM Port Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4 - UTOPIA Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5 - Clock Management Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6 - Master Clock, Test, and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7 - Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8 - Pinout by Ball Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9 - Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10 - Possible Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11 - Formation of the Reassembly Circular Buffer Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12 - Fields within the SDT Reassembly Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 13 - Operation of Correction/Detection State Machine in Correction State . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 14 - Operation of Correction/Detection State Machine in Detection State . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine. . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 16 - Examples of Operation of the UDT Fast Sequence Number Processing State Machine . . . . . . . . . . . 75
Table 17 - Operation of SDT Fast Sequence Number Processing State Machine. . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 18 - Examples of Operation of SDT Fast Sequence Number Processing State Machine . . . . . . . . . . . . . . 77
Table 19 - Formation of SDT Reassembly Circular Buffer Base Addresses to External Memory . . . . . . . . . . . . . 82
Table 20 - Sample Gapping Circuitry Calculation (N = 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 21 - Center Frequency and Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 22 - Relevant Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 23 - Minimum Input Wander and Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 24 - Maximum Allowed Intrinsic Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 25 - Internal Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 26 - Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 27 - Chip Wide Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 28 - Main Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 29 - Low Address Word Indirection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 30 - High Address Indirection Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 31 - Indirection Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 32 - Main Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 33 - MT90528 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 34 - TX_SAR Pointer Table Base Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 35 - Data TX_SAR Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 36 - Data TX_SAR Write Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 37 - Data TX_SAR Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 38 - Data TX_SAR Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 39 - Data Cell Generation Time Out Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 40 - Data TX_SAR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 41 - TX_SAR Master Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 42 - UDT Reassembly Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 43 - UDT Reassembly Service Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 44 - UDT Reassembly Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 45 - UDT Reassembly Cell Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 46 - Data RX_SAR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 47 - Data RX_SAR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 48 - Data RX_SAR Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

MT90528

Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 49 - Data RX_SAR Write Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 50 - Data RX_SAR Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 51 - Data RX_SAR Cell Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 52 - SDT Reassembly Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 53 - SDT Reassembly Service Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 54 - SDT Reassembly Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 55 - SDT Reassembly Cell Counter Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 56 - SDT Reassembly Cell Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 57 - MIB Timeout Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 58 - MIB Timeout Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 59 - MIB Timeout Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 60 - Timeout Configuration Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 61 - UTOPIA Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 62 - UTOPIA Number of Concatenated Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 63 - LUT Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 64 - VC Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 65 - VC Match Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 66 - VP Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 67 - VP Match Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 68 - UTOPIA Parity Mismatches Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 69 - UTOPIA FIFO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 70 - UTOPIA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 71 - UTOPIA Service Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 72 - UTOPIA Incoming Cell Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 73 - UDT VCI for Port p (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 74 - UDT VPI for Port p (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 75 - Clock Management Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 76 - External PLL Clock Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 77 - Clocking Configuration Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 78 - Clocking Phase Accumulator Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 79 - Clocking DCO Difference Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 80 - SRTS FIFO Status Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 81 - PLL Enable Register (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 82 - Main TDM Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 83 - Main TDM Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 84 - TDM Control Register 1 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 85 - TDM Control Register 2 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 86 - TDM Control Register 3 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 87 - TDM Control Register 4 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 88 - TDM Control Register 5 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 89 - TDM Control Register 6 (one per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 90 - Memory Arbiter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 91 - Parity Error Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 92 - Intel Microprocessor Interface Timing - Write Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 93 - Motorola Microprocessor Interface Timing - Read Cycle Parameters. . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 94 - Motorola Microprocessor Interface Timing - Write Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 95 - External Memory Interface Timing - Read Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 96 - External Memory Interface Timing - Write Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Электронный компонент: MT90528AG

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