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PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
NJ8820
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
2
V
SS
Input voltage
Open drain outputs, pins 3 and 13
All other pins
Storage temperature
Storage temperature
2
05V to 7V
7V
V
SS
2
03V to V
DD
1
03V
2
65
C to
1
150
C
(DG package, NJ8820MA)
2
55
C to 1125
C
(DP and MP packages, NJ8820)
PROGRAM
ENABLE (PE)
OSC IN
OSC OUT
D0
D1
D2
D3
F
IN
V
DD
V
SS
LATCH 1
LATCH 2
LATCH 3
`M' COUNTER
(10 BITS)
CONTROL LOGIC
LATCH 4
LATCH 5
`A' COUNTER
(7 BITS)
FREQUENCY/
PHASE
DETECTOR
V
SS
PDA
PDB
LOCK DETECT (LD)
MODULUS
CONTROL
OUTPUT (MC)
RB CH
15 16 17
f
v
REFERENCE COUNTER
(11BITS)
LATCH 6
LATCH 7
LATCH 8
4
2
SAMPLE/HOLD
PHASE
DETECTOR
f
r
PULSE
DETECT
SEQUENCE
COUNTER
DS0 DS1 DS2
14
7
8
9
10
11
12
4
6
5
TO
INTERNAL
LATCHES
MEMORY ENABLE
(ME)
DATA SELECT
OUTPUTS
19 20
13
1
2
3
18
DATA
INPUTS
NJ8820
FREQUENCY SYNTHESISER (PROM INTERFACE)
Fig.1 Pin connections - top view
The NJ8820 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable `M' counter,
7-bit programmable `A' counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words read from an external
memory, with the necessary timing signals generated internally.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8820 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of 230
C to 170
C. The NJ8820MA is available only in
Ceramic DIL package with operating temperature range of
2
40
C to 185
C.
ORDERING INFORMATION
NJ8820 BA DP Plastic DIL Package
NJ8820 BA MP Miniature Plastic DIL Package
NJ8820 MA DG Ceramic DIL Package
FEATURES
s
Low Power Consumption
s
Direct Interface to ROM or PROM
s
High Performance Sample and Hold Phase Detector
s
>10MHz Input Frequency
Fig.2 Block diagram
CH
RB
MC
DS2
DS1
DS0
PE
ME
D3
D2
PDA
PDB
LD
F
IN
V
SS
V
DD
OSC IN
OSC OUT
D0
D1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NJ8820
DS3277-1.2
DP20, MP20,
DG20
NJ8820
f
osc
, f
F
IN
= 10MHz
f
osc
, f
F
IN
= 10MHz
I
SINK
= 4mA
I
SOURCE
= 1mA
I
SINK
= 2mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SINK
= 4mA
I
SOURCE
= 5mA
I
SINK
= 5mA
TTL compatible
See note 1
V
BIAS
= self-bias point of PE
(nominally V
DD
/2)
mA
mA
V
V
V
V
V
V
V
V
V
V
A
V
V
V
55
15
04
7
04
04
04
7
04
6
01
075
Supply current
OUTPUT LEVELS
Memory Enable Output (ME)
Low level
Open drain pull-up voltage
Data Select Outputs (DS0-DS2)
High level
Low level
Modulus Control Output (MC)
High level
Low level
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
High level
Low level
3-state leakage current
INPUT LEVELS
Data Inputs (D0-D3)
High level
Low level
Program Enable Input (PE)
Trigger level
46
46
46
425
V
BIAS
6
100mV
2
ELECTRICAL CHARACTERISTICS AT V
DD
= 5V
Test conditions unless otherwise stated:
V
DD
V
SS
=5V
05V. Temperature range NJ8820 BA: 30
C to +70
C; NJ8820 MA: 40
C to +85
C
DC Characteristics
Value
Typ.
Max.
Characteristic
Min.
35
07
Units
Conditions
0 to 5V
square
wave
AC Characteristics
Value
Typ.
Max.
Characteristic
Min.
Units
Conditions
mVRMS
MHz
ns
s
s
ns
ns
k
nF
k
V/Rad
s
50
1
5
F
IN
and OSC IN input level
Max. operating frequency, f
F
IN
and f
osc
Propagation delay, clock to MC
PE pulse length, t
W
Data set-up time, t
DS
Data hold time, t
DH
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Output resistance, PDA
Digital phase detector gain
Power supply rise time
200
106
5
1
10
5
100
30
500
04
10MHz AC-coupled sinewave
Input squarewave V
DD
to V
SS
,
See note 5.
See note 2.
Pulse to V
SS
or V
DD
.
See note 3.
10% to 90%, see note 4.
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5
s, typically.
4. To ensure correct operation of power-on programming.
5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
NJ8820
PIN DESCRIPTIONS
Name
Description
Analog output from the sample and hold phase comparator for use as a `fine' error signal. Output at
(V
DD
2
V
SS
)/2 when the system is in lock. Voltage increases as f
v
phase lead increases; voltage
decreases as f
r
phase lead increases. Output is linear over only a narrow phase window, determined
by gain (programmed by RB).
Three-state output from the phase/frequency detector for use as a `coarse' error signal.
f
v
.
f
r
or f
v
leading: positive pulses with respect to the bias point V
BIAS
f
v
, f
r
or f
r
leading: negative pulses with respect to the bias point V
BIAS
f
v
= f
r
and phase error within PDA window: high impedance.
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when
a full logic swing is available, may be DC-coupled.
Negative supply (ground).
Positive supply.
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.
Information on these inputs is transferred to the internal data latches during the appropriate data read
time slot. D3 is MSB, D0 is LSB.
An open drain output for use in controlling the power supply to an external ROM or PROM. ME is low
during the data read period and high impedance at other times.
A positive or negative pulse or edge AC-coupled into this pin initiates the single-shot data read
procedure. Grounding this pin repeats the data read procedure in a cyclic manner.
Internally generated three-state data select outputs, which may be used to address external memory.
Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning
of a count cycle and will remain low until the `A' counter completes its cycle. MC then goes high and
remains high until the `M' counter completes its cycle, at which point both `A' and `M' counters are reset.
This gives a total division ratio of
MP1A, where P and P11 represent the dual-modulus prescaler
values. The program range of the `A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the `M' counter is 8-1023
and, for correct operation,
M>A. Where every possible channel is required, the minimum total division
ratio should be
P
2
2
P.
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and V
SS
.
An external hold capacitor should be connected between this pin and V
SS
.
PDA
PDB
LD
F
IN
V
SS
V
DD
OSC IN/
OSC OUT
D0-D3
ME
PE
DS0-DS2
MC
RB
CH
3
Pin no.
1
2
3
4
5
6
7, 8
9,10, 11, 12
13
14
15, 16, 17
18
19
20
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
INPUT LEVEL (V RMS)
02 04 06 08 10 12 14 16
SUPPLY CURRENT (mA)
8
7
6
5
4
3
2
1
V
DD
= 5V
F
IN
= LOW FREQUENCY
0V TO 5V SQUARE WAVE
10MHz
1MHz
V
DD
= 5V
OSC IN, F
IN
= 0V TO 5V SQUARE WAVE
F
IN
OSC IN
INPUT FREQUENCY (MHz)
1 2 3 4 5 6 7 8 9 10
SUPPLY CURRENT (mA)
20
15
10
05
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO
F
IN
AND OSC IN
NJ8820
PROGRAMMING
Program information can be obtained from an external
ROM or PROM under the control of the NJ8820. Twenty-eight
data bits are required per channel arranged as eight 4-bit
words leaving four redundant bits, two of which are available
on the data bus driving the data transfer time slot and may be
used for external control purposes. A suitable PROM would be
the 74S287, giving up to 32 channel capability as shown in Fig.
5. Note that the choice of PNP transistor and supply bypass
capacitor on the ROM should be such that the ROM will power
up in time: for example, at 10MHz oscillator frequency, the
ROM must be powered up in less than 25
s.
Reading this data is normally done in single shot mode, with
the data read cycle started by either a positive or negative
pulse on the program enable (PE) pin. The data read cycle is
generated from a program clock at 1/64 of the reference
oscillator frequency. A memory enable signal (ME) is supplied
to allow power-down of the ROM when it is not in use. Data
select outputs (DS0-DS2) remain in a high impedance state
when the program cycle is completed to allow the address bus
to be used for other functions if desired. The data map, data
read cycle and timing diagram are shown in Figs. 6 to 8. Data
is latched internally during the portions of the program cycle
shown shaded in Fig. 7 and all data is transferred to the
counters and latched during the data transfer time slot.
Alternatively, the PE pin may be grounded, causing the data
read cycle to repeat cyclically to allow continuous up-dating of
the program information. In this mode, external memory will be
enabled continuously (ME low) and the data read cycle will
repeat every sixteen cycles of the internal program clock, i.e.
every 1024/f
osc
seconds. This programming method is not
recommended because the higher power consumption and
the possibilities of noise into the loop from the digital data lines.
Power-on Programming
On power-up, the data read cycle is automatically initiated,
making it unnecessary to provide a PE pulse. The circuit
detects the power supply rising above a threshold point
(nominally 15V) and, after an internally generated delay to
allow the supply to rise fully, the circuit is programmed in the
normal way. This delay is generated by counting reference
oscillator pulses and is therefore dependent on the crystal
used. The delay consists of 53248 reference oscillator cycles,
giving a delay of about 5ms at 10MHz.
To ensure correct operation of this function, the power
supply rise time should be less than 5ms (at 10MHz), rising
smoothly through the threshold point.
Fig. 5 Programming via PROM
DS0
0
1
0
1
0
1
0
1
D3
M1
M5
M9
A3
-
R3
R7
-
D2
M0
M4
M8
A2
A6
R2
R6
R10
D1
-
M3
M7
A1
A5
R1
R5
R9
D0
-
M2
M6
A0
A4
R0
R4
R8
DS1
0
0
1
1
0
0
1
1
DS2
0
0
0
0
1
1
1
1
WORD
1
2
3
4
5
6
7
8
Fig. 6 Data map
4
DS2
DS1
DS0
PE
ME
D3
D2
D0
D1
20
19
18
17
16
15
14
13
12
11
NJ8820
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
10
9
74S287
1
2
3
4
5
6
7
8
A4-A7
(CHANNEL SWITCH)
01
10
100k
1
5V
15k
C1
47p
C2B
22p
C2A
22p
C1
>
C2A
1
C2B
1
...
NJ8820
4 PROGRAM CLOCK
CYCLES FROM SETTLING
WORD
1
WORD
2
WORD
3
WORD
4
WORD
5
WORD
6
WORD
7
WORD
8
DATA
TRANSFER
DATA
TRANSFER
ON 2VE
CYCLE OF
PROGRAM
CLOCK
PROGRAM
CLOCK
PE
ME
DS0
DS1
DS2
Fig.7 Data selection
PHASE COMPARATORS
The digital phase/frequency detector drives a three-state
output, PDB, which provides a `coarse' error signal to enable
fast switching between channels. The PDB output is active
until the phase error is within the sample and hold phase
detector, PDA, window, when PDB becomes high impedance.
Phase-lock is indicated at this point by a low level on LD. The
sample and hold phase detector provides a `fine' error signal
to give further phase adjustment and to hold the loop in lock.
An internally generated ramp, controlled by the digital
output from both the reference and main divider chains, is
sampled at the reference frequency to give the `fine' error
signal, PDA. When in phase lock, this output would be typically
at (V
DD
2
V
SS
)/2 and any offset from this would be proportional
to phase error. The relationship between this offset and the
phase error is the phase comparator gain, which is
programmable with an external resistor, RB. An internal 50pF
capacitor is used in the sample and hold comparator.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between pin 8 (OSC OUT) and the other components. A value
of 22k
is advised.
PROGRAMMING/POWER UP
Data and signal input pins should not have input applied to
them prior to the application of V
DD
, as otherwise latch-up may
occur.
5
Fig.8 Timing diagram
t
W
(PE INTERNAL)
t
DS
t
DH
(DATA - INTERNAL
MODE)
PE
DS0
D0 - D3
NJ8820
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information
and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES
FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07
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JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
NORTH AMERICA Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023.
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UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (0793) 518510 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
GEC Plessey Semiconductors 1992
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I
2
C components conveys a licence under the Philips I
2
C Patent rights to use these components in and I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
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