SP5510S
1
8
MP16
16
9
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
I/O PORT P7
*
I/O PORT P6
I/O PORT P5
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
NC
P3 OUTPUT PORT/ADD SELECT
I/O PORT P4
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
I/O PORT P7
*
I/O PORT P6
I/O PORT P5
I/O PORT P4
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
P0 OUTPUT PORT
P1 OUTPUT PORT
P2 OUTPUT PORT
P3 OUTPUT PORT/ADD SELECT
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SP5510
DP18
= Logic level I/O port
*
= 3-bit ADC input
The SP5510 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I
2
C BUS format. The device has four addressable current-
limited output ports (P0-P3) and four bi-directional open-
collector ports (P4-P7), one of which (P6) is also a 3-bit 5-level
ADC input. The information on these ports can be read via the
I
2
C BUS. The SP5510S is a variant in a 16-lead miniature
plastic package, without P0-P2 but functionally identical in
other respects.
Both variants have one fixed I
2
C BUS address and three
programmable addresses, allowing two or more synthesisers
to be used in a system.
FEATURES
s
Complete 13GHz Single Chip System
s
Programmable via the I
2
C BUS
s
Low Power Consumption (215mW Typ.)
s
Low Radiation
s
Phase Lock Detector
s
Varactor Drive Amp Disable
s
8 Controllable Outputs, 4 Bi-directional(SP5510)
s
5 Controllable Outputs, 4 Bi-directional (SP5510S)
s
5-Level ADC
s
Variable I
2
C BUS Address for Picture in Picture TV
s
ESD Protection
*
*
Normal ESD handling precautions should be observed.
APPLICATIONS
s
Cable Tuning Systems
s
VCRs
SP5510
1.3GHz Bidirectional I
2
C BUS Controlled Synthesiser
DS2184
ISSUE 4.2
November 2001
Ordering Information
SP5510G/KG/DPAS (Tubes)
(18 lead Dual-in-line plastic package)
SP5510GS/KG/MPAS (Tubes)
SP5510GS/KG/MPAD (Tape & Reel)
(16 lead miniature plastic package)
Fig. 1 Pin connections top view
2
SP5510
ELECTRICAL CHARACTERISTICS
T
AMB
= -10
C to +80
C, V
CC
= +45V to +55V. All pin references are to the SP5510 (DP18 package).
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient
temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Supply current
Prescaler input voltage
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
SDA
Output voltage
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
Output Ports
P0-P3 sink current (see note 1)
P0-P3 leakage current (see note 1)
P4-P7 sink current
P4-P7 leakage current
Input Ports
P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low
Typ.
Value
Conditions
Characteristic
Pin
14
15,16
15,16
4,5
4,5
4,5
4,5
4,5
4
1
1
1
18
2
10-13
10-13
6-9
6-9
10
10
6,8,9
6,8,9
7
7
125
30
3
0
500
10
750
07
10
27
43
50
2
50
170
400
40
1
53
300
300
55
15
10
-10
10
04
5
200
15
10
10
+10
-
10
08
+10
-10
Units
Min.
Max.
mA
mVrms
mVrms
pF
V
V
A
A
A
V
A
A
nA
mV p-p
mA
A
mA
A
A
A
V
V
A
A
V
CC
= 5V
50MHz to 1GHz
13GHz, see Fig. 5
Input voltage = V
CC
Input voltage = 0V
When V
CC
= 0V
Sink current = 3mA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 18 = 07V
Parallel resonant crystal (note 2)
V
OUT
= 12V
V
OUT
= 132V
V
OUT
= 07V
V
OUT
= 132V
V pin 10 = 132V
V pin 10 = 0V
See Table 3 for ADC levels
NOTES
1. Ports P0-P2 not present on the SP5510S.
2. The maximum resistance quoted refers to all conditions, including start-up.
3
SP5510
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V
EE
and pin 3 at 0V. Pin references are for SP5510 (DP18 package)
Supply voltage
RF input voltage
Port voltage
Total port output current
RF input DC offset
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
Storage temperature
Junction temperature
DP18 thermal resistance, chip-to-ambient
DP18 thermal resistance, chip-to-case
MP16 thermal resistance, chip-to-ambient
MP16 thermal resistance, chip-to-case
Power consumption at 55V
Conditions
Parameter
14
15,16
6-13
6-9
10-13
6-13
15-16
1
18
2
4,5
Pin
Max.
Min.
Units
7
25
14
6
14
50
V
CC
+03
V
CC
+03
V
CC
+03
V
CC
+03
V
CC
+03
55
+150
+150
78
24
111
41
321
Value
-03
-03
-03
-03
-03
-03
-03
-03
-03
-03
-55
V
V p-p
V
V
V
mA
V
V
V
V
V
V
C
C
C/W
C/W
C/W
C/W
mW
Port in off state
Port in on state
Port in on state
With V
CC
applied
V
CC
not applied
Fig. 2 Block diagram. (Ports P0-P2 not present on SP5510S)
48
PRESCALER
RF IN
RF IN
SCL
SDA
I
2
C BUS
TRANSCEIVER
PRE
AMP
15 BIT
PROGRAMMABLE
DIVIDER
15 BIT DIVIDER
RATIO LATCH
8-BIT LATCH
PORT
INFORMATION
DRIVE
OUTPUT
P0 P1 P2 P3 P4 P5 P6 P7
PHASE
COMP
F
F
DIV
CHARGE
PUMP
F
COMP
DIVIDER
4512
OSC
4MHz
V
CC
Q1
CRYSTAL
Q2
CHARGE
PUMP
V
EE
POWER ON
DETECTOR
ADDRESS
SELECT
CONTROL
DATA
LATCH
LOGIC
OS
T0 CP
3 TTL
LEVEL
COMP
3-BIT
ADC
LOCK
DETECTOR
T1
4
SP5510
FUNCTIONAL DESCRIPTION
The SP5510 is programmed from an I
2
C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I
2
C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode).
The Tables in Fig. 3 illustrate the format of the data. The
device can be programmed to respond to several addresses,
which enables the use of more than one synthesiser in an I
2
C
BUS system. Table 4 shows how the address is selected by
applying a voltage to P3. The LSB of the address Byte (R/
W) sets the device into read mode if it is high and write mode
if it is low. When the SP5510 receives a correct address
Byte it pulls the SDA line low during the acknowledge period
and during following acknowledge periods after further data
Bytes are programmed. When the SP5510 is programmed
into the read mode the controlling device accepting the data
must pull down the SDA line during the following acknowl-
edge period to read another status Byte.
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 2+3 select the
synthesised frequency while Bytes 4+5 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to re-
address the device until an I
2
C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit
shift register and is used to control the division ratio of the 15-
bit programmable divider which is preceded by a divide-by-
8 prescaler and amplifier to give excellent sensitivity at the
local oscillator input; see Fig 5. The input impedance is
shown in Figs. 7 and 8.
The programmed frequency can be calculated by multi-
plying the programmed division ratio by 8 times the compari-
son frequency F
COMP
.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the pro-
grammable divider is frequency and phase locked to the
comparison frequency.
The reference frequency may be generated by an exter-
nal source capacitively coupled into pin 2 or provided by an
on-chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 78125kHz when
a 4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for
170
A and
a logic 0 for
50
A, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier's output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a
logic 1 connects F
COMP
to P6 and F
DIV
to P7.
Byte 5 programs the output ports P0-P7, a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read
from the device on the SDA line takes the form shown in
Table 2.
Bit 1 (POR) is the power on reset indicator and is set to a
logic 1 if the power supply to the device has dropped below
a nominal 3V and the programmed information lost (e.g.,
when the device is initially turned on). The POR is set to 0
when the read sequence is terminated by a stop command.
The outputs are all set to high impedance when the device
is initially powered up. Bit 2 (FL) indicates whether the device
is phase locked, a logic 1 is present if the device is locked and
a logic 0 if the device is unlocked.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5 and P4 respectively. A logic 0 indicates a low level
and a logic 1 a high level. If the ports are to be used as inputs
they should be programmed to a high impedance state
(logic1). These inputs will then respond to data complying
with standard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0)
combine to give the output of the 5-level ADC.
The 5-level ADC can be used to feed AFC information to
the microprocessor from the IF section of the television, as
illustrated in Fig. 4.
5
SP5510
MSB
1
0
2
7
1
P7
Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
Table 1 Write data format (MSB transmitted first)
Table 2 Read data format
Table 4 Address selection
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
1
2
14
2
6
CP
P6
0
2
13
2
5
T1
P5
0
2
12
2
4
T0
P4
0
2
11
2
3
1
P3
MA0
2
9
2
1
1
P1
*
MA1
2
10
2
2
1
P2
*
A
A
A
A
A
LSB
0
2
8
2
0
OS
P0
*
Byte 1
Byte 2
Address
Status byte
1
FL
0
I2
0
I1
0
I0
MA0
A1
MA1
A2
A
A
1
POR
1
A0
NOTE
*
Don't care condition on SP5510S.
Fig. 3 Data formats
MA0
0
1
0
1
MA1
0
0
1
1
Voltage input to P3
0V to 02V
CC
Always valid
03V
CC
to 07V
CC
08V
CC
to 132V
Voltage input to P6
06V
CC
to 132V
045V
CC
to 06V
CC
03V
CC
to 045V
CC
015V
CC
to 03V
CC
0V
to 015V
CC
A1
0
1
1
0
0
A2
1
0
0
0
0
A0
0
1
0
1
0
Table 3 ADC levels
A
: Acknowledge bit
MA1, MA0
: Variable address bits (see Table 4)
CP
: Charge Pump current select
T1
: Test mode selection
T0
: Charge pump disable
OS
: Varactor drive Output disable Switch
P7, P6, P5, P4,
: Control output port states
P3, P2
*
, P1
*
, P0
*
POR
: Power On Reset indicator
FL
: Phase lock detect flag
I2, I1, I0
: Digital information from ports P7, P5 and P4 respectively
A2, A1, A0
: 5-level ADC data from P6 (see Table 3)
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