Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink's obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
ADVANCE INFORMATION
FEBRUARY 1997
D.S. 3920 3.3
SP5610
1.3GHz BIDIRECTIONAL I
2
C BUS CONTROLLED SYNTHESISER
(Supersedes edition in 1996 Media IC Handbook, HB45991.0)
The SP5610 is a single chip frequency synthesiser
designed for TV tuning systems. Control data is entered in the
standard I
2
C BUS format. The device contains 1 addressable
current limited output and 4 addressable bidirectional open
collector ports one of which is a 3 bit ADC. The information on
these ports can be read via the I
2
C BUS. The device has one
fixed I
2
C BUS address and 3 programmable addresses,
programmed by applying a specific input voltage to the P3
current limited output. This enables 2 or more synthesisers to
be used in a system.
FEATURES
J
Complete 1.3GHz Single chip System
J
High Sensitivity RF Inputs
J
Programmable via I
2
C Bus
J
On Chip oscillator with 1k
W
negative resistance
J
Low power consumption (5V, 20mA)
J
Low Radiation
J
Phase Lock Detector
J
Varactor Drive Amp Disable
J
5 Controllable Outputs
J
5 Level ADC
J
Variable I
2
C BUS Address For Multi Tuner
Applications
J
ESD Protection *
J
Switchable
512/1024 Reference Divider
J
Pin and Function Compatible with SP5510S
[
* Normal ESD handling procedures should be observed.
[
The SP5510S does not have a switchable
reference division ratio.
APPLICATIONS
J
Satellite TV when combined with SP4902 2.5GHz
prescaler
J
Cable Tuning Systems
J
VCR's
1
16
* = 3bit ADC input
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
[
I/O PORT P7
* I/O PORT P6
[
I/O PORT P5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[
= Logic level I/O
MP16
SP5610S
Fig. 1 Pin connections top view
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
NC
P3 OUTPUT PORT/
ADD SELECT
I/O PORT P4
[
ORDERING INFORMATION
SP5610S/KG/MPAS (Tubes)
SP5610S/KG/MPAD (Tape and Reel)
SP5610
2
ELECTRICAL CHARACTERISTICS
T
amb
= 40
C to
)
85
C, V
CC
=
)
4.5V to
)
5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristic
Pin
Value
Units
Conditions
Characteristic
Pin
Min
Typ
Max
Units
Conditions
Supply current
12
20
27
mA
V
CC
= 4.5V to 5.5V
Prescaler Input Voltage
13, 14
12.5
300
mVrms
50MHz to 1.3GHz sinewave
See Fig. 5.
Prescaler
Input Impedance
Input Capacitance
13, 14
50
2
W
pF
SDA, SCL Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Leakage Current
4, 5
4, 5
4, 5
4, 5
4, 5
3
0
5.5
1.5
10
10
10
V
V
m
A
m
A
m
A
Input Voltage = V
CC
Input Voltage = 0V
When V
CC
= 0V
SDA
Output Voltage
4
0.4
V
I
sink
= 3mA
Charge Pump Current Low
1
"
50
m
A
Byte 4 Bit 2 = 0, Pin 1 = 2V
Charge Pump Current High
1
"
170
m
A
Byte 4 Bit 2 = 1, Pin 1 = 2V
Charge Pump Output Leakage
Current
1
"
5
nA
Byte 4 Bit 4 = 1, Pin 1 = 2V
Charge Pump Drive Output
Current
16
500
m
A
V
pin
16 = 0.7V
Charge Pump Amplifier Gain
6400
Recommended Crystal series
Resistance
10
200
W
``Parallel Resonant" crystal.
Resistance specified is max
under all conditions
Crystal Oscillator Drive Level
2
80
mVpp
Crystal Oscillator Negative
Resistance
2
750
1000
W
External Reference Input
Frequency
2
2
8
MHz
AC coupled sinewave
External Reference Input
amplitude
2
70
200
mVrms
AC coupled sinewave
Output Ports
P3 Sink Current
10
0.7
1
1.5
mA
V
out
= 12V
P3 Leakage Current
10
10
m
A
V
out
= 13.2V
P4P7 Sink Current
96
10
mA
V
out
= 0.7V
P4P7 Leakage Current
96
10
m
A
V
out
= 13.2V
Input Ports
P3 Input Current High
10
+10
m
A
V
pin 10
= 13.2V
P3 Input Current Low
10
10
m
A
V
pin 10
= 0V
P4,P5,P7 Input Voltage Low
9,8,6
0.8
V
P4,P5,P7 Input Voltage High
9,8,6
2.7
V
P6 Input Current High
7
+10
m
A
See Table 3 for ADC Levels
P6 Input Current Low
7
10
m
A
SP5610
3
RF IN
PRE
AMP
PRESCALER
PROGRAMMABLE
15 BIT
DIVIDER
F
PD
PHASE
COMP
F
POWER
ON DET
TRANSCEIVER
I
2
C BUS
SELECT
ADDRESS
ADC
3 BIT
LEVEL
COMP
3 TTL
15 BIT LATCH
DIVIDE
RATIO
5 BIT LATCH
PORT
INFORMATION
DET
LOCK
CONTROL
DATA
LATCHES
AND CONTROL
LOGIC
PORT OUTPUT DRIVERS
F
COMP
DIVIDER
OSC
Q 1
CRYSTAL
PUMP
CHARGE
PUMP
CHARGE
F
L
DOWN
UP
CP
TO
OS
Q 2
VARICAP
DRIVE/
OUT
V
CC
P3
P4
P5
P6
P7
SCL
SDA
Fig 2. Block diagram
POR
4
1
4
512/1024
V
EE
13
14
5
4
2
3
1
16
12
15
10
9
8
7
6
8
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