Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink's obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
ADVANCE INFORMATION
FEBRUARY 1994
D.S. 3931 1.5
SP5654
2.7GHz 3WIRE BUS CONTROLLED SYNTHESISER
The SP5654 is a single chip frequency synthesiser
designed for satellite TV tuning systems. It is a programming
variant of the SP5655 allowing the design of one tuner with
either I
2
C bus or a 3wire bus format depending on which
device is inserted. The device when used with a varicap tuner,
forms a complete phase locked loop tuning system. The circuit
consists of a divideby16 prescaler with its own preamplifier
and a 14/15 bit programmable divider controlled by a serially
loaded data register. Four independently programmable open
collector outputs are included. The device contains five modes
of operation each compatible with Toshiba 18 and 19 bit
software.
The comparison frequencies are obtained from a crystal
controlled onchip oscillator typically operating at 4MHz. The
comparator has a charge pump output amplifier stage around
which feedback may be applied. Only one external transistor
is required for varicap line driving.
FEATURES
J
Complete 2.7GHz Single Chip System
J
High Sensitivity RF Input
J
Low power Consumption (5V, 30mA)
J
OnChip Oscillator with 1k
W
negative resistance
J
On chip oscillator startup circuit
J
Programming Compatible with Toshiba TD6380,
TD6381 and TD6382#
J
Pin compatible with SP5655#
J
5 Modes of Operation with different step sizes,
see Table 1; each selectable with 18 or 19 bit
transmission length.
J
Single Port 18/19 Bit Serial Data Entry
J
Auto select for Data transmission length, 18 or 19
J
Low Radiation
J
Phase Lock Detector
J
Varactor Drive Amp Disable
J
Charge Pump Disable
J
Four Controllable Outputs
J
ESD Protection
[
# See notes on pin and programming compatibility
[
Normal ESD handling procedures should be
observed.
Fig. 1 Pin connections top view
1
16
1
16
CHARGE PUMP
CRYSTAL
MODE SELECT
DATA
CLOCK
PORT P3
PORT P2
PORT P1
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
LOCK
ENABLE
PORT P0
S
P
5
6
5
4
MP16
APPLICATIONS
J
Satellite TV
J
High IF Cable Tuning Systems
ORDERING INFORMATION
SP5654/KG/MPAS (Tubes)
SP5654/KG/MPAD (Tape and Reel)
SP5654
2
ELECTRICAL CHARACTERISTICS
T
amb
= 20
C to
)
80
C, V
CC
=
)
4.5V to
)
5.5V. Reference frequency =4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristics
Symbol
Pin
Value
Units
Conditions
Characteristics
Symbol
Pin
Min
Typ
Max
Units
Conditions
Supply current
I
CC
12
30
40
mA
Typical applies to V
CC
= 5V
Prescaler Input Voltage
13, 14
12.5
300
mV
rms
300MHz to 2GHz sinewave.
40
300
mV
rms
120MHz & 2.7GHz See Fig.6.
Prescaler Input Impedance
Input Capacitance
13, 14
50
2
W
pF
Data Clock and Enable
High Level Input Voltage
4, 5, 10
3
V
CC
V
Low Level Input Voltage
4, 5, 10
0
1.5
V
High Level Input Current
4, 5, 10
10
m
A
V
IN
=5.5V V
CC
=5.5V
Low Level Input Current
4, 5, 10
10
m
A
V
IN
=0V V
CC
=5.5V
Input Hysteresis
4, 5, 10
0.8
V
Clock Rate
5
500
kHz
Timing Information
Data Setup Time
t
SU
4
300
ns
See Fig.4
Data Hold Time
t
HD
4
600
ns
See Fig. 4
Enable Setup time
t
ES
10
300
ns
See Fig. 4
Enable Hold Time
t
EH
10
600
ns
See Fig. 4
ClocktoEnable Time
t
CE
10
300
ns
See Fig. 4
Clock Low Period
t
LO
5
600
ns
See Fig. 4
Clock High Period
t
HI
5
600
ns
See Fig. 4
Mode Select
High Level Input Current
3
700
m
A
V
IN
=5.5V V
CC
=5.5V
Low Level Input Current
3
700
m
A
V
IN
=0V V
CC
=5.5V
Charge Pump Output Current
1
150
m
A
V pin 1 = 2.0V, device `out of
lock'
Charge Pump Output Current
1
50
m
A
V pin 1 = 2.0V, device `locked'
Charge Pump Output
Leakage Current
1
5
nA
V pin 1 = 2.0V, charge pump
disabled
Charge Pump Drive Output
Current
16
1
mA
V pin 16 = 0.7V
Charge Pump Amplifier Gain
6400
Pin 18 Current = 100
m
A
Oscillator Temperature
Stability
2
ppm/
C
Oscillator Stability with
Supply Voltage
2
ppm/V
Recommended Crystal
Series Resistance
10
200
W
``Parallel resonant crystal." Fig-
ure quoted is under all condi-
tions including start up.
Crystal Oscillator Drive Level
2
80
mV pp
Crystal Oscillator Negative
Resistance
2
750
W
Includes temperature and
process tolerances
Reference Crystal Frequency
2
4
8
MHz
External Reference input
Frequency
2
2
16
MHz
AC coupled sinewave
External Reference input
Amplitude
2
400
1000
mV
pp
AC coupled sinewave
SP5654
3
ELECTRICAL CHARACTERISTICS (cont.)
T
amb
= 20
C to
)
80
C, V
CC
=
)
4.5V to
)
5.5V. Reference frequency =4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristics
Conditions
Units
Value
Pin
Symbol
Characteristics
Conditions
Units
Max
Typ
Min
Pin
Symbol
Ports and Lock output
Sink Current
69, 11
10
mA
V
out
=0.7V
Lock Leakage Current
11
10
m
A
V
out
=V
CC
Port Leakage Current
69
10
m
A
V
out
=13.2V
Varactor Drive Amp Disable
10
50
m
A
V
pin
10 < 0V. Current sourced
from device
Charge Pump Disable
4
50
m
A
V
pin
4 < 0V. Current sourced
from device
Test Mode Enable
5
50
m
A
V
pin
5 < 0V. Current sourced
from device. See Table 2
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V
EE
=0V
Parameter
Pin
Value
Units
Conditions
Parameter
Pin
Min
Max
Units
Conditions
Supply voltage
12
0.3
7
V
Prescaler input voltage
13, 14
2.5
Vpp
Prescaler DC offset
13, 14
0.3
V
CC
+0.3
V
Port voltage
69
0.3
14
V
Port in off state
0.3
6
V
Port in on state
Total port output current
69
50
mA
Loop amplifier DC offset
1, 16
0.3
V
CC
+0.3
V
Crystal oscillator DC offset
2
0.3
V
CC
+0.3
V
3wire bus inputs
4, 5, 10
0.7
6
V
Mode select input
3
0.3
V
CC
+0.3
V
Lock output voltage
11
0.3
V
CC
+0.3
V
Lock output current
11
15
mA
Storage temperature
55
+150
C
Junction temperature
+150
C
MP16 thermal resistance, chiptoambient
111
C/W
MP16 thermal resistance, chiptocase
41
C/W
Power consumption
220
mW
All ports off
ESD protection
All
4
kV
MIL STD 883 TM 3015
SP5654
4
0.5
0.2
1
0
+j0.2
+j0.5
+j1
+j2
+j5
2
5
j5
j2
j1
j0.5
j0.2
FREQUENCY MARKER STEP = 500MHz
S
11
:Z
0
= 50
W
Fig. 2 Typical input impedance
X
X
X
X
X
2.6GHz
NORMALISED TO 50
W
RF
V
INPUTS
CLOCK
DATA
ENABLE
MODE
SELECT
CC
CRYSTAL
CHARGE
PUMP
DRIVE/
VARICAP
OUTPUT
V
EE
LOCK
P0
P1
P2
P3
PRE
AMP
PRESCALER
14/15 BIT
PROGRAMMABLE
DIVIDER
F
PD
F
COMP
PHASE
COMP
F
OSC
DATA
INPUT
INTERFACE
DATA
CLOCK
18/19
LATCH
CONTROL
OUTPUT
BUFFER
CHARGE
PUMP
AMP
LOCK
DETECT
CP DIS
VA DIS
Fig. 3 Block diagram
16
REFERENCE
DIVIDER
13
14
5
4
10
3
6
7
8
9
11
15
16
1
2
12
512/640/1024
/1280/2048
MODE
SELECT
SP5654
5
FUNCTIONAL DESCRIPTION
The SP5654 contains all the elements necessary, with the
exception of reference crystal, loop filter and external high
voltage transistor, to control a voltage controlled local
oscillator, so forming a PLL frequency synthesised source.
The system is controlled by a microprocessor via a
standard data, clock and enable threewire bus. The data load
consists of a single word, which contains the frequency and
port information, and is only transferred to the internal data
shift register during an enable high period. The clock is
disabled during low periods. New data words are only
accepted by the internal data buffers from the shift register on
a negative transition of the enable, so giving improved fine
tuning facility for digital AFC etc.
The device has 5 modes of operation, as defined in Table
1, and each of these modes can accept either 18bit or 19bit
data entry. The format of the data entry is shown in Fig. 4, and
consists of 4bits for port switching, plus 14/15 bits to control
the 15bit programmable divider. For 18bit data entry (4+14),
the MSB of the 15bit programmable divider is internally set to
logic `0' effectively making the divider 14bits. The device
recognises the data entry as 18bit when a falling edge at the
enable input occurs during the 18th clock period. The device
associates falling enable edges during the 19th clock period
with 19bit data entry. A falling edge at the enable input before
the 18th clock period constitutes invalid data entry to the
device.
The frequency is set by first selecting the required mode of
operation as detailed in Table 1, and then by loading the
programmable divider with the required 14/15bit divisor
word. The output of this divider, F
PD
, is fed to the phase
comparator where it is compared in phase and frequency to
the internally generated comparison frequency, F
COMP
.
The comparison frequency F
COMP
is obtained by dividing
the output of the onchip crystal controlled oscillator. The
crystal frequency generally used is 4MHz, giving an F
COMP
of
7.8125kHz in mode 4, which when multiplied back up to the LO
gives a minimum step size of 125kHz.
The programmable divider is preceded by an input RF
preamplifier and high speed low radiation prescaler. The
preamplifier is arranged to be self oscillating, so giving
excellent input sensitivity. The input impedance and sensitivity
are shown in Fig. 2 and 6 respectively.
The device contains a lock detect circuit which generates
a flag when the loop has attained lock. The `in lock' condition
is indicated by a high impedance state.
The charge pump current is initially set to
150
m
A. When
the device attains frequency lock, the charge pump current is
switched to
50
m
A, so improving the local oscillator short term
jitter.
The device also contains four general purpose open
collector output ports P0P3. These outputs are each capable
of sinking a minimum of 10mA, when the appropriate bits
P0P3 of the programming data, see Fig. 4 are set to a logic
`1'.
PIN and PROGRAMMING COMPATIBILITY
The SP5654 may be used in SP5655 applications which
require 3wire bus as opposed to I
2
C bus data format. In
SP5655 applications where the reference crystal is grounded
to pin 3, a small modification is required to ground the crystal
as shown in Fig. 5.
Appropriate connections must also be to the mode select
input (see Table 1). For each mode of operation, the SP5654
is programming and step size compatible with Toshiba
devices as shown in Table 3.
TEST FEATURES
Charge pump disable
The charge pump may be disabled by sourcing current
from the data input, i.e. by forcing a negative input voltage.
Varactor line disable
The charge pump amplifier drive output may be disabled by
sourcing current from the enable input, i.e. by forcing a
negative voltage.
Device test mode
Further test modes can be invoked by sourcing current
from the clock input, i.e. by forcing a negative input voltage.
These test modes when invoked are determined by the data
held in the P1, P2 and P3 internal registers as detailed in Table
2.
MODE
`MODE SELECT'
INPUT VOLTAGE
PROGRAMMABLE
DIVIDER BIT
LENGTH
REFERENCE
DIVIDER RATIO
*FREQUENCY
STEP SIZE
(kHz)
*MAXIMUM
OPERATING
FREQUENCY (GHz)
14 bit
15 bit
4
0.85 V
CC
V
CC
14/15
512
125
2.0479
2.7000
3
0.65 V
CC
0.75V
CC #
14/15
1280
50
0.8191
1.6383
2
OPEN CIRCUIT
14/15
1024
62.5
1.0239
2.0479
1
0.25 V
CC
0.35V
CC
[
14/15
2048
31.25
0.5119
1.0239
0
0 0.15 V
CC
14/15
640
100
1.6383
2.7000
*When used with a 4MHz crystal
# Selected by connecting a 15k
W
resistor to V
CC
[
Selected by connecting a 15k
W
resistor to V
EE
Table 1. Modes of operation
SP5654
6
Test Mode
P1
P2
P3
Test Mode Description
0
0
0
0
Charge pump down 170
m
A
1
0
0
1
Charge pump up 170
m
A
2
1
0
0
Charge pump down 50
m
A
3
1
0
1
Charge pump up 50
m
A
4
d
1
0
F
COMP
to P2; F
PD
/2 to P3;
Lock output switched to out of lock
condition
5
d
1
1
Lock output switched to inlock condition
These test modes are invoked by taking the clock input below V
EE
d=don`t care
Table 2 Test mode options
MODE
COMPATIBILITY
18 Bit Data entry
19 Bit Data entry
4
TD6380 plus
2 prescaler
TD6382 plus
4 prescaler
3
None
TD6381
2
TD6380
TD6382 plus
2 prescaler
1
None
TD6382
0
None
TD6381 plus
2 prescaler
Table 3. Programming compatibilities
FREQUENCY DATA
CLOCK
ENABLE
P0
P1
P2
P3
LSB
2
17
2
16
2
15
2
14
2
13
2
12
2
2
2
1
2
0
P0
P1
P2
P3
LSB
2
18
2
17
2
16
2
15
2
14
2
13
2
2
2
1
2
0
FREQUENCY DATA
t
ES
=Enable set up time
=Data set up time
=Data hold time
=Clocktoenable time
=Enable hold time
t
SU
t
HD
t
CE
t
EH
18BIT
19BIT
Fig. 4 Data format and timing
DATA ENTRY
DATA ENTRY
MSB IS TRANSMITTED
FIRST
MSB
MSB
CLOCK
ENABLE
DATA
t
SU
t
HD
3V
3V
1.5V
1.5V
t
CE
t
ES
t
LO
t
Hi
t
EH
3V
1.5V
=Clock low period
t
LO
t
Hi
=Clock high period
SP5654
7
S
P
5
+30V
+5V
22k
10k
47k
10n
OSCILLATOR
OUTPUT
VARICAP
INPUT
+12V
TUNER
TUNER
SWITCHING
2N3904
22k
47n
180n
4MHz
CRYSTAL
18p
CONTROL
MICRO
1n
1n
P3
P2
P1
Fig. 5 T
ypical application (step size = 100kHz)
SATELLITE
1
16
1
16
P0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
6
5
4
Fig. 6 T
ypical input sensitivity
FUNCTIONS
300
100
50
25
120
1000
2000
2700
3000
VIN (mV RMS
INTO 50
W
)
FREQUENCY (MHz)
3500
40
12.5
300
OPERATING
WINDOW
SP5654
8
v
REF
400
RF INPUTS
v
CC
DRIVE
OUTPUT
CHARGE
PUMP
170
Mode select input
Data, Clock, Enable inputs
400
VADIS
(o/p disable)
CRYSTAL
Reference oscillator
CC
V
Output ports P0P3 and lock output
OUTPUT
I/P
CC
V
67k
3k
CC
V
Fig. 7. Input/Output interface circuits
RF inputs
Loop amplifier
v
CC
20k
I/P
3k
20k
SP5654
9
SP5654
10
SP5654
11
SP5654
12
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre.
9.80/.01
(0.386/0.394)
16
SPOT REF
CHAMFER
REF
PIN 1
0.35/0.49
(0.014/0.0019)
0.69 (0.027)
MAX
MINIATURE PLASTIC DIL MP16
16 LEADS AT
1.27 (0.050)
NOM SPACING
0.10/0.25
(0.004/0.010)
1.35/1.91
(0.053/0.075)
3.80/4.00
(0.150/0.157)
5.80/6.20
(0.228/0.244)
0.25/0.51
345
(0.010/0.020)
O
0.18/0.25
(0.007/0.010)
08
O
0.41/1.27
(0.016/0.050)
NOTES
1. Controlling dimensions are inches.
2. This package outline diagram is for guidance
only. Please contact your GPS Customer
Service Center for further information.
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire United Kingdom SN2 2QW.
Tel: (01793) 518000
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017 1500 Green Hills Road,
Scotts Valley, California 950670017,
United States of America. Tel: (408) 438 2900
Fax: (408) 438 5576
This publication is issued to provide information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any
order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. The Company reserves the right to alter without proir knowledge the specification, design, or price of any product or service.
Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of
equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up
to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All
products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
E
GEC Plessey Semiconductors 1995 Publication No. D.S. 3931 Issue No. 1.5 February 1995
CUSTOMER SERVICE CENTRES
F
FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45
Fax: (1) 64 46 06 07
F
GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55
F
ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
F
JAPAN Tokyo Tel: (03) 52765501 Fax: (03) 52765510
F
NORTH AMERICA Scotts Valley, USA
Tel: (408) 438 2900 Fax: (408) 438 7023
F
SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
F
SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736
F
TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
F
UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (01793) 518510 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries worldwide.
TECHNICAL DOCUMENTATION NOT FOR RESALE. PRINTED IN UNITED KINGDOM
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I
2
C components conveys a licence under the Philips I
2
C Patent rights to use these components in and I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products
visit our Web Site at
PDF 
ZIP