SP5769
3GHz I
2
C Bus Synthesiser
DS4878 ISSUE 4.3 May 2002
Ordering Information
SP5769A/KG/MP1S (Tubes)
SP5769A/KG/MP1T (Tape and Reel)
(16 lead SOIC Package)
SP5769A/KG/QP1S (Tubes)
SP5769A/KG/QP1T (Tape and Reel)
(16 lead QSOP Package)
Features
Complete 30 GHz Single Chip System
Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
No RF Prescaler
Selectable Reference Division Ratio
Selectable Reference/Comparison Frequency Output
Selectable Charge Pump Current with 10:1 Ratio
Four Selectable I
2
C Addresses
I
2
C Fast Mode Compliant with 33V and 5V Logic
Levels
Four Switching Ports
Functional Replacement for SP5659 (except ADC)
Pin Compatible with SP5655
Power Consumption 138mW with V
CC
= 55V, all Ports off
ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
Digital Satellite and Cable Tuning Systems
Communications Systems
Description
The SP5769 is a single chip frequency synthesiser
designed for tuning systems up to 3GHz. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
size equal to the loop comparison frequency and no
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, f
REF
, or phase
comparator frequency, f
COMP
, can be switched to the REF/
COMP output providing a reference for a second
frequency synthesiser. The synthesiser is controlled via
an 1
2
C bus and is fast mode compliant. It can be hard
wired to respond to one of four addresses to enable two
or more synthesisers to be used on a common bus. The
device contains four switching ports P0 - P3.
4-BIT LATCH AND
PORT INTERFACE
4
16/17
4-BIT
COUNT
11-BIT
COUNT
15-BIT LATCH
REFERENCE
DIVIDER
REF/COMP
CRYSTAL CAP
CRYSTAL
CHARGE PUMP
DRIVE
I
2
C BUS
TRANSCEIVER
ADDRESS
SDA
SCL
RF
INPUT
P3
11
2
3
1
16
6
13
14
10
4
5
PUMP
2 BIT
4 BIT
2 BIT
3 BIT
7
8
9
P2
P1
P0
CP TEST
MODE SET
LOCK
f
PD
/2
f
PD
/2 SELECT
ENABLE/
SELECT
Figure 1 - SP5769 Block Diagram
Absolute Maximum Ratings
All voltages are referred to V
EE
= 0V
Supply voltage, V
CC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
MP16 thermal resistance
Chip to ambient,
JA
Chip to case,
JC
-3V to +7V
25Vp-p
-03 to V
CC
+03V
203 to 6V
-55
C to +125
C
+150
C
80
C/W
20
C/W
2
SP5769
Figure 2 - Pin connections - top view
MP16
SP
5769
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHARGE PUMP
CRYSTAL CAP
CRYSTAL
SDA
SCL
PORT P3/LOGLEV
PORT P2
PORT P1
DRIVE
V
EE
RF INPUT
RFINPUT
V
CC
REF/COMP
ADDRESS
PORTP0
QP16
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SP
5769
CHARGE PUMP
CRYSTAL CAP
CRYSTAL
SDA
SCL
PORT P3/LOGLEV
PORT P2
PORT P1
DRIVE
V
EE
RF INPUT
RFINPUT
V
CC
REF/COMP
ADDRESS
PORTP0
Electrical Characteristics
Test conditions (unless otherwise stated): T
AMB
= -40
C to +80
C, V
CC
= +45V to +55V. These characteristics are
guaranteed by either production test or design. They apply within the specified ambient temperature and supply
voltage ranges unless otherwise stated.
Characteristic
Conditions
Max.
Min.
Value
Typ.
Units
100MHz to 200MHz, see figure 3
200MHz to 3GHz, see figure 3
See Figure 4
5V I
2
C logic selected
33V I
2
C logic selected
5V I
2
C logic selected
33V I
2
C logic selected
Input voltage = V
CC
Input voltage = V
EE
V
CC
= V
EE
I
SINK
= 3mA
I
SINK
= 6mA
See Table 6, V
PIN1
= 2V
V
PIN1
= 2V, V
CC
= 150V, T
AMB
= 25
C
V
PIN16
= 07V
See Figure 5 for application
Sinewave coupled via 10nF blocking capacitor
Sinewave coupled via 10nF blocking capacitor
AC coupled, see Note 2
00625 to 20MHz
Enabled by bit RE = 1
SSB, within loop bandwidth, all comparison
frequencies
See Table 1
Pin
25
300
300
55
55
15
1
10
- 1 0
10
04
06
400
+ - 1 0
20
20
05
4
32767
Supply current
RF input
Input voltage
Input impedance
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
Input hysteresis
SDA output voltage
SCL clock rate
Charge pump
Output current
Output leakage
Drive output current
Crystal frequency
External reference
Input frequency
Drive level
Buffered REF/COMP
Output amplitude
Output impedance
Comparison frequency
Equivalent phase noise at
phase detector
RF division ratio
Reference division ratio
12
13,14
4,5
4
5
1
1
16
2,3
3
11
100
40
3
23
0
0
04
05
2
2
02
-148
240
20
6 3
035
250
mA
mVrms
mVrms
V
V
V
V
A
A
A
V
V
V
kHz
nA
mA
MHz
MHz
Vp-p
Vp-p
MHz
dBc/Hz
cont...
3
SP5769
Functional Description
The SP5769 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varactor tuned
local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
15-bit fully programmable divider which is of MN1A
architecture, where the dual modulus prescaler is 416/
17, the A counter is 4 bits, and the M counter is 11 bits.
The output of the programmable divider is applied to the
phase comparator where it is compared in both phase
and frequency domains with the comparison frequency.
This frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 16 ratios as detailed inTable 1.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage. The
programmable divider output f
PD
/2 can be switched to
port P0 by programming the device into test mode. The
test modes are described inTable 5.
Programming
The SP5769 is controlled by an I
2
C data bus and is
compatible with both standard and fast mode formats and
with I
2
C data generated from nominal 33V and 5V
sources. The I
2
C logic level is selected by the bi-directional
port P3/ LOGLEV. 5V logic levels are selected by
connecting P3/ LOGLEV to V
CC
or leaving it open circuit;
33V logic levels are set by connecting P3/LOGLEV to
ground. If this port is used as an input the P3 data should
be programmed to high impedance. If used as an output
only 5V logic levels can be used, in which case the logic
state imposed by the port on the input is ignored.
Data and clock are fed in on the SDA and SCL lines
respectively as defined by I
2
C bus format . The synthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the device
into write mode if it is low, and read mode if it is high.
Tables 2 and 3 illustrate the format of the data. The device
can be programmed to respond to several addresses,
which enables the use of more than one synthesiser in
an I
2
C bus system. Table 4 shows how the address is
selected by applying a voltage to the address input. When
the device receives a valid address byte, it pulls the SDA
line low during the acknowledge period, and during
following acknowledge periods after further data bytes
are received. When the device is programmed into read
mode, the controller accepting the data must be pulled
low during all status byte acknowledge periods to read
another status byte. If the controller fails to pull the SDA
line low during this period, the device generates an internal
STOP condition, which inhibits further reading.
Electrical Characteristics (continued)
2
3
0
Characteristic
V
PORT
= 07V
V
PORT
= V
CC
See Note 1
See Table 4
V
IN
= V
CC
V
IN
= V
EE
See Note 3
5V I
2
C logic level selected or open circuit
33V I
2
C logic level selected
V
IN
= V
EE
to V
CC
Conditions
Max.
Min.
Value
Units
mA
A
mA
A
V
V
A
Typ.
10
1
- 0 5
15
10
Output Ports P3 - P0
Sink current
Leakage current
Address select
Input high current
Input low current
Logic level select
Input high level
Input low level
Input current
Pin
6-9
10
6
NOTES
1. Output ports high impedance on power-up, with SDA and SCL at logic `0'.
2. If the REF/COMP output is not used, the output should be left open circuit or connected to V
CC
and disabled by setting RE = `0'.
3. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched
into high impedance (off) state.
4
SP5769
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R0
Division ratio
2
4
8
16
32
64
128
256
24
5
10
20
40
80
160
320
a byte transmission, the previous byte data is retained.
To facilitate smooth fine tuning, the frequency data bytes
are only accepted by the device after all 15 bits of
frequency data have been received, or after the generation
of a STOP condition.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 3.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic `1' if the V
CC
supply to the device has dropped
below 3V (at 25
C ), e.g. when the device is initially turned
on. The POR is reset to `0' when the read sequence is
terminated by a STOP command. When POR is set high
this indicates the programmed information may be
corrupted and the device reset to power up condition.
Bit 2 (FL) indicates whether the device is phase locked, a
logic'1'is present if the device is locked, and a logic `0' if it
is not.
Programable features
RF programmable divider Function as described
above.
Reference programmable divider Function as
described above.
Charge pump current The charge pump current can
be programmed by bits C1 and C0 within data byte 5,
as defined in Table 6.
Test mode The test modes are invoked by setting bit
T2 = 1, with selected test modes as defined by bits T1
and T0 as described in Table 5. Clock input on crystal
and RF input pins are required to invoke FL test modes.
Reference/Comparison frequency output The
reference frequency f
REF
or comparison frequency
f
COMP
can be switched to the REF/COMP output,
function as defined in Table 7. RE and RS default to
logic'1'during device power up, thus enabling the
comparison frequency f
COMP
at the REF/COMP output.
Write mode
With reference to Table 2, bytes 2 and 3 contain frequency
information bits 2
14
-2
0
inclusive. Bytes 4 and 5 control
the reference divider ratio (see Table 1), charge pump
setting (see Table 6), REF/COMP output (see Table 7),
output ports and test modes (see Table 5).
After reception and acknowledgement of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as a byte 2 or
4, a logic `0' indicating byte 2, and a logic `1' indicating
byte 4.
Having interpreted this byte as either byte 2 or 4,
the following data byte will be interpreted as byte 3 or 5
respectively. Having received two complete data bytes,
additional data bytes can be entered, where byte
interpretation follows the same procedure, without re-
addressing the device. This procedure continues until a
STOP condition is received. The STOP condition can be
generated after any data byte, if however it occurs during
Table 1 - Reference division ratios
Address
Programmable divider
Programmable divider
Control data
Control data
1
0
2
7
1
C1
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
1
2
14
2
6
T2
C0
0
2
13
2
5
T1
RE
0
2
12
2
4
T0
RS
0
2
11
2
3
R3
P3
MA1
2
10
2
2
R2
P2
MA0
2
9
2
1
R1
P1
0
2
8
2
0
R0
P0
A
A
A
A
A
Table 2 Write data format (MSB transmitted first)
MSB
LSB
A
Acknowledge bit
MA1, MA0
Variable address bits (see Table 4)
2
14
-2
0
Programmable division ratio control bits
R3-R0
Reference division ratio select (see Table 1)
C1, C0
Charge pump current select (see Table 6)
RE
Reference oscillator output enable
RS
REF/COMP output select when RE=1 (see Table 7)
T2-T0
Test mode control bits (see Table 5)
P3-P0
P3, P2, P1 and P0 port output states
5
SP5769
A
Acknowledge bit
MA1, MA0
Variable address bits (see Table 4)
POR
Power On Reset indicator
FL
Phase lock flag
Address
Status byte
1
POR
Byte 1
Byte 2
1
FL
0
0
0
0
0
0
MA1
0
MA0
0
1
0
A
A
MSB
LSB
Table 3 - Read data format (MSB transmitted first)
100
1000
2000
FREQUENCY (MHz)
VIN (mVRMS INT
O 50
)
300
40
200
OPERATING WINDOW
3000
4000
100
Figure 3 - Typical RF input sensitivity
Table 4 - Address selection
*
Programmed by connecting a 15k
resistor from pin 10 to V
CC
0
0
1
1
MA1
0 to 01V
CC
Open circuit
04V
CC
to 06V
CC
*
09V
CC
to V
CC
Address input voltage level
MA0
0
1
0
1
T2
Test mode description
0
1
1
1
1
T1
X
0
0
1
1
T0
X
0
1
0
1
Normal operation
Charge pump sink
Status byte FL = logic `0'
Charge pump source
Status byte FL = logic `0'
Charge pump disable
Status byte FL = logic `1'
P0 = f
PD
/2
Table 5 - Test modes
0
1
1
RE
High impedance
f
REF
selected
f
COMP
selected
REF/COMP output
RS
X
0
1
Table 7 - REF/COMP output
Current (
A)
0
0
1
1
0
1
0
1
C1
C0
Min.
Typ.
Max.
+ - 116
+ - 247
+ - 517
+-1087
+-155
+-330
+-690
+-1450
+-194
+-412
+-862
+ - 1812
Table 6 - Charge pump current
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