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SP8647
250MHz4
4
4
4
4
10/11
DS3643-12
The SP8647 is an ECL variable modulus divider, with
ECL10K and TTL/CMOS compatible outputs. It divides by 10
when either of the ECL control inputs, PE1 or PE2, is in the high
state and by 11 when both are low (or open circuit).
The two clock inputs are interchangeable and either will act
as a clock inhibit when connected to an ECL high level.
Normally, one input is left open circuit and the other is AC-
coupled, with externally applied bias.
FEATURES
s
ECL Compatible Inputs/Outputs
s
Open Collector TTL/CMOS Output
s
AC-Coupled Input (External Bias)
QUICK REFERENCE DATA
s
Supply Voltage: 252V6025V (ECL), 50V6025V (TTL)
s
Power Consumption: 260mW
s
Temperature Range: 230
C to 170
C
Fig. 1 Pin connections - top view
DG16
CLOCK INPUT 2
NC
NC
NC
V
EE
TTL/CMOS OUTPUT
NC
ECL OUTPUT
CLOCK INPUT 1
PE1
PE2
NC
V
CC
NC
NC
ECL OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SP8647
CONTROL INPUTS
Fig. 2 Functional diagram
ABSOLUTE MAXIMUM RATINGS
Supply voltage, |V
CC
2
V
EE
|
Output current
Storage temperature range
Max. junction temperature
Open collector voltage (pin 11)
Max. clock input voltage
Max. open collector current
V
CC
D1
CK
Q1
D2
CK
Q2
D3
CK
Q3
D4
CK
Q4
PE1
PE2
CLOCK INPUT 1
CLOCK INPUT 2
TTL/CMOS
OUTPUT
OUTPUT
OUTPUT
Q4
V
EE
2
3
1
16
5
12
11
8
9
ORDERING INFORMATION
SP8647 B DG
5962-90618 (SMD)
8V
20mA
2
65
C to 1150
C
1
175
C
1
12V
25V p-p
15mA
2
SP8647
Characteristic
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
ECL output high voltage
ECL output low voltage
Clock and PE input high voltage
Clock and PE input low voltage
Clock to ECL output delay
Set-up time
Release time
Symbol
f
MAX
f
MIN
I
EE
V
OH
V
OL
V
INH
V
INL
t
p
t
s
t
r
250
2
085
2
18
2
093
25
3
Min.
Max.
50
65
2
07
2
15
2
162
6
Units
Input = 400-800mV p-p
Input = 400-800mV p-p
V
EE
= 252V
V
EE
= 252V (25
C)
V
EE
= 252V (25
C)
V
EE
= 252V (25
C)
V
EE
= 252V (25
C)
Conditions
Notes
MHz
MHz
mA
V
V
V
V
ns
ns
ns
5
5
5
6
3, 6
4, 6
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
ECL OPERATION
Supply voltage, V
CC
= 0V, V
EE
= 252V 6 025V
Temperature, T
AMB
= 230
C to 170
C
TTL OPERATION
Supply voltage, V
CC
= 5V 6 025V, V
EE
= 0V
Temperature, T
AMB
= 230
C to 170
C
Characteristic
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
TTL output low voltage
TTL output high voltage
Clock to TTL output high delay,1ve going
Clock to TTL output low delay,2ve going
Set-up time
Release time
Symbol
f
MAX
f
MIN
I
EE
V
OL
V
OH
t
PLH
t
PHL
t
s
t
r
250
35
25
3
Min.
Max.
50
65
05
15
15
Units
Input = 400-800mV p-p
Input = 400-800mV p-p
V
CC
= 525V, sink current = 8mA
V
CC
= 50V
Conditions
Notes
5
5
5
5, 7
5, 7
6
6
3, 6
4, 6
NOTES
1. The temperature coefficients of V
OH
= 1163mV/
C, V
OL
= 1094mV/
C and of V
IN
= 1122mV/
C.
2. The test configuration for dynamic testing is shown in Fig.6.
3. The set-up time t
s
is defined as the minimum time that can elapse between L
H transition of control input and the next L
H clock pulse transition
to ensure that the 410 mode is obtained.
4. The release time t
r
is defined as the minimum time that can elapse between H
L transition of control input and the next L
H clock pulse transition
to ensure that the 411 mode is obtained.
5. Tested at 25
C only.
6. Guaranteed but not tested.
7. The open collector output is not recommended for use at output frequencies above 15MHz. C
LOAD
< 5pF.
Value
Value
MHz
MHz
mA
V
V
ns
ns
ns
ns
Fig. 3 Typical input characteristic
1200
1000
800
600
400
200
0
0 100 200 300
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE
(mV p-p)
*
Tested as specified
in table of Electrical
Characteristics
GUARANTEED
*
OPERATING
WINDOW
T
AMB
= 230
C TO 170
C
3
SP8647
L
H
L
H
PE1
L
L
H
H
TRUTH TABLE FOR
CONTROL INPUTS
11
10
10
10
PE2
Division ratio
Fig. 4 Timing diagram
Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 5V,
Ambient Temperature = 25
C. Frequencies in MHz, impedances normalised to 50
.
OPERATING NOTES
1. The clock and control inputs are ECLIII compatible. There
is an internal pulldown resistor to V
EE
of 43k
on each input
and therefore any unused input can be left open circuit. If it
is desirable to capacitively couple the signal source to the
clock then an external bias is required as shown in Fig. 6.
The external bias voltage should be 213V at 25
C.
2. The outputs are compatible with ECLII but can be interfaced
to ECL10K as shown in Fig.8.
3. The circuit will operate down to DC but slew rate must be
better than 100V/
s.
4. Input impedance is a function of frequency. See Fig. 5.
5. The TTL/CMOS output is a free collector, with an output
rise/fall time which is a function of load resistance and load
capacitance. The load capacitance should therefore be kept
to a minimum and the load resistance should not be too
small otherwise V
OL
will be too great. For example, TTL
output current = 8mA, V
OL
= 05V. For CMOS outputs, the
value of load resistor should be the maximum consistent
with satisfactory rise times.
6. All components should be suitable for the frequency in use.
6
t
r
t
s
5
5
CLOCK INPUT
PE INPUT
OUTPUT
j 2
j 1
j 0.5
j 0.2
0
2
j 0.2
2
j 0.5
2
j 1
2
j 2
1
0.5
0.2
j 5
2
j 5
2
5
50
100
150
200
250
4
SP8647
1N4148
DUT
91
450
450
0.1
0.1
OUTPUTS TO
SAMPLING
SCOPE
2
52V
5
9
8
12
1
16
1n
1n
1n
750
33
33
20
INPUT FROM
GENERATOR
TO SAMPLING
SCOPE
DIVIDE BY
10/11
11
9
8
2k
2k
43k
43k
2
3
15k
680
V
CC
12
1n
43k
43k
1
16
5
680
1
5V
V
EE
(0V)
TTL OUTPUT
0V
1N4148
91
750
10n
TP1
TTL CONTROL INPUTS
0 = 411
1 = 410
Fig. 7 Typical application showing TTL interfacing. NB: Voltage at TP1 should be 1375V at 25
C.
47
2
52V
PIN 8 OR 9
15k
ECL OUTPUT
Fig. 6 Test circuit
Fig. 8 Interfacing to ECL10K
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