Figure 1 Functional Diagram
Description
The SP8782 is a multi-modulus divider which divides by 16/
17 when the Ratio Select input is low and by 32/33 when
theRatio Select input is high. When high, the modulus Control
input selects the lower division ratio (16 or 32) and the higher
ratio (17 or 33) when it is low.
The device uses resynchronisation techniques to reduce the
effects of propagation delays in frequency synthesis.
The SP8782A (ceramic DIL package) is characterised over
the full military temperature range of -55 C to +125 C, the
SP8782B (miniature plastic DIL package) over the industrial
range of -40 C to+85 C.
Features
Advanced Resynchronisation techniques to negate
loop delay effects
CMOS compatible output capability
Multi-Modulus division
Available as DESC SMD 5962-9208901MPA
Absolute Maximum Ratings
Supply Voltage
6V
Clock input level
2.5V p-p
Junction temperature
+175 C
Storage temperature range:
SP8782A
SP8782B
V
RATIO
SELECT
CC
MODULUS
CONTROL
INPUT
CLOCK INPUT
CLOCK INPUT
OUTPUT
V
EE
1
2
2
3
4
5
7
16/17
32/33
SP8782A & B
March 2006
1GHz 16/17, 32/33 Multi-Modulus Divider
-55 C to +125 C
-55 C to +150 C
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright
1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Ordering Information
SP8782/B/MP
8 Pin SOP/SOIC
Tubes
SP8782/A/DG
8 Pin CERDIP
Tubes
SP8782/B/MPTC
8 Pin SOP/SOIC
Tape & Reel
SP8782/B/MP2Q
8 Pin SOP/SOIC**
Tape & Reel
**Pb Free Tin/Silver/Copper
2
SP8782A & B
Electrical Characteristics
Unless otherwise stated, the Electrical Characteristics are guaranteed over the specified supply, frequency and
temperature range.
Supply Voltage
,
V
CC
= +4V to +5.5V, V
EE
= 0V
Temperature Tamb= -55
C to +125
C, (SP8782A), -40
C to +85
C (SP8782B)
Characteristic
Pin
Value
Conditions
Min
Max
Units
Maximum frequency
2, 3
1
GHz
Input = 200-1200mVp-p
(sinewave input)
Minimum frequency
2, 3
50
MHz
Input = 400-1200mVp-p
Min Slew rate for low frequency operation
2, 3
100
V/
s
Power Supply current, I
CC
8
60
mA
Output unloaded, V
CC
=5.5V
Output low voltage
7
0
1.7
V
Output high voltage
7
V
CC
-1.4
V
CC
V
Modulus control input high voltage
5
0.7V
CC
V
CC
V
At driver end of 3k
resistor
Modulus control input low voltage
5
0
0.3V
CC
V
At driver end of 3k
resistor
Modulus control input high current
5
0.6
1.2
mA
Via 3k
resistor to V
CC
Modulus control input low current
5
-0.6
-1.2
mA
Via 3k
resistor to V
CC
Ratio select input high voltage
1
0.6V
CC
V
CC
V
Ratio selected input low voltage
1
0
0.4V
CC
V
Ratio select input current
1
-10
10
A
Clock to output propagation Delay
2,3,7
3
ns
Set-up time, t
s
5,7
3
ns
See note 1 and Fig. 3a
Release time,t
r
5,7
3
ns
See note 2 and Fig. 3b
Notes: 1. The set-up time t
s
is defined as the minimum time that can elapse between L
H transition of the
modulus control input and the next L
H output transition to ensure that the
16 (32) mode is obtained.
2. The release time t
r
is defined as the minimum time that can elapse between H
L transition of the modulus
control input and the next L
H output transition to ensure that the
17 (33) mode is obtained.
Figure 2 Typical Pin Connections
DG 8
RATIO SELECT
CLOCK INPUT
CLOCK INPUT
V
EE
V
CC
OUTPUT
NC
MODULUS CONTROL
1
2
3
4
8
7
6
5
MP 8
V
CC
OUTPUT
NC
MODULUS CONTROL
1
2
3
4
8
7
6
5
RATIO SELECT
CLOCK INPUT
CLOCK INPUT
V
EE
3
SP8782A & B
DON'T CARE
8 (16)
t
r
t
r
8 (16)
9 (17)
CLOCK INPUT
MODULUS
CONTROL INPUT
OUTPUT
DON'T CARE
8 (16)
DIVIDE-BY-17 (33) MODE
ESTABLISHED
EXTRA
PULSE
Fig. 3a Setting divide-by-16 (32) mode
DON'T CARE
9 (17)
t
s
t
s
8 (16)
8 (16)
CLOCK INPUT
MODULUS
CONTROL INPUT
OUTPUT
DON'T CARE
8 (16)
DIVIDE-BY-16 (32) MODE
ESTABLISHED
Figure 3 Timing diagrams
Table 1 Truth table for control inputs
Modulus control
Ratio select input
input
0
1
0
17
33
1
16
32
Figure 3b Setting divide - by - 17 (33 mode)
Figure 3a Setting divide - by - 16 (32 mode)
4
SP8782A & B
1600
1400
1200
1000
800
600
400
200
0
0 200 400 600 800 1000
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE
(mV p-p)
*
Tested as speci
in table of E
Characteristi
GUARANTEED
*
OPERATING
WINDOW
Figure 4 Typical input characteristics
7
6
2
3
OUTPUT
V
EE
CLOCK
INPUT
DIVIDE BY
16/17 OR 32/33
V
CC
4
8
5
MODULUS
CONTROL
INPUT
1
RATIO SELECT
10n
3k
NOTES
1. Pin 6 is grounded to improve
isolation
between the output
and the
modulus control input.
2.
The 3k
resistor
on pin
5 reduces
the amplitude
of the modulus control
signal to minimise radiation.
1n
1n
Figure 5 Typical application showing interfacing
DIVIDE BY
16/17 OR 32/33
* Tested as specified
in table of Electrical
Characteristics
NOTES
1.
Pin 6 is grounded to improve
isolation between the output and
the modulus control input
2.
The 3k
resistor on pin 5 reduces
the amplitude of the modulus control
signal to minimise radiation
5
SP8782A & B
j 2
j 1
j 0.5
j 0.2
0
2
j 0.2
2
j 0.5
2
j 1
2
j 2
1
0.5
0.2
j 5
2
j 5
2
5
1000
200
400
600
800
1100
Figure 6 Typical input impedance. Test conditions: supply voltage =5V, ambient temperature =25
C,
frequencies in MHz, impedances normalised to 50
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