HC44

SP8854E

2.7GHz Parallel Load Professional Synthesiser

Preliminary Information

DS4238

ISSUE 2.0

June 1998

Ordering Information

SP8854E KG HCAR

Non-standard temperature range,

255

°C to 1100°C, standard product screening

SP8854E IG HCAR

Industrial temperature range,

240

°C to 185°C, standard product screening

The SP8854E is one of a family of parallel load synthesisers

containing all the elements apart from the loop amplifier to
fabricate a PLL synthesis loop. Other parts in the series are
the SP8852E which is fully programmable, requiring tw0 16-
bit words to set the RF and reference counters and the
SP8855E which is fully programmable using hard wired links
or switches.

The SP8854E is programmed using a 16-bit parallel data

bus. Data is stored in an internal buffer. The 10-bit program-
mable reference divider is programmed by connecting the
10 programming pins either to ground or 15V. The device
can therefore be programmed with a single transfer from the
control microprocessor. Hard wired inputs can also control
the F

and F

REF

outputs and the control sense of the loop.

Features

2·7 GHz Operating Frequency

Single 5V Supply

Low Power Consumption <1·3W

High Comparison Frequency : 20MHz

High Gain Phase Detector : 1mA/rad

Zero `Dead Band' Phase Detector

Wide Range of RF and Reference Division Ratios

Programming by Single Word Data Transfer

Absolute Maximum Ratings

Supply voltage
Operating temperature
Storage temperature
Prescaler and reference input voltage
Data inputs

Junction temperature

20·3V to 16V

255

°C to1100°C

265

°C to 1150°C

2·5V p-p

10·3V

20·3V

1175

°C

Figure 1 - Pin connections - top view

and F

REF

outputs are reversed using the control

direction input, pin 23. The above diagram is correct
when pin 23 is high.

1 44

DATA BIT 4
DATA BIT 3
DATA BIT 2
DATA BIT 1
DATA BIT 0

0V (PRESCALER)

RF INPUT
RF INPUT

(PRESCALER)

VEE

LOCK DETECT

STROBE
REF DIV BIT 0
REF DIV BIT 1
REF DIV BIT 2
REF DIV BIT 3
REF DIV BIT 4
REF DIV BIT 5
REF DIV BIT 6
REF DIV BIT 7
REF DIV BIT 8
REF DIV BIT 9

C-LOCK DETECT

SET

CHARGE PUMP

OUTPUT

CHARGE PUMP

REF

ENABLE

CONTROL

DIRECTION

REF

REF OSC CAP

ACIT

REF IN/CR

YST

T
A

BIT 5

T
A

BIT 6

T
A

BIT 7

T
A

BIT 8

T
A

BIT 9

T
A

BIT 10

T
A

BIT 1

T
A

BIT 12

T
A

BIT 13

T
A

BIT 14

T
A

BIT 15

SP8854E

SP8854E

Preliminary Information

STROBE

B10

B11

B12

B13

B14

B15

INPUT

INTERFACE

48/9

PRESCALER

RF INPUT

PRESCALER

3-BIT

A COUNTER

11-BIT

M COUNTER

B13 B14

B15

LOAD

RF BUFFER

PHASE

DETECTOR

10-BIT REFERENCE DIVIDER

REF

REFERENCE

CRYSTAL

REFERENCE

CAPACITOR

CHARGE PUMP OUTPUT

CHARGE PUMP REFERENCE

LOCK DETECT OUTPUT

SET

C-LOCK DETECT

REF

FPD/FREF ENABLE

CONTROL DIRECTION

MODULUS

CONTROL

*FREF and FPD outputs are reversed using
the control direction input. The pin allocations
shown are correct when bit 12 is high.

RF INPUT

BIT 0

BIT 9

REFERENCE DIVIDER PROGRAMMING

Figure 2 - Block Diagram

SP8854E

Preliminary Information

Pin

Description

These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these
pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in
buffers when pin 39 is low.

Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into
pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC
biased.

A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
an external indication of phase lock.

A capacitor connected to this point determines the lock detect integrator time constant and can
be used to vary the sensitivity of the phase lock indicator.

An external resistor from pin 19 to V

sets the charge pump output current.

The phase detector output is a single ended charge pump sourcing or sinking current to the
inverting input of an external loop filter.

Connected to the non-inverting input of the loop filter to set the optimum DC bias.

Part of the input bus. When this pin is high, the F

REF

/ F

outputs are enabled.

High is open circuit.

This pin controls charge pump output direction. When pin 23 is high, the output sinks current
when F

> F

REF

or when the RF phase leads the reference phase. When pin 23 is low, the

relationship is reversed (see Table 3).

RF divider output pulses. F

= RF input frequency/(M.N1A). Pulse width = 8 RF input cycles

(1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. F

REF

= reference input frequency/R. Pulse width = high period

of Ref input.

Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as
an onboard crystal oscillator.

This pin is the input buffer amplifier for an external reference signal. This amplifier provides the
active element if an onboard crystal oscillator is used.

These pins set the reference divider ratio R. High is open circuit.

When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump
output is disabled. When pin 39 is low the data on the RF data and PD gain pins is fixed in the
buffers, the buffers are loaded into the RF counters and the PD gain control, all the counters are
active, and the charge pump is enabled. High is open circuit.

These pins set the charhe pump current multiplication factor (see Table 2). The data is
transparent into the buffers when pin 39 is high and frozen when pin 39 is low.
High is open circuit.

1-11, 42-44

13 (RF INPUT)

14 (RF INPUT)

17 (LOCK DETECT INPUT)

18 (C-LOCK DETECT)

19 (R

SET

)

20 (CHARGE PUMP OUTPUT)

21 (CHARGE PUMP REF)

22 (F

REF

/ F

ENABLE)

23 (CONTROL DIRECTION)

if pin 23 is high

REF

if pin 23 is low

REF

if pin 23 is high

27 (Ref. oscillator capacitor)

28 (REF IN/XTAL)

29-38

39 (STROBE)

40, 41 (PD gain)

Table 1 - Pin Descriptions

SP8854E

Preliminary Information

Supply current

RF input sensitivity

RF division ratio

Reference division ratio

Comparison frequency

Reference input frequency

Reference input voltage

REF

output voltage high

REF

output voltage low

LOCK DETECT output voltage

CHARGE PUMP current

Input bus logic level high

Input bus logic level low

Input bus current source

Input bus current sink

Up/down current matching

CHARGE PUMP REFERENCE voltage

SET

current

SET

voltage

C-LOCK DETECT current

STROBE pulse width

Data setup time

Electrical Characteristics

The Electrical Characteristics are guaranteed over the following range of operating conditions unless otherwise stated
T

AMB

= 2 55

°C to 1100°C (KG parts), 2 40°C to 185°C (IG parts); V

= 4·75V to 5·25V

Characteristic

Conditions

61·4

62·0

63·4

65·4

3·5

2200

21·6

0·5

100

180

20·8

21·4

300

61·5

62·3

63·8

66·1

1·6

110

Pin

18, 26

13,14

13,14, 24

28, 25

28, 24, 25

24, 25

19, 20, 21

1-11, 22,

23, 29, 44

1-11, 22,

23, 29, 44

1-11, 22,

23, 29, 44

1-11, 22,

23, 29, 44

Typ.

Max.

Min.

dBm

MHz

dBm

µA

Units

Value

240

16383

1023

100

110

500

61·7

62·5

64·1

66·5

20·5

100MHz to 2·7GHz. See note 3.

Ref division ratio >2. See note 1

WRT V

, 2·2k

to 0V

WRT V

, 2·2k

to 0V

OUT

= 3mA

PIN20

= V

PIN21

, I

PIN19

= 1·6mA,

multiplication factor = 1

PIN20

= V

PIN21

, I

PIN19

= 1·6mA,

multiplication factor = 1·5

PIN20

= V

PIN21

, I

PIN19

= 1·6mA,

multiplication factor = 2·5

PIN20

= V

PIN21

, I

PIN19

= 1·6mA,

multiplication factor = 4·0

= 0V

= V

PIN20

= V

PIN21

, I

PIN19

= 1·6mA

PIN19

= 1·6mA, current

multiplication factor = 1·0

PIN19

= 1·6mA, current

multiplication factor = 4·0

Note 2

PIN19

= 1·6mA

PIN18

= 4·7V

Note 3

NOTES
1. Lower frequencies may be used provided that slew rates are maintained.
2. Pin 19 current3multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.
3. Guranteed but not tested.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP8854EHCAR

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SP8854EHCAR