THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1994
DS3002-2.0
VP101
30/50MHz 8-BIT CMOS VIDEO DAC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
BLANK
AGND
9
10
32
31
R
7
R
6
R
5
R
4
SYNC
V
REF
B
7
B
6
B
4
DP40
11
12
13
14
15
16
17
18
30
29
28
27
26
25
24
23
V
AA
COMP
I
SYNC
FS ADJUST
REF WHITE
19
20
22
21
B
1
B
2
B
3
R
0
R
1
R
2
R
3
B
5
G
4
CLOCK
B
0
AGND
V
AA
G
6
G
7
G
5
IOB
IOR
IOG
AGND
G
1
G
0
G
2
G
3
BLANK
AGND
R
7
R
6
R
5
R
4
SYNC
V
REF
B
7
B
6
B
4
V
AA
COMP
I
SYNC
FS ADJUST
REF WHITE
B
1
B
2
B
3
R
0
R
1
R
2
R
3
B
5
G
4
CLOCK
B
0
AGND
V
AA
G
6
G
7
G
5
IOB
IOR
IOG
AGND
G
1
G
0
G
2
G
3
AGND
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND
V
AA
29
30
31
32
33
34
35
36
37
38
39
V
AA
BLANK
AGND
R
7
R
6
R
5
R
4
SYNC
V
REF
B
7
B
6
B
4
V
AA
COMP
I
SYNC
FS ADJUST
REF WHITE
B
1
B
2
B
3
R
0
R
1
R
2
R
3
B
5
G
4
CLOCK
B
0
AGND
V
AA
G
6
G
7
G
5
IOB
IOR
IOG
AGND
G
1
G
0
G
2
G
3
AGND
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AGND
V
AA
23
24
25
26
27
28
29
30
31
32
33
V
AA
HP44
GP44
Fig.1 Pin connections (not to scale) - top view
The VP101 is a CMOS 8-bit video DAC designed for
use in high performance, high resolution colour graphics
applications.
The device uses video control inputs (BLANK, SYNC
and REF WHITE) to provide the VP101 with the video
pedestal levels required to generate RS-343A compatible
video signals into a doubly-terminated 75
load, or
alternatively to produce RS-170 video signals across a
singly-terminated 75
load.
Data and control inputs are fully pipelined to maintain
synchronisation between the DAC outputs.
The full scale output current is defined by a 1.2V
reference and a single resistor. The reference voltage is
included on-chip in the VP101, but may be supplied
externally if required (see Fig. 2).
Differential and integral linearity errors of the D-A
converters are guaranteed to be a maximum of
1LSB over
the full operating temperature range.
FEATURES
s
30/50MHz Pipeline Operation
s
Triple 8-Bit D-A Converters
s
1 LSB Differential Linearity Error
s
1 LSB Integral Linearity Error
s
Guaranteed Monotonic
s
RS-343A/RS-170 Compatible Levels
s
Drives Doubly Terminated 75
Load
s
Single 5V Power Supply
s
Typical Power Dissipation 500mW
s
Direct Replacement for Bt101
s
On-Chip Reference Available
APPLICATIONS
s
High Resolution Colour Graphics
s
CAE/CAD/CAM Applications
s
Image Processing
s
Video Reconstruction
s
Instrumentation
ORDERING INFORMATION
VP101-3 BA DP
(Commercial - Plastic DIL Package)
VP101-3 BA HP
(Commercial - J-lead Package)
VP101-5 BA DP
(Commercial - Plastic DIL Package)
VP101-5 BA HP
(Commercial - J-lead Package)
VP101-3 BA GP
(Commercial - Plastic Leaded Chip
Carrier, Gullwing formed leads)
ABSOLUTE MAXIMIM RATINGS
(Referenced to AGND)
DC supply voltage (V
AA
) -0.3 to +7V
Digital input voltage-0.3 to V
AA
+0.3V
Analog output short circuit duration Indefinite
Ambient operating temperature 0
C to +70
C
Storage temperature range-55
C to +125
C
VP101
2
Fig.2 functional block diagram of VP101
THERMAL CHARACTERISTICS
DP HP GP
Thermal resistance, chip-to-case
jc
=
12 17 17
C/W
Thermal resistance, chip-to-ambient
jc
= 45 50 50
C/W
RECOMENDED OPERATING CONDITIONS
Parameter
Symb
ol
Min.
Value
Typ.
Max.
Units
Conditions
Supply voltage
V
AA
4.75
5.00
5.25
V
Ambient operating temperature
T
amb
0
+70
C
Output load
Reference voltage
(internal or external)
FS ADJUST resistor
R
L
V
REF
R
SET
1.14
37.5
1.20
542
1.26
V
for RS-343A compatible output levels
123
VP101
3
DC CHARACTERISTICS
AC CHARACTERISTICS
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Conditions
Max clock rate
Data and control setup time
Data and control hold time
Clock cycle time
Clock pulse width high time
Clock pulse width low time
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
Analog output skew
Pipeline delay
V
AA
supply current
f
max
t
SU
t
H
t
CYC
t
CLKH
t
CLKL
t
DLY
t
VRF
t
S
I
AA
50
6
2
20
8
8
1
10
12
100
0
1
120
8
3
1
175
30
8
2
33.3
10
10
1
10
15
100
0
1
100
9
3
1
140
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pV-sec
ns
Clock
mA
at f
max
, V
AA
= 5V
VP101-5
VP101-3
Parameter
Symbol
Min.
Value
Typ.
Max.
Units
Conditions
Resolution (each DAC)
Accuracy (each DAC)
Integral linearity error
Differential linearity error
Grey scale error
Monotonicity
INL
DNL
8
0.3
0.3
1%
guaranteed
1
1
5%
Bits
LSB
LSB
% grey scale
Digital inputs
Input high voltage
Input low voltage
Input high current
Input low current
V
IH
V
IL
I
IH
I
IL
3.0
AGND-0.3
V
AA
+0.3
1.2
+1
-1
V
V
A
A
binary
coding
Analog outputs
Grey scale current range
Output currents
White level relative to blank level
White level relative to black level
Black level relative to blank level
Blank level on IOR, IOB
Blank level on IOG
Sync level on IOG
LSB size
DAC to DAC matching
Output compliance
External V
REF
input current
Internal voltage reference
Internal V
REF
temperature coefficient
LSB
V
OC
I
REF
V
REF
15
17.69
16.74
0.95
0
6.29
0
-0.5
1.14
255
19.06
276
17.62
255
1.44
21
5
0
7.62
111
5
69.1
2
1.20
40
20
20.40
18.50
1.90
50
8.96
50
+1.4
10
1.26
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
A
LSB
A
%
V
A
V
ppm/
C
RS-343A
tolerances
assumed
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
As specified in recommended operating conditions.
144424443
123
VP101
4
NOTE: Typical with full scale IOG = 26.68mA, R
SET
= 542
, V
REF
= 1.2V, I
SYNC
connected to IOG
Table 1: Video output truth table
Full Scale output current is set by an external resistor
(R
SET
) between the FS ADJUST pin and AGND. R
SET
has a
typical value of 542
for generation of RS-343A video into a
37.5
load. The VP101 may be used in applications where
an external 1.2V (typical) reference is provided, in which
case the external reference should be temperature
compensated and provide a low impedance output.
The D-A converters on the VP101 use a segmented
architecture in which bit currents are routed to either the
output or AGND by a sophisticated decoding scheme.This
architecture eliminates the need for precision component
ratios and greatly reduces the switching transients
associated with turning current sources on or off.
Monotonicity and low glitch energy are guaranteed by using
identical current sources and current steering their outputs.
An on-chip operational amplifier stabilises the full scale
output current against temperature and power supply
variations.
The analog outputs of the VP101 are capable of directly
driving a 37.5
load, such as a doubly terminated 75
co-
axial cable or interpolation filters.
CIRCUIT DESCRIPTION
As shown in the Fig. 2, the VP101 contains three 8-bit
D-A converters, input latches, and a loop amplifier.
On the rising edge of each clock cycle, (see Fig. 4), 24
bits of colour information (R
0
-R
7
, G
0
-G
7
, and B
0
-B
7
) are
latched into the device and presented to the three 8-bit D-A
converters. The REF WHITE input, also latched on the rising
edge of each clock cycle, and will force the inputs of each D-
A converter to $FF.
SYNC and BLANK are latched on the rising edge of the
clock to maintain synchronisation with the colour data. These
inputs add appropriately weighted currents to the analog
outputs, producing the specific output levels required for
video applications as shown in Fig. 3. Table 1 details how the
SYNC, BLANK, and REFWHITE inputs modify the output
levels.
The I
SYNC
current output is typically connected directly
to the IOG output and is used to encode sync information
onto the IOG output. If I
SYNC
is not connected to the IOG
output, sync information will not be encoded on the green
channel, and the IOR, IOG and IOB outputs will have the
same full scale output current.
Fig.3 Composite video output waveform
Description
IOG
(mA)
IOR/IOB
(mA)
REF
WHITE
SYNC
BLANK
DAC
I/P Data
White Level
26.68
19.06
1
1
1
$XX
White Level
26.68
19.06
0
1
1
$FF
Data
Data + 9.06
Data + 1.44
0
1
1
Data
Data-Sync
Data + 1.44
Data + 1.44
0
0
1
Data
Blank Level
9.06
1.44
0
1
1
$00
Blank-Sync
1.44
1.44
0
0
1
$00
Blank Level
7.62
0
X
1
0
$XX
Sync Level
0
0
X
0
0
$XX
PDF 
ZIP