VP 510

VP510

Bi Directional Colour Space Converter

Advance Information

DS3507 - 1.6 September 1996

DESCRIPTION

The VP510 converts three channels of RGB data into two

channels of decimated chrominance and luminance data.
Alternatively it converts two channels of luminance and chromi-
nance data into three channels of interpolated RGB data.
Each channel has its own RAM based look up table, which can
be loaded from a host system and then used for gamma
correction and/or ranging.

The direction of the data flow is controlled by a bit in a

Control Register, and causes previous outputs to become
inputs and vice versa. The filters change from the decimating
to the interpolating mode, and correspondingly follow or
precede the colour space conversion.

The 3 x 3 conversion matrix is provided with user definable

12 bit coefficients which have a range from -4.0 to +4.0. The
luminance channel is provided with a 23 tap low pass filter
which can decimate or interpolate by two. The chrominance
channels each have two 11 tap filters in series which can
decimate or interpolate by four. This arrangement allows the
device to accept or produce RGB data which has been 2x
oversampled, thus avoiding the need for external analog anti-
aliasing filters. If necessary the device will still accept or
produce video data which has not been oversampled.

FEATURES
I

User definable colour space conversion

Sampling rates up to 27 MHz

On chip decimating or interpolating FIR filters

Conversion from 24 bit inputs to 16 bit outputs or vice
versa

RAM based look up tables for gamma correction

100 pin Quad Flat Pack

ASSOCIATED PRODUCTS
I

VP2611 Integrated H.261 Video Encoder

VP2615 H.261 Video Decoder

VP520S Two dimensional Video Filter

Figure 1. Simplified Block Diagram

HREF

DELAYED

RD WR CS RES OEN CRI

23 TAP

DECIMATING /

INTERPOLATING

FILTER

COUNTER

ADDRESS

RAM

256 X 8 BITS

COUNTER

ADDRESS

RAM

256 X 8 BITS

3 X 3

MATRIX

MULTIPLIER

11 TAP

DECIMATING /

INTERPOLATING

FILTER

11 TAP

DECIMATING /

INTERPOLATING

FILTER

COUNTER

ADDRESS

RAM

256 X 8 BITS

11 TAP

DECIMATING /

INTERPOLATING

FILTER

11 TAP

DECIMATING /

INTERPOLATING

FILTER

HOST DATA BUS

ADDRESS BUS

CONTROL

RED

GREEN

BLUE

PIPELINE DELAY

HREF

FLAG

DELAYED

CHROMINANCE

LUMINANCE

CLEAR

CRO

CLOCK

CLK GEN

ORDERING INFORMATION

VP510 CG GPFR

(Commercial Temperature - PLCC Package).

VP 510

PIN DESCRIPTION

TYPE

DESCRIPTION

R7:0

I/O

Unsigned Red data. Range may be changed by the RAM look up table

G7:0

I/O

Unsigned Green data. Range may be changed by the RAM look up table

B7:0

I/O

Unsigned Blue data. Range may be changed by the RAM look up table

Y7:0

I/O

Unsigned Luminance data in or out. Range is user definable

C7:0

I/O

Two's complement or offset binary multiplexed chrominance data. Range is user definable

D7:0

I/O

Host data bus used for reading or writing

A4:0

Host Address Bus. Matrix coefficients and the control register are directly addressable

CLK

External line locked clock. All inputs and outputs are referenced to the rising edge

HREF

Horizontal or Composite reference used as a start of line indicator and to clear the FIR filters

HDLY

HREF input delayed by the 39 clock delay to a correctly filtered output

Input Flag as defined by the user. No internal operation.

FI delayed by the 39 clock delay to a correctly filtered output

CRI

An input which indicates that valid luminance and chrominance data is present

CRO

An output which indicates that valid luminance and chrominance data is on the output pins

OEN

Active low output enable for the tristate bus. Used in conjunction with a Control Register bit

Active low Chip Select from the host system

Active low request from the host to read the matrix coefficients and RAM contents

Active low request from the host to write to the device

RES

Asynchronous low reset used to initialise the device. Must be present for at least 1024 clock periods

LOOK UP TABLES

When the device is configured to produce chrominance

and luminance outputs from RGB inputs, each of the three
look up tables is addressed by its appropriate colour bus. Any
changes to the data thus occur before the colour space
conversion. Typically the look up tables are used to provide
gamma correction to linear RGB inputs, and / or to limit the
range of the inputs. The coefficients in the conversion matrix
are usually defined to expect either a range of 1 - 254 or 16 -
235, when converting to Cr and Cb chrominance values.

When the device is configured to produce RGB outputs,

the look up tables are positioned just before the output buses.
If linear outputs are required the tables can then be used to
remove the gamma correction which is produced by the
coefficients in the conversion matrix. They can also be used to
expand the range produced by the conversion matrix.

The RAM's are not dual ported and use by the host system

takes priority over pixel accessing. The RAM's are not directly
addressable from the host since the device only uses a 5 bit
address bus. Instead each RAM has an internal address
counter which must be cleared by writing to address decimal
27. Data is then sequentially written to the Red RAM by
supplying 256 bytes of data and address 28. Similarly using
address 29 will cause write operations to the green RAM, and
address 30 will cause write operations to the blue RAM. The
counters do not wrap around and must be reset by using
address 27 before further write or read operations are re-
quired. Read operations are mechanized in a similar manner
to write operations, except that a read strobe must be supplied
instead of a write strobe. Since each RAM has its own address
counter the red, green, and blue operations can be intermin-
gled on a byte by byte basis, rather than completing one colour
before starting the next.

Although host operations are asynchronous to the device

clock, this clock must be present to internally effect a read or
write operation. The read and write strobes are internally

synchronized to the clock, and the read strobe must be active
for at least five clock periods, and the write strobe for two clock
periods.

CONVERSION MATRIX

The 3 x 3 matrix multiplier performs the following basic

operation on three channels with identical sampling rates;

O/PA c1 c2 c3

I/PA

O/PB = c4 c5 c6 X

I/PB

O/PC c7 c8 c9

I/PC

When converting from RGB to colour difference informa-

tion, any decimation of the chrominance channels must be
done after the above operation. Conversely when producing
RGB data the chrominance channels must be interpolated
before the matrix operation. The configuration bit in the
Control Register takes care of this reorganization.

The coefficients C9:1 are loaded from the host system,

and are directly addressable using the 5 bits provided ( see
Table 1 ). Each coefficient must be loaded as two bytes since
it uses a total of 12 bits. The upper 4 bits in the most significant
byte are don't care values. If the loaded values are read back
by the host, these four bits will always be zero's, and are not
sign bits.

The 12 coefficient bits are comprised of 3 signed integer

and 9 fractional bits. This gives a decimal range of -4.00 to
approximately +3.998, with the fractional bits actually giving a
decimal resolution of 0.001953.

Pixel data going into the matrix multiplier uses a total of 13

bits; 10 signed integer bits plus 3 fractional bits. This additional
pixel accuracy is only obtained from the output of the interpo-
lating filters, where 10 integer bits are necessary to accommo-
date signed data with undershoot and overshoot beyond the
nominal gain.

VP 510

In the RGB to chrominance and luminance mode, when

pre interpolation does not occur, only 8 unsigned integer bits
are available from the look up table. Thus, within the 13 bit
total, the top 2 bits plus the bottom 3 bits will be made into
zero's.

Intermediate precision within the matrix multiplier grows to

15 signed integer bits plus 6 fractional bits. The least signifi-
cant 9 or 10 of the integer bits are selected at the output, and
the fractional bits are rounded to 3 bits. Ten integer bits are
used when the matrix is producing RGB from interpolated
chrominance and luminance. This allows for undershoot and
overshoot beyond the nominal 8 bit unsigned value.

Only 9 integer bits are necessary when the matrix is

producing chrominance, and the three fractional bits provide
additional precision into the decimating filter. In fact, if the
matrix is producing normalized chrominance, the coefficients
will have been chosen to produce an output in the range

� 127.

This range only requires 8 integer bits, and the ninth bit will be
a repeated sign bit. Note that

�127 is actually representing

�0.5 in this context. When the NORM bit in the Control
Register is reset, the chrominance outputs lie in the range

�1,

�256 in our internal representation. The full 9 integer bits are

then needed.

LUMINANCE FILTER

The luminance channel contains a 23 tap low pass filter

with internally defined 10 bit signed coefficients. When the
MODE bit in the Control Register is reset the filter will decimate
the sampling rate by two. When the MODE bit is set the filter
will interpolate the incoming data to produce outputs at twice

the incoming sampling rate. The filter coefficients remain the
same in both cases, but the gain is adjusted to preserve the
energy content..

When the filter is producing decimated luminance it ac-

cepts data from the matrix converter with 9 signed integer bits
plus 3 fractional bits ( 9.3 ). Since luminance is always positive,
however, the most significant bit will be zero. Words within the
filter calculation are allowed to grow to 15 integer bits plus 6
fractional bits. This is then rounded to 15 bits plus 3 fractional
bits, and finally the 10 least significant integer bits are chosen
to give a 10.3 result. The 10 bit integer component allows for
any undershoot or overshoot in the nominal 0 to 255 lumi-
nance range. The three fractional bits are used to round the
integer component to a 10 bit value. This is then clipped to a
value between 0 and 255. Negative values become zero, and
positive values greater then 255 will saturate at 255. Outputs
will not saturate under normal operating conditions, and the
circuit is only necessary to prevent overflow when the input
swings between the maximum and minimum values. Figure 2
illustrates the bit significance at various points in the data path.

When the filter is used to interpolate incoming luminance

data, the 8 bit input is padded to the 9.3 format used previ-
ously. The 13 bit output from the filter is applied to the matrix
converter without further rounding.

The response given by the filter is shown in Figure 3. Stop

band attenuation is approximately 45 dB, and the maximum
pass band ripple is 0.07 dB. These figures were obtained with
10 bit quantized coefficients and unquantized data. The
effects of the various quantization steps within the filter, plus
the reduction to 10 bits, is superimposed upon Figure 3. Also
shown is the CCIR601 specification for a luminance or RGB

0.1 0.2 0.3 0.4 0.5

CCIR601 Specification

Quantized Coefficients, FP Data

Quantized Coefficients and Data

0.0

-0.05

-0.1

0.05

0.1

0.05

0.1

0.15

0.2

PASSBAND RIPPLE

NORMALIZED FREQUENCY

Figure 3. Response of the Luminance Filter

Fig 2. Bit significance in the Y Filter

ROUND

MAC ARRAY

SELECT 10

INTEGER BITS

08.000 9.3

From

Pins

From

Matrix

1.9

Coefficents

15.6

15.3

10.3

To Matrix
Converter

in Interpolate

Mode

10.0

CLIP TO

0 - 255

Unsigned 8.0 to Pins

ROUND

VP 510

filter with 13.5 MHz output sampling.

CHROMINANCE FILTERS

Each chrominance channel has two 11 tap filters in series

and each pair can decimate or interpolate by four. The MODE
bit defines whether the filters interpolate or decimate. The
coefficients are 10 bit internally defined values, and are the
same in both modes. Figure 4 illustrates the bit significance at
various points in the calculation.

When the filters are used to decimate chrominance pro-

duced by the matrix converter, the inputs are represents by
either 8 or 9 signed integer bits plus 3 fractional bits. When the
matrix coefficients have been chosen to produce normalized
chrominance, the range can be represented by 8 integer bits.
Otherwise 9 integer bits are needed. When the inputs are
chrominance from the pins, the 3 fractional bits are set to zero,
and the ninth bit is sign extended. Words within the filter
calculation are allowed to grow to 15 integer bits plus 6
fractional bits. This is then rounded to 15 bits plus 3 fractional
bits.

When the filter is used to supply interpolated data to the

matrix converter, the least significant 10 integer bits are
selected out of the 15 outputs. Only 9 integer bits are actually
needed to represent the filtered chrominance with undershoot
and overshoot, but the hardware multiplier expects a 10 bit
number.

When the filter is producing decimated chrominance, the

NORM bit in the Control Register is used to select which 12
integer and fractional bits will be used by the rounding and
clipping circuit. For a full description of this operation see the

section on Chrominance Outputs.

The response of the filters is given in Figure 5. These

results were obtained with 10 bit quantized coefficients and
unquantized data. The effects of the various quantization
steps within the filter, and then finally rounding down to a 9 bit
value are superimposed onto Figure 5. Also shown is the
CCIR601 specification for sample rate conversion down to
4:2:2 resolution.

RGB INPUTS

The 24 bit RGB data must meet the set up and hold

requirements, with respect to the rising edge of the clock,
which are specified in Figure 6. The first edge after HREF has
gone inactive ( i.e. high ) must strobe in the first samples if the
delay to the first correctly filtered output is to match the fixed
pipline delay of 39 clock to the HDLY and FO outputs. The
maximum range is 0 to 255 for each component. If the
coefficients in the matrix converter are defined for a restricted
input range then this must be guaranteed by the user. Alterna-
tively the look up tables can be used to limit the range. When
HREF goes active low the outputs will go low after 39 clocks.

The VP510 has been designed to accept two times over-

sampled RGB data from an A/D converter. This avoids the
need for analog anti aliasing filters before the A/D converters.
For this reason the clock used by the VP510 is expected to be
twice the sampling clock needed to produce a given number
of RGB pixels per line. If the RGB inputs have not been
oversampled this double rate clock should still be used. Each
incoming sample will then be internally used twice, but the
decimating filters will still produce the correct luminance and
chrominance values.

Each input directly addresses its own RAM, which has

been pre-loaded to meet the system requirements. Linear

Figure 4. Bit significance

Figure 5. Response of the Chrominance Filters

TWO MAC

ARRAYS

RGB

From

Pins

From

Matrix

1.9

Coefficents

15.6

15.3

ROUND

CLIP TO 8 BITS

Signed 8.0 to Pins

SELECT 9 LS

INTEGER BITS

+ MS FRACTIONAL

9.1

10.3

To Matrix

Converter

in Interpolate

Mode

8.000

8.3 Normalized
9.3 Un - normalized

NORM CONTROL

BIT

ROUND WITH

MS FRACTIONAL

SELECT 10 LS

INTEGER BITS

(NO FRACTIONAL)

10.0

ROUND

WITH LSB

0.1 0.2 0.3 0.4 0.5

Quantized Coefficients, FP data

CCIR601 Specification

Quantized Coefficients and Data

0.0

0.05

-0.05

-0.1

0.1

0.15

0.1

0.15

0.05

Peak 0.25 dB

PASSBAND RIPPLE

NORMALIZED FREQUENCY

Электронный компонент: VP510