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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Meets jitter requirements of Telcordia GR-253-
CORE for OC-192, OC-48, OC-12, and OC-3
rates
Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
Provides four LVPECL differential output clocks at
622.08 MHz
Provides a CML differential clock at 155.52 MHz
Provides a single-ended CMOS clock at 19.44
MHz
Lock Indicator
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
Applications
SONET/SDH line cards
Network Element timing cards
Description
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
February 2005
Ordering Information
ZL30414QGC
64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
-40
C to +85C
ZL30414
SONET/SDH Clock Multiplier PLL
Data Sheet
Figure 1 - Functional Block Diagram
Frequency
Detector
VCO
C622oP/N-A
Frequency
LPF
C622oP/N-B
C622oP/N-C
VDD GND VCC
C622oP/N-D
C19o
C19oEN
C155oP/N
C155oEN
Loop
Filter
C622oEN-C
C19i
C622oEN-B
BIAS
C622oEN-A
C622oEN-D
& Phase
19.44MHz
05
State
Machine
LOCK
Reference
Bias Circuit
and
Dividers
and
Clock
Drivers
ZL30414
Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - TQFP 64 pin (Top View)
Pin Description
Pin Description Table
Pin #
Name
Description
1
GND
Ground. 0 volt
2
VCC1
Positive Analog Power Supply. +3.3 V 10%.
3
VCC
Positive Analog Power Supply. +3.3 V 10%.
4
5
C155oN
C155oP
C155 Clock Output (CML). These outputs provide a differential 155.52 MHz
clock.
6
GND
Ground. 0 volt
7
VCC2
Positive Analog Power Supply. +3.3 V 10%
8
LPF
Low Pass Filter (Analog). Connect to this pin external RC network (R
F
and
C
F
) for the low pass filter.
9
GND
Ground. 0 volt
10
GND
Ground. 0 volt
50
52
54
56
58
60
62
64
34
36
38
40
44
46
48
42
32
30
28
26
24
22
20
18
GND
VDD
GND
VCC
VDD
VDD
GND
GND
NC
GND
GND
LOCK
GND
C19o
VCC
GND
VDD
C1
9o
E
N
NC
N
C
IC
NC
VDD
C
19i
VDD
NC
N
C
VDD
GN
D
VCC
C622oP-C
C622oN
-
C
GN
D
VCC
C622oP-B
C622oN
-
B
GN
D
VCC
C622oP-A
C6
22o
N-A
GN
D
C622oP-D
C622oN
-
D
VCC
16
14
12
10
6
4
2
8
GND
VCC1
VCC
C155oN
C155oP
GND
VCC2
LPF
C622oEN-B
C622oEN-D
GND
BIAS
C155oEN
C622oEN-A
C622oEN-C
GND
GN
D
GN
D
GN
D
GND
ZL30414
65 - EP_GND
ZL30414
Data Sheet
3
Zarlink Semiconductor Inc.
11
BIAS
Bias. See Figure 13 for the recommended bias circuit.
12
C155oEN
C155o Clock Enable (CMOS Input). If tied high this control pin enables the
C155oP/N differential driver. Pulling this input low disables the output clock and
deactivates differential drivers.
13
C622oEN-A
C622 Clock Output Enable A (CMOS Input). If tied high this control pin
enables the C622oP/N-A output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
14
C622oEN-B
C622 Clock Output Enable B (CMOS Input). If tied high this control pin
enables the C622oP/N-B output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
15
C622oEN-C
C622 Clock Output Enable C (CMOS Input). If tied high this control pin
enables the C622oP/N-C output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
16
C622oEN-D
C622 Clock Output Enable D (CMOS Input). If tied high this control pin
enables the C622oP/N-D output clock.Pulling this input low disables the output
clock without deactivating differential drivers.
17
GND
Ground. 0 volt
18
VDD
Positive Digital Power Supply. +3.3 V 10%
19
NC
No internal bonding Connection. Leave unconnected.
20
NC
No internal bonding Connection. Leave unconnected.
21
NC
No internal bonding Connection. Leave unconnected.
22
VDD
Positive Digital Power Supply. +3.3 V 10%
23
IC
Internal Connection. Connect this pin to Ground (GND).
24
NC
No internal bonding Connection. Leave unconnected.
25
NC
No internal bonding Connection. Leave unconnected.
26
C19oEN
C19o Output Enable (CMOS Input). If tied high this control pin enables the
C19o output clock. Pulling this pin low forces output driver into a high
impedance state.
27
GND
Ground. 0 volt
28
C19i
C19 Reference Input (CMOS Input). This pin is a single-ended input reference
source used for synchronization. This pin accepts 19.44 MHz.
29
VDD
Positive Digital Power Supply. +3.3 V 10%
30
GND
Ground. 0 volt
31
VDD
Positive Digital Power Supply. +3.3 V 10%
32
GND
Ground. 0 volt
Pin Description Table (continued)
Pin #
Name
Description
ZL30414
Data Sheet
4
Zarlink Semiconductor Inc.
33
GND
Ground. 0 volt
34
VDD
Positive Digital Power Supply. +3.3 V 10%
35
C19o
C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS
clock at 19.44 MHz.
36
GND
Ground. 0 volt
37
LOCK
Lock Indicator (CMOS Output). This output goes high when PLL is frequency
locked to the input reference C19i.
38
GND
Ground. 0 volt
39
GND
Ground. 0 volt
40
NC
No internal bonding Connection. Leave unconnected.
41
GND
Ground. 0 volt
42
VDD
Positive Digital Power Supply. +3.3 V 10%
43
GND
Ground. 0 volt
44
VCC
Positive Analog Power Supply. +3.3 V 10%
45
GND
Ground. 0 volt
46
VDD
Positive Digital Power Supply. +3.3 V 10%
47
VCC
Positive Analog Power Supply. +3.3 V 10%
48
GND
Ground. 0 volt
49
VCC
Positive Analog Power Supply. +3.3 V 10%.
50
51
C622oN-D
C622oP-D
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
52
GND
Ground. 0 volt
53
VCC
Positive Analog Power Supply. +3.3 V 10%.
54
55
C622oP-C
C622oN-C
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
56
GND
Ground. 0 volt
57
VCC
Positive Analog Power Supply. +3.3 V 10%.
58
59
C622oN-B
C622oP-B
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
Pin Description Table (continued)
Pin #
Name
Description
ZL30414
Data Sheet
5
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30414 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block
diagram of the ZL30414 is shown in Figure 1 and a brief description is presented in the following sections.
1.1 Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit.
1.2 Lock Indicator
The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i
and the VCO frequency. When the VCO frequency is less than 300 ppm apart from the input reference frequency
then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds 1000 ppm.
1.3 Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an
input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external
capacitor and resistor connected to the LPF pin and ground as shown in Figure 3.
Figure 3 - Loop Filter Elements
60
GND
Ground. 0 volt
61
VCC
Positive Analog Power Supply. +3.3 V 10%.
62
63
C622oP-A
C622oN-A
C622 Clock Output (LVPECL). These outputs provide a differential LVPECL
clock at 622.08 MHz. Unused LVPECL port should be left unterminated to
decrease supply current.
64
GND
Ground. 0 volt
65
NC
No internal bonding Connection. Leave unconnected.
Pin Description Table (continued)
Pin #
Name
Description
R
F
C
F
ZL30414
LPF
R
F
=8.2 k
, C
F
=470 nF
Filter
Loop
Frequency
and Phase
Detector
VCO
ZL30414
Data Sheet
6
Zarlink Semiconductor Inc.
1.4 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
1.5 Output Interface Circuit
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at
622.08 MHz, one CML differential clock at 155.52 MHz and a single-ended 19.44 MHz output clock. This block
provides also a 19.44 MHz feedback clock that closes PLL loop. Each output clock can be enabled or disabled
individually with the associated Output Enable pin.
To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be
disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
Output Clocks
Output Enable Pins
C622oP/N-A
C622oEN-A
C622oP/N-B
C622oEN-B
C622oP/N-C
C622oEN-C
C622oP/N-D
C622oEN-D
C155oP/N
C155oEN
C19o
C19oEN
Table 1 - Output Enable Control
ZL30414
Data Sheet
7
Zarlink Semiconductor Inc.
2.0 ZL30414 Performance
The following are some of the ZL30414 performance indicators that complement results listed in the Characteristics
section of this data sheet.
2.1 Input Jitter Tolerance
Jitter tolerance is a measure of the PLL's ability to operate properly (i.e., remain in lock and/or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. The
input jitter tolerance of the ZL30414 is shown in Figure 4. On this graph, the single line at the top represents
measured input jitter tolerance and the three overlapping lines below represent minimum input jitter tolerance for
OC-192, OC-48, and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to
accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
ZL30414
Data Sheet
8
Zarlink Semiconductor Inc.
2.2 Jitter Transfer Characteristic
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a
PLL. This ratio is expressed in dB and it characterizes the PLLs ability to attenuate (filter) jitter. The jitter transfer
characteristic for the ZL30414 configured with recommended loop filter components (R
F
=8.2 k
, C
F
=470 nF) is
shown in Figure 5. The plotted curves represent jitter transfer characteristics over the recommended voltage (3.0 V
to 3.6 V) and temperature (-40C to 85C) ranges.
Figure 5 - Jitter Transfer Characteristic
ZL30414
Data Sheet
9
Zarlink Semiconductor Inc.
3.0 Applications
3.1 Ultra-Low Jitter SONET/SDH Equipment Clocks
The ZL30414 functionality and performance complements the entire family of the Zarlink's advanced network
synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical
interfaces operating up to OC-192/STM-64 rate (10 Gbit/s). The ZL30414 in combination with the MT90401 or the
ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks
suitable for network synchronization (see Figure 6) .
Figure 6 - SONET/SDH Equipment Clock
MT90401
ZL30414
C155o CML
622.08 MHz
19.44 MHz
C622oA LVPECL
C622oB LVPECL
C622oC LVPECL
C622oD LVPECL
C19o CMOS
C19i
C19o CMOS
C155o LVDS
C34o/C44o CMOS
C16o CMOS
C8o CMOS
C6o CMOS
19.44 MHz
C2o CMOS
C1.5o CMOS
F8o CMOS
F0o CMOS
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
C4o CMOS
34.368 MHz or 44.736 MHz
16.384 MHz
8.192 MHz
6.312 MHz
4.096 MHz
2.048 MHz
1.544 MHz
8 kHz
8 kHz
PRI
SEC
PRIOR
SECOR
LOCK
HOLDOVER
RefSel
RefAlign
R
F
LPF
C
F
C
1
5
5
o
E
N
155.52 MHz
C
6
2
2
o
E
N
-
A
C
6
2
2
o
E
N
-
B
C
6
2
2
o
E
N
-
C
C
6
2
2
o
E
N
-
D
C
1
9
o
E
N
D
S
C
S
R
/
W
A
0
-
A
6
D
0
-
D
7
uP
Data Port
Controller Port
Synchronization
Reference
Clocks
Note: Only main functional connections are shown
20 MHz
C
2
0
i
F16o CMOS
OCXO
8 kHz
or
ZL30407
L
O
C
K
ZL30414
Data Sheet
10
Zarlink Semiconductor Inc.
The ZL30414 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure
7).
Figure 7 - SONET/SDH Line Card
MT9046
ZL30414
C19i
C19o CMOS
C16o CMOS
C8o CMOS
C6o CMOS
19.44 MHz
C2o CMOS
C1.5o CMOS
F8o CMOS
F0o CMOS
C4o CMOS
16.384 MHz
8.192 MHz
6.312 MHz
4.096 MHz
2.048 MHz
1.544 MHz
8 kHz
8 kHz
PRI
SEC
LOCK
HOLDOVER
RSEL
R
1
LPF
C
1
C
1
5
5
o
E
N
C
6
2
2
o
E
N
-
A
C
6
2
2
o
E
N
-
B
C
6
2
2
o
E
N
-
C
C
6
2
2
o
E
N
-
D
C
1
9
o
E
N
M
S
1
F
S
2
F
L
O
C
K
uC
Synchronization
Reference
Clocks
Note: Only main functional connections are shown
20 MHz
F16o CMOS
TCXO
8 kHz
C
2
R
1
= 680
C
1
= 820 nF
C
2
= 22 nF
C20i
M
S
2
F
S
1
P
C
C
i
Hardware Control
T
C
L
R
C155o CML
622.08 MHz
19.44 MHz
C622oA LVPECL
C622oB LVPECL
C622oC LVPECL
C622oD LVPECL
C19o CMOS
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
L
O
C
K
ZL30414
Data Sheet
11
Zarlink Semiconductor Inc.
3.2 Recommended Interface circuit
3.2.1 LVPECL to LVPECL Interface
The C622oP/N-A, C622oP/N-B, C622oP/N-B, and C622oP/N-D outputs provide differential LVPECL clocks at
622.08 MHz. The LVPECL output drivers require a 50
termination connected to the Vcc-2V source for each
output terminal at the terminating end as shown below. The terminating resistors should be placed as close as
possible to the LVPECL receiver.
Figure 8 - LVPECL to LVPECL Interface
3.2.2 CML to CML Interface
The C155o output provides a differential CML/LVDS compatible clock at 155.52 MHz. The output drivers require a
50
load at the terminating end if the receiver is CML type.
Figure 9 - CML to CML Interface
LVPECL
LVPECL
ZL30414
Z=50
Z=50
C622oP-A
C622oN-A
Receiver
GND
Typical resistor values: R1 = 130
, R2 =82
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1 uF
+3.3 V
Driver
622.08 MHz
ZL30414
CML
Z=50
CML
50
C155oP
C155oN
Driver
GND
VCC
Receiver
0.1 uF
+3.3 V
50
Z=50
0.1 uF
0.1 uF
Low impedance
DC bias source
155.52 MHz
ZL30414
Data Sheet
12
Zarlink Semiconductor Inc.
3.2.3 CML to LVDS Interface
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V
CM
(common mode voltage)
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
Figure 10 - LVDS Termination
3.2.4 CML to LVPECL Interface
The CML output can drive LVPECL input as is shown in Figure 11. The terminating resistors should be placed as
close as possible to the LVPECL receiver.
Figure 11 - CML to LVPECL Interface
ZL30414
CML
Z=50
Z=50
Driver
0.1 uF
+3.3 V
GND
VCC
LVDS
10 nF
10 nF
Receiver
R1
R2
VCC=+3.3 V
R1
R2
100
Typical resistor values: R1 = 16 k
, R2 = 10 k
C155oP
C155oN
155.52 MHz
LVPECL
CML
ZL30414
Z=50
Z=50
Receiver
GND
Typical resistor values: R1 = 82
, R2 =130
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1 uF
+3.3 V
Driver
10 nF
10 nF
C155oP
C155oN
155.52 MHz
ZL30414
Data Sheet
13
Zarlink Semiconductor Inc.
3.3 Tristating LVPECL Outputs
The ZL30414 has four differential 622.08 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-
12/OC-48/OC-192 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are
required, a user can disable unused LVPECL outputs on the ZL30414 by pulling the corresponding enable pins low.
When disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.
For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling can be used as
shown in Figure 12. Typically this might be required in hot swappable applications.
Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC
coupling capacitors. During disable mode (C622oEN pin pulled low) those capacitors present infinite impedance to
the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6
are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the
LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,
R5 and R6 should not be populated.
Figure 12 - Tristatable LVPECL Outputs
Z=50
Z=50
C622oEN
ZL30414
0.1 u
C1
0.1 u
C2
R4
82.5
R6
82.5
R5
127
R3
127
R1
200
R2
200
3.3 V 3.3 V
ZL30414
Data Sheet
14
Zarlink Semiconductor Inc.
3.4 Power Supply and BIAS Circuit Filtering Recommendations
Figure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter
performance. The level of required filtering is subject to further optimization and simplification. Please check
Zarlink's web site for updates.
Figure 13 - Power Supply and BIAS Circuit Filtering
50
52
54
56
58
60
62
64
34
40
44
46
48
42
32
30
28
26
24
22
20
18
GND
VDD
GND
VCC
VDD
VDD
GND
GND
GND
GND
VCC
VDD
VD
D
VD
D
GN
D
VC
C
GN
D
VC
C
GN
D
VC
C
GN
D
VC
C
16
14
12
10
6
4
2
8
GND
VCC1
GND
VCC2
GND
GND
GND
GN
D
GN
D
GN
D
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Ferrite Bead
0.1 uF
33 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Notes:
1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same ground plane.
2. Select Ferrite Bead with I
DC
> 400 mA and R
DC
in a range from 0.10
to 0.15
+3.3 V Power Rail
ZL30414
0.1 uF
GN
D
GND
BIAS
220
11
VCC
0.1 uF
36
38
+
0.1 uF
4.7
10 uF
+
+
33 uF
+
33 uF
0.1 uF
0.1 uF
VD
D
ZL30414
Data Sheet
15
Zarlink Semiconductor Inc.
4.0 Characteristics
Voltages are with respect to ground unless otherwise stated.
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Voltages are with respect to ground unless otherwise stated.
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings
Characteristics
Sym.
Min.
Max.
Units
1
Supply voltage
V
DDR
, V
CCR
TBD
TBD
V
2
Voltage on any pin
V
PIN
-0.5
V
CC
+ 0.5
V
DD
+ 0.5
V
3
Current on any pin
I
PIN
-0.5
30
mA
4
ESD Rating
V
ESD
1250
V
5
Storage temperature
T
ST
-55
125
C
6
Package power dissipation
P
PD
1.8
W
Recommended Operating Conditions
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Operating Temperature
T
OP
-40
25
+85
C
2
Positive Supply
V
DD,
V
CC
3.0
3.3
3.6
V
DC Electrical Characteristics
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Supply Current
I
DD
+I
CC
146
mA
LVPECL, CML
drivers
disabled and
unterminated
2
Incremental Supply Current to
single LVPECL driver (driver
enabled and terminated, see
Figure 8)
I
LVPECL
37
mA
Note 1
Note 2
3
Incremental Supply Current to
CML driver (driver enabled and
terminated, see Figure 9)
I
CML
26
mA
Note 3
4
CMOS: High-level input
voltage
V
IH
0.7V
DD
V
DD
V
5
CMOS: Low-level input
voltage
V
IL
0
0.3V
DD
V
6
CMOS: Input leakage current
I
IL
1
5
uA
V
I
= V
DD
or 0 V
ZL30414
Data Sheet
16
Zarlink Semiconductor Inc.
-
: Voltages are with respect to ground unless otherwise stated.
-
:Typical figures are for design aid only: not guaranteed and not subject to production testing.
-
Supply voltage and operating temperature are as per Recommended Operating Conditions
-
Note 1: The I
LVPECL
current is determined by the termination network connected to LVPECL outputs. More than 25% of this current
flows outside the chip and it does not contribute to the internal power dissipation.
-
Note 2: LVPECL outputs terminated with Z
T
= 50
resistors biased to V
CC
-2V (see Figure 8)
-
Note 3: CML outputs terminated with Z
T
= 50
resistors connected to low impedance DC bias voltage source (see Figure 9)
7
CMOS: Input bias current for
pulled-down inputs:
C622oEN-A, C622oEN-C,
C622oEN-D, OC-CLKoEN
I
B-PU
300
uA
V
I
= V
DD
8
CMOS: Input bias current for
pulled-up inputs: , C622oEN-B,
C19oEN
I
B-PD
90
uA
V
I
= 0V
9
CMOS: High-level output
voltage
V
OH
2.4
V
I
OH
= 8 mA
10
CMOS: Low-level output
voltage
V
OL
0.4
V
I
OL
= 4 mA
11
LOCK pin: High-level output
voltage
V
OH
2.4
I
OH
= 0.5 mA
12
LOCK pin: Low-level output
voltage
V
OL
0.4
I
OL
= 0.5 mA
13
CMOS: C19o output rise time
T
R
1.8
3.3
ns
18 pF load
14
CMOS: C19o output fall time
T
F
1.1
1.4
ns
18 pF load
15
LVPECL: Differential output
voltage (622.08 MHz)
IV
OD_LVPECL
I
1.17
V
Note 2
16
LVPECL: Offset voltage
(622.08 MHz)
V
OS_LVPECL
Vcc-
1.31
Vcc-
1.20
Vcc-
1.09
V
Note 2
17
LVPECL: Output rise/fall times
(622.08 MHz)
T
RF
170
ps
Note 2
18
CML: Differential output
voltage (155.52 MHz)
IV
OD_CML
I
0.73
V
Note 3
19
CML: Offset voltage
(155.52 MHz)
V
OS_CML
Vcc-
0.58
Vcc-
0.54
Vcc-
0.50
V
Note 3
20
CML: Output rise/fall times
(155.52 MHz)
T
RF
220
ps
Note 3
DC Electrical Characteristics
(continued)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
ZL30414
Data Sheet
17
Zarlink Semiconductor Inc.
Voltages are with respect to ground unless otherwise stated.
Figure 14 - Output Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics
- Output Timing Parameters Measurement Voltage Levels
Characteristics
Sym
CMOS
LVPECL
CML
Units
1
Threshold Voltage
V
T-CMOS
V
T-LVPECL
V
T-CML
0.5V
DD
0.5V
OD_LVPECL
0.5V
OD_CML
V
2
Rise and Fall Threshold Voltage High
V
HM
0.7V
DD
0.8V
OD_LVPECL
0.8V
OD_CML
V
3
Rise and Fall Threshold Voltage Low
V
LM
0.3V
DD
0.2V
OD_LVPECL
0.2V
OD_CML
V
V
T
All Signals
V
HM
V
LM
t
IF
, t
OF
t
IR
, t
OR
Timing Reference Points
ZL30414
Data Sheet
18
Zarlink Semiconductor Inc.
Supply voltage and operating temperature are as per Recommended Operating Conditions
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Figure 15 - C19i Input to C19o, C155o and C622o Output Timing
AC Electrical Characteristics
- C19i Input to C19o, C155o and C622o Output Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
C19i to C19o delay
t
C19D
6.2
7.2
8.2
ns
2
C19i to C155o delay
tc
155D
3
4
5
ns
3
C19i to C622oA delay
t
C622D
0
0.8
1.6
ns
4
C155o duty cycle
d
C155L
48
50
52
%
5
C622o duty cycle
d
C622L
48
50
52
%
C622oA
V
T-LVPECL
C19i
V
T-CMOS
(19.44 MHz)
t
C19D
C19o
V
T-CMOS
(19.44 MHz)
t
C622D
(622.08 MHz)
C155o
V
T-CML
t
C155D
(155.52 MHz)
ZL30414
Data Sheet
19
Zarlink Semiconductor Inc.
Supply voltage and operating temperature are as per Recommended Operating Conditions
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Figure 16 - C622oB, C622oC, C622oD Outputs Timing
AC Electrical Characteristics
- C622 Clocks Output Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
C622oA to C622oB
t
C622D-AB
-50
0
+50
ps
2
C622oA to C622oC
t
C622D-AC
-50
0
+50
ps
3
C622oA to C622oD
t
C622D-AD
-50
0
+50
ps
C622oD
V
T-LVPECL
C622oC
t
C622D-AB
C622oB
C622oA
V
T-LVPECL
V
T-LVPECL
V
T-LVPECL
t
C622D-AC
t
C622D-AD
Note: All output clocks have nominal 50% duty cycle.
ZL30414
Data Sheet
20
Zarlink Semiconductor Inc.
Performance Characteristics
- Functional
(V
CC
= 3.3 V 10%; T
A
= -40 to 85
C )
Performance Characteristics
: Output Jitter Generation - GR-253-CORE conformance
(V
CC
= 3.3V 10%;
T
A
= -40 to 85
C )
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Loop Filter components: R
F
=8.2 k
, C
F
=470 nF
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Pull-in range
1000
ppm
At nominal input
reference frequency
C19i = 19.44 MHz
2
Lock Time
300
ms
GR-253-CORE Jitter Generation Requirements
ZL30414 Jitter Generation
Performance
Interface
(Category II)
Jitter
Measurement
Filter
Limit in
UI
Equivalent
limit in time
domain
Typ.
Max.
Units
1
OC-192
STS-192
50 kHz - 80 MHz
0.1 UI
PP
10.0
-
7.31
ps
P-P
0.01 UI
RMS
1.0
0.52
0.94
ps
RMS
2
OC-48
STS-48
12 kHz - 20 MHz
0.1 UI
PP
40.2
-
7.32
ps
P-P
0.01 UI
RMS
4.02
0.58
0.83
ps
RMS
3
OC-12
STS-12
12 kHz - 5 MHz
0.1 UI
PP
161
-
4.37
ps
P-P
0.01 UI
RMS
16.1
0.34
0.60
ps
RMS
ZL30414
Data Sheet
21
Zarlink Semiconductor Inc.
Performance Characteristics
: Output Jitter Generation - G.813 conformance (Option 1 and 2)
(V
CC
= 3.3V
10%; T
A
= -40 to 85
C )
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Loop Filter components: R
F
=8.2 k
, C
F
=470 nF
G.813 Jitter Generation Requirements
ZL30414 Jitter Generation
Performance
Interface
Jitter
Measurement
Filter
Limit in
UI
Equivalent
limit in time
domain
Typ.
Max.
Units
Option 1
1
STM-64
4 MHz to 80 MHz
0.1 UIpp
10.0
-
6.95
ps
P-P
0.49
0.89
ps
RMS
20 kHz to 80 MHz
0.5 UIpp
50.2
-
11.5
ps
P-P
0.82
1.04
ps
RMS
2
STM-16
1 MHz to 20 MHz
0.1 UIpp
40.2
-
6.40
ps
P-P
0.50
0.68
ps
RMS
5 kHz to 20 MHz
0.5 UIpp
201
-
8.67
ps
P-P
0.68
1.06
ps
RMS
3
STM-4
250 kHz to 5 MHz
0.1 UIpp
161
-
3.33
ps
P-P
0.26
0.42
ps
RMS
1 kHz to 5 MHz
0.5 UIpp
804
-
19.1
ps
P-P
1.51
2.88
ps
RMS
Option 2
5
STM-64
4 MHz to 80 MHz
0.1 UIpp
10.0
-
6.95
ps
P-P
0.49
0.89
ps
RMS
20 kHz to 80 MHz
0.3 UIpp
30.1
-
11.5
ps
P-P
0.82
1.04
ps
RMS
6
STM-16
12 kHz - 20 MHz
0.1 UIpp
40.2
-
7.32
ps
P-P
0.58
0.83
ps
RMS
7
STM-4
12 kHz - 5 MHz
0.1 UIpp
161
-
4.37
ps
P-P
0.34
0.60
ps
RMS
ZL30414
Data Sheet
22
Zarlink Semiconductor Inc.
Performance Characteristics
: Output Jitter Generation - ETSI EN 300 462-7-1conformance
(V
CC
= 3.3V
10%; T
A
= -40 to 85
C )
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Loop Filter components: R
F
=8.2 k
, C
F
=470 nF
EN 300 462-7-1 Jitter Generation Requirements
ZL30414 Jitter Generation
Performance
Interface
Jitter
Measurement
Filter
Limit in
UI
Equivalent
limit in time
domain
Typ.
Max.
Units
1
STM-16
1 MHz to 20 MHz
0.1 UIpp
40.2
-
6.40
ps
P-P
0.50
0.68
ps
RMS
5 kHz to 20 MHz
0.5UIpp
201
-
8.67
ps
P-P
0.68
1.06
ps
RMS
2
STM-4
250 kHz to 5 MHz
0.1 UIpp
161
-
3.33
ps
P-P
0.26
0.42
ps
RMS
1 kHz to 5 MHz
0.5 UIpp
804
-
19.1
ps
P-P
1.51
2.88
ps
RMS
c Zarlink Semiconductor 2005 All rights reserved.
APPRD.
ISSUE
DATE
ACN
Package Code
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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Purchase of Zarlink's I
2
C components conveys a licence under the Philips I
2
C Patent rights to use these components in and I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products
visit our Web Site at
Document Outline
- Features
- Applications
- Figure 1 - Functional Block Diagram
- Description
- Figure 2 - TQFP 64 pin (Top View)
- Pin Description
- 1.0 Functional Description
- 1.1 Frequency/Phase Detector
- 1.2 Lock Indicator
- 1.3 Loop Filter
- Figure 3 - Loop Filter Elements
- 1.4 VCO
- 1.5 Output Interface Circuit
- Table 1 - Output Enable Control
- 2.0 ZL30414 Performance
- 2.1 Input Jitter Tolerance
- Figure 4 - Input Jitter Tolerance
- 2.2 Jitter Transfer Characteristic
- Figure 5 - Jitter Transfer Characteristic
- 3.0 Applications
- 3.1 Ultra-Low Jitter SONET/SDH Equipment Clocks
- Figure 6 - SONET/SDH Equipment Clock
- Figure 7 - SONET/SDH Line Card
- 3.2 Recommended Interface circuit
- 3.2.1 LVPECL to LVPECL Interface
- Figure 8 - LVPECL to LVPECL Interface
- 3.2.2 CML to CML Interface
- Figure 9 - CML to CML Interface
- 3.2.3 CML to LVDS Interface
- Figure 10 - LVDS Termination
- 3.2.4 CML to LVPECL Interface
- Figure 11 - CML to LVPECL Interface
- 3.3 Tristating LVPECL Outputs
- Figure 12 - Tristatable LVPECL Outputs
- 3.4 Power Supply and BIAS Circuit Filtering Recommendations
- Figure 13 - Power Supply and BIAS Circuit Filtering
- 4.0 Characteristics
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Electrical Characteristics
- AC Electrical Characteristics- Output Timing Parameters Measurement Voltage Levels
- Figure 14 - Output Timing Parameter Measurement Voltage Levels
- AC Electrical Characteristics- C19i Input to C19o, C155o and C622o Output Timing
- Figure 15 - C19i Input to C19o, C155o and C622o Output Timing
- AC Electrical Characteristics- C622 Clocks Output Timing
- Figure 16 - C622oB, C622oC, C622oD Outputs Timing
- Performance Characteristics - Functional (VCC = 3.3V 10%; TA = -40 to 85C )
- Performance Characteristics : Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3V 10%...
- Performance Characteristics : Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC ...
- Performance Characteristics : Output Jitter Generation - ETSI EN 3
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