Document Outline
- Features
- Applications
- Description
- Figure 1 - Functional Block Diagram
- Figure 2 - Pin Connections
- Table 1 - Summary of ZL490x0/1 Product Family
- Functional Description
- Automatic Gain Control (AGC) Circuit
- Filter and Decoder Section
- Energy Detection
- Serial Data (SD) Output
- Powerdown Mode (ZL4901x/4903x)
- Table 2 - Serial Decode Bit Table
- Table 3 - Powerdown Mode
- Table 4 - Call Progress Tones
- Oscillator
- Applications
- Figure 3 - Application Circuit for ZL4902x
- Figure 4 - Timing Diagram
- Figure 5 - ACK to SD Timing
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Wide dynamic range (50dB) DTMF Receiver
Call progress (CP) detection via cadence
indication
4-bit synchronous serial data output
Software controlled guard time for ZL490x0
Internal guard time circuitry for ZL490x1
Powerdown option (ZL4901x & ZL4903x)
3.579MHz crystal or ceramic resonator (ZL4903x
and ZL4902x)
External clock input (ZL4901x)
Guarantees non-detection of spurious tones
Applications
Integrated telephone answering machine
End-to-end signalling
Fax Machines
Description
The ZL490xx is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
signalling. The ZL490x0 provides an early steering
(ESt) logic output to indicate the detection of a DTMF
signal and requires external software guard time to
validate the DTMF digit. The ZL490x1, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The SD
pin is multiplexed with call progress detector output. In
the presence of supervisory tones, the call progress
September 2003
Ordering Information
ZL49010DAA
8 Pin PDIP
Tubes
ZL49011DAA
8 Pin PDIP
Tubes
ZL49020DAA
8 Pin PDIP
Tubes
ZL49021DAA
8 Pin PDIP
Tubes
ZL49030DCA
18 Pin SOIC
Tubes
ZL49030DCB
18 Pin SOIC
Tape & Reel
ZL49030DDA
20 Pin SSOP Tubes
ZL49030DDB
20 Pin SSOP Tape & Reel
ZL49031DCA
18 Pin SOIC
Tubes
ZL49031DCB
18 Pin SOIC
Tape & Reel
ZL49031DDA
20 Pin SSOP Tubes
ZL49031DDB
20 Pin SSOP Tape & Reel
-40
C to +85
C
ZL49010/1, ZL49020/1, ZL49030/1
Wide Dynamic Range DTMF Receiver
Data Sheet
Figure 1 - Functional Block Diagram
VDD
VSS
OSC2
1.
ZL49010/1 and ZL49030/1 only.
2.
ZL49020/1 and ZL49030/1 only.
Voltage
Bias Circuit
AGC
Anti-
alias
Filter
High
Group
Filter
Low
Group
Filter
Steering
Circuit
Digital
Detector
Algorithm
Code
Converter
and
Latch
Digital
Guard
Time
3
Parallel to
Serial
Converter
& Latch
Mux
Energy
Detection
Oscillator
and
Clock
Circuit
To All Chip Clocks
Dial
Tone
Filter
ESt
DStD
ACK
SD
1
2
or
3.
ZL490x1 only.
PWDN
OSC1
(CLK)
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
2
Zarlink Semiconductor Inc.
detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be
processed by an external microcontroller to identify specific call progress signals. The ZL4902x and ZL4903x can
be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for
the ZL4901x and ZL4903x.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
4903x
4902x
4901x
2
1
1
INPUT
DTMF/CP Input. Input signal must be AC coupled via capacitor.
4
2
-
OSC2
Oscillator Output.
6
3
3
OSC1
(CLK)
Oscillator/Clock Input. This pin can either be driven by:
1)
an external digital clock with defined input logic levels. OSC2
should be left open.
2)
connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
9
4
4
V
SS
Ground. (0V)
11
5
5
SD
Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
13
6
6
ACK
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
15
7
7
ESt
(ZL490x0)
DStD
(ZL490x1)
Early Steering Output. A logic high on ESt indicates that a DTMF
signal is present. ESt is at logic low in powerdown state.
Delayed Steering Output. A logic high on DStD indicates that a
valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
10
18
17
16
15
14
13
12
11
VDD
NC
NC
ESt/DStD
NC
ACK
NC
SD
NC
1
2
3
4
5
6
7
8
9
NC
INPUT
PWDN
OSC2
NC
OSC1
NC
NC
VSS
INPUT
PWDN
CLK
VSS
VDD
ACK
SD
INPUT
OSC2
OSC1
VSS
VDD
ESt/
ACK
SD
ZL49010/1
ZL49020/1
ZL49030/1
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
NC
NC
INPUT
PWDN
NC
NC
OSC1
OSC2
VSS
20 PIN SSOP
NC
VDD
NC
NC
ACK
SD
NC
NC
ESt/DStD
DStD
ESt/
DStD
ZL49030/1
NC
NC
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
3
Zarlink Semiconductor Inc.
Functional Description
The ZL490xxs are high performance and low power consumption DTMF receivers. These devices provide wide
dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy
detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following
the unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output
is routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to
separate the input DTMF signal into high and low group tones. The high group and low group tones are then
verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection
stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be
shifted out serially by applying external clock pulses.
Automatic Gain Control (AGC) Circuit
As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With
large input signal amplitude (between 0 and approximately -30dBm for each tone of the composite signal), the AGC
is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the
input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit.
Filter and Decoder Section
The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection.
The composite dual-tone signal is further split into its individual high and low frequency components by two 6
th
order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate
18
8
8
V
DD
Positive Power Supply (5V Typ.) Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across V
DD
and V
SS
are therefore recommended.
1,5,7,8,
10, 12,
14,16,
17
-
-
NC
No Connection. Pin is unconnected internally.
3
-
2
PWDN Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
'0' to power down device.
Device
Type
8 Pin
18 Pin
20 Pin
PWDN
2 Pin
OSC
Ext
CLK
ESt
DStD
ZL49010
x
x
x
x
ZL49011
x
x
x
x
ZL49020
x
x
x
x
ZL49021
x
x
x
x
ZL49030
x
x
x
x
x
x
ZL49031
x
x
x
x
x
x
Table 1 - Summary of ZL490x0/1 Product Family
Pin Description (continued)
Pin #
Name
Description
4903x
4902x
4901x
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
4
Zarlink Semiconductor Inc.
output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a
digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For
ZL490x0, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,
indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt
pin to go low. For ZL490x1, an internal delayed steering counter validates the early steering signal after a
predetermined guard time which requires no external components. The delayed steering (DStD) will go high only
when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal
due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD
output will go low only after this validation period.
Energy Detection
The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists
of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal
comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator
ensure the SD output will remain at high even though the input signal is changing. When the input signal is
removed, the SD output will go low following the integrator decay time. Short decay time enables the signal
envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for
specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause
the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.
As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected
at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse
applied at the ACK pin.
Serial Data (SD) Output
When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the
ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The
rising edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit
on the SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure
5). If less than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be
valid. Clock pulses should be applied to clock out any remaining data bits to resume normal operation. Any
transitions in excess of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at
logic low. The 4-bit binary representing all 16 standard DTMF digits are shown in Table .
Powerdown Mode (ZL4901x/4903x)
The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in
use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be
kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).
F
LOW
F
HIGH
DIGIT
b
3
b
2
b
1
b
0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
852
1477
9
1
0
0
1
Table 2 - Serial Decode Bit Table
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
5
Zarlink Semiconductor Inc.
Table 3 - Powerdown Mode
Table 4 - Call Progress Tones
Oscillator
The ZL4902x/4903x can be used in both external clock or two pin oscillator mode. In two pin oscillator mode, the
oscillator circuit is completed by connecting either a 3.579MHz crystal or ceramic resonator across OSC1 and
OSC2 pins. It is also possible to configure a number of these devices (4 maximum) employing only a single
oscillator crystal. The OSC2 output of the first device in the chain is connected to the OSC1 input of the next
device. Subsequent devices are connected similarily. The oscillator circuit can also be driven by an 3.579MHz
external clock applied on pin OSC 1. The OSC2 pin should be left open.
For ZL4901x devices, the CLK input is driven directly by an 3.579MHz external digital clock.
941
1336
0
1
0
1
0
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
852
1633
C
1
1
1
1
941
1633
D
0
0
0
0
0= LOGIC LOW, 1= LOGIC HIGH
Note: b0=LSB of decoded DTMF digit and shifted out first.
ACK (input)
PWDN (input)
ESt/DStD (output)
SD (output)
ZL4901x/4903x
status
low
low
Refer to Fig. 4 for
timing waveforms
Refer to Fig. 4 for
timing waveforms
normal operation
low
high
+
low
low
powerdown mode
high
low
low
undefined
undefined
high
high
undefined
undefined
undefined
Note:
+
=enters powerdown mode on the rising edge.
Frequency 1 (Hz)
Frequency 2 (Hz)
On/Off
Description
350
440
continuous
North American Dial Tones
425
---
continuous
European Dial Tones
400
---
continuous
Far East Dial Tones
480
620
0.5s/0.5s
North American Line Busy
440
---
0.5s/0.5s
Japanese Line Busy
480
620
0.25s/0.25s
North American Reorder Tones
440
480
2.0s/4.0s
North American Audible Ringing
480
620
0.25s/0.25s
North American Reorder Tones
F
LOW
F
HIGH
DIGIT
b
3
b
2
b
1
b
0
Table 2 - Serial Decode Bit Table (continued)
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
6
Zarlink Semiconductor Inc.
Applications
The circuit shown in Figure 3 illustrates the use of a ZL4902x in a typical receiver application. It requires only a
coupling capacitor (C1) and a crystal or ceramic resonator (X1) to complete the circuit.
The ZL490x0 is designed for user who wishes to tailor the guard time for specific applications. When a DTMF
signal is present, the ESt pin will go high. An external microcontroller monitors ESt in real time for a period of time
set by the user. A guard time algorithm must be implemented such that DTMF signals not meeting the timing
requirements are rejected. The ZL490x1 uses an internal counter to provide a preset DTMF validation period. It
requires no external components. The DStD output high indicates that a valid DTMF digit has been detected.
Figure 3 - Application Circuit for ZL4902x
DTMF/CP Input
C1
X1
1
2
3
4
8
7
6
5
INPUT
OSC2
OSC1
V
SS
V
DD
ESt/DStD
ACK
SD
V
DD
COMPONENTS LIST:
C
1
= 0.1
F
10 %
X1 = Crystal or Resonator (3.579MHz)
To microprocessor or
microcontroller
ZL4902x
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
7
Zarlink Semiconductor Inc.
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing
Absolute Maximum Ratings
-
Voltages are with respect to V
SS
=0V unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
DC Power Supply Voltage
V
DD
-V
SS
6
V
2
Voltage on any pin (other than supply)
V
I/O
-0.3
6.3
V
3
Current at any pin (other than supply)
I
I/O
10
mA
4
Storage temperature
T
S
-65
150
C
5
Package power dissipation
P
D
500
mW
Recommended Operating Conditions
-
Voltages are with respect to V
SS
=0V unless otherwise stated
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
Positive Power Supply
V
DD
4.75
5.0
5.25
V
2
Oscillator Clock Frequency
f
OSC
3.579
MHz
3
Oscillator Frequency Tolerance
f
OSC
0.1
%
4
Operating Temperature
T
d
-40
25
85
C
DC Electrical Characteristics
- Voltages are with respect to V
DD
=5V
5%,V
SS
=0V, and temperature -40 to 85
C, unless
otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Operating supply current
I
DD
3
8
mA
2
Standby supply current
I
DDQ
30
100
A
PWDN=5V, ACK=0V
ESt/DStD = SD = 0V
3a
Input logic 1
V
IH
4.0
V
3b
Input logic 1
(for OSC1 input only)
V
IH
3.5
V
ZL4902x/ZL4903x
4a
Input logic 0
V
IL
1.0
V
4b
Input logic 0
(for OSC1 input only)
V
IL
1.5
V
ZL4902x/ZL4903x
5
Input impedance (pin 1)
R
IN
50
k
6
Pull-down Current
(PWDN, ACK pins)
I
PD
25
A
with internal pull-down
resistor of approx.
200k
. PWDN/ACK =
5V
7
Output high (source) current
I
OH
0.4
4.0
mA
V
OUT
=V
DD
-0.4V
8
Output low (sink) current
I
OL
1.0
9.0
mA
V
OUT
=V
SS
+0.4V
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
8
Zarlink Semiconductor Inc.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing
* Test Conditions
1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load.
2. Data sequence consists of all DTMF digits.
3. Tone on = 40 ms, tone off = 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by
1.5%
2 Hz.
7. Bandwidth limited (0-3 kHz) Gaussian noise.
8. Precise dial tone frequencies are 350 Hz and 440 Hz (
2%).
9. Referenced to lowest level frequency component in DTMF signal.
10. Referenced to the minimum valid accept level.
11. Both tones must be within valid input signal range.
12. Internal guard time for ZL490x1 = 20ms.
13. Timing parameters are measured with 70pF load at SD output.
14. Time duration between PWDN pin changes from `1` to `0` and ESt/DStD becomes active.
15. Guaranteed by design and characterization. Not subject to production testing.
16. Value measured with an applied tone of 450 Hz.
AC Electrical Characteristics
- voltages are with respect to V
DD
=5V
5%, V
SS
=0V and temperature -40 to +85
C unless
otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions*
1
Valid input signal level
(each tone of composite signal)
-50
2.45
0
775
dBm
mV
RMS
1,2,3,5,6,12
2
Positive twist accept
8
dB
1,2,3,4,11,12,15
3
Negative twist accept
8
dB
1,2,3,4,11,12,15
4
Frequency deviation accept
1.5
%
2Hz
1,2,3,5,12
5
Frequency deviation reject
3.5
%
1,2,3,5,12,15
6
Third tone tolerance
-16
dB
1,2,3,4,5,12
7
Noise tolerance
-12
dB
7,9,12
8
Dial tone tolerance
+15
dB
8,10,12
9
Supervisory tones detect level
(Total power)
-35
dBm
16
10
Supervisory tones reject level
-50
dBm
16
11
Energy detector attack time
t
SA
1.0
6.5
ms
16
12
Energy detector decay time
t
SD
3
25
ms
16
13a
13b
Powerdown time
Powerup time
10
30
50
ms
ms
ms
IDDQ
100
A
ZL49010/ZL49030
ZL49011/ZL49031
Note 14
14
Tone present detect time (ESt
logic output)
t
DP
3
13
20
ms
ZL490x0
15
Tone absent detect time (ESt
logic output)
t
DA
3
15
ms
ZL490x0
16
Tone duration accept
(DStD logic output)
t
REC
40
ms
ZL490x1
17
Tone duration reject
(DStD logic output)
t
REC
20
ms
ZL490x1
18
Interdigit pause accept (DStD
logic output)
t
ID
40
ms
ZL490x1
19
Interdigit pause reject (DStD logic
output)
t
DO
20
ms
ZL490x1
20
Data shift rate 40-60% duty cycle
f
ACK
1.0
3.0
MHz
13,15
21
Propagation delay
(ACK to Data Bit)
t
PAD
100
140
ns
1MHz f
ACK
,
13,15
22
Data hold time (ACK to SD)
t
DH
30
50
ns
13,15
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
9
Zarlink Semiconductor Inc.
Figure 4 - Timing Diagram
INPUT
ESt
(ZL490x0)
DStD
(ZL490x1)
ACK
SD
DTMF
Tone #n
t
DP
t
REC
t
DO
DTMF
Tone #n + 1
DTMF
Tone
#n + 1
Input
Signal
t
DA
t
REC
t
ID
LSB
MSB
b
0
b
1
b
2
b
3
b
0
b
1
b
2
b
3
t
SA
t
SD
Input
Signal
Envelope
LSB
MSB
t
DO
t
ID
- maximum allowable dropout during valid DTMF signals. ZL490xx).
t
REC
t
REC
t
DA
t
DP
t
SA
t
SD
- minimum time between valid DTMF signals (ZL49011).
- maximum DTMF signal duration not detected as valid (ZL490xx).
- minimum DTMF signal duration required for valid recognition (ZL490x1).
- time to detect the absence of valid DTMF signals (ZL490x0).
- time to detect the presence of valid DTMF signals (ZL490x0).
- supervisory tone integrator attack time (ZL490xx).
- supervisory tone integrator decay time (ZL490xx).
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
10
Zarlink Semiconductor Inc.
Figure 5 - ACK to SD Timing
ESt/DStD
ACK
SD
V
IH
V
IL
V
IH
V
IL
1/
f
ACK
t
PAD
t
DH
b
0
b
1
b
2
b
3
MSB
DTMF Energy
Detect
LSB
DTMF Energy
Detect
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