Document Outline

Features
Applications
Description
- Figure 1 - ZL50016 Functional Block Diagram
Changes Summary
1.0 Pinout Diagrams
- 1.1 BGA Pinout
  - Figure 2 - ZL50016 256-Ball 17mm x 17mm PBGA (as viewed through top of package)
- 1.2 QFP Pinout
  - Figure 3 - ZL50016 256-Lead 28mm x 28mm LQFP (top view)
2.0 Pin Description
3.0 Device Overview
4.0 Data Rates and Timing
- 4.1 External High Impedance Control, STOHZ0 - 7
- 4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
  - Table 1 - CKi and FPi Configurations for Divided Clock Modes
  - Table 2 - CKi and FPi Configurations for Multiplied Clock Mode
  - Figure 4 - Input Timing when CKIN1 - 0 bits = 10Ž in the CR
  - Figure 5 - Input Timing when CKIN1 - 0 bits = 01Ž in the CR
  - Figure 6 - Input Timing when CKIN1 - 0 = 00Ž in the CR
5.0 ST-BUS and GCI-Bus Timing
6.0 Output Timing Generation
- Table 3 - Output Timing Generation
- Figure 7 - Output Timing for CKo0 and FPo0
- Figure 8 - Output Timing for CKo1 and FPo1
- Figure 9 - Output Timing for CKo2 and FPo2
- Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=Ž11Ž
7.0 Data Input Delay and Data Output Advancement
- 7.1 Input Bit Delay Programming
  - Figure 11 - Input Bit Delay Timing Diagram (ST-BUS)
- 7.2 Input Bit Sampling Point Programming
  - Figure 12 - Input Bit Sampling Point Programming
  - Figure 13 - Input Bit Delay and Factional Sampling Point
- 7.3 Output Advancement Programming
  - Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS)
- 7.4 Fractional Output Bit Advancement Programming
  - Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
- 7.5 External High Impedance Control Advancement
  - Figure 16 - Channel Switching External High Impedance Control Timing
8.0 Data Delay Through the Switching Paths
- 8.1 Variable Delay Mode
  - Table 4 - Delay for Variable Delay Mode
  - Figure 17 - Data Throughput Delay for Variable Delay
- 8.2 Constant Delay Mode
  - Figure 18 - Data Throughput Delay for Constant Delay
9.0 Connection Memory Description
10.0 Connection Memory Block Programming
- 10.1 Memory Block Programming Procedure
  - Table 5 - Connection Memory Low After Block Programming
  - Table 6 - Connection Memory High After Block Programming
11.0 Device Operation in Divided Clock and Multiplied Clock Modes
- Table 7 - ZL50016 Operating Modes
- 11.1 Divided Clock Mode Operation
- 11.2 Multiplied Clock Mode Operation
- 11.3 Output Clock Frequencies
  - Table 8 - Generated Output Frequencies
12.0 Microprocessor Port
13.0 Device Reset and Initialization
- 13.1 Power-up Sequence
- 13.2 Device Initialization on Reset
- 13.3 Software Reset
14.0 Pseudo Random Bit Generation and Error Detection
15.0 PCM A-law/u-law Translation
- Table 9 - Input and Output Voice and Data Coding
16.0 Quadrant Frame Programming
- Table 10 - Definition of the Four Quadrant Frames
- Table 11 - Quadrant Frame Bit Replacement
17.0 JTAG Port
- 17.1 Test Access Port (TAP)
- 17.2 Instruction Register
- 17.3 Test Data Registers
- 17.4 BSDL
18.0 Register Address Mapping
- Table 12 - Address Map for Registers (A13 = 0)
19.0 Detailed Register Description
- Table 13 - Control Register (CR) Bits
  - Unused
- Table 14 - Internal Mode Selection Register (IMS) Bits
- Table 15 - Software Reset Register (SRR) Bits
- Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
- Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
- Table 18 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
- Table 19 - Internal Flag Register (IFR) Bits - Read Only
- Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only
- Table 21 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
- Table 22 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits
- Table 23 - Stream Input Quadrant Frame Register 0 - 15 (SIQFR0 - 15) Bits
- Table 24 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits
- Table 25 - BER Receiver Start Register [n] (BRSR[n]) Bits
- Table 26 - BER Receiver Length Register [n] (BRLR[n]) Bits
- Table 27 - BER Receiver Control Register [n] (BRCR[n]) Bits
- Table 28 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
20.0 Memory
- 20.1 Memory Address Mappings
  - Table 29 - Address Map for Memory Locations (A13 = 1)
- 20.2 Connection Memory Low (CM_L) Bit Assignment
  - Table 30 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
  - Table 31 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
- 20.3 Connection Memory High (CM_H) Bit Assignment
  - Table 32 - Connection Memory High (CM_H) Bit Assignment
21.0 DC Parameters
22.0 AC Parameters
- Figure 19 - Timing Parameter Measurement Voltage Levels
- Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access
- Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access
- Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access
- Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access
- Figure 24 - JTAG Test Port Timing Diagram
- Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
- Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
- Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4 or 8Mbps
- Figure 28 - ST-BUS Input Timing Diagram when Operated at 16Mbps
- Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4 or 8Mbps
- Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16Mbps
- Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16Mbps
- Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16Mbps
- Figure 33 - Serial Output and External Control
- Figure 34 - Output Drive Enable (ODE)
- Figure 35 - Input and Output Frame Boundary Offset
- Figure 36 - FPo0 and CKo0 Timing Diagram
- Figure 37 - FPo1/3 and CKo1/3 Timing Diagram
- Figure 38 - FPo2 and CKo2 Timing Diagram
- Figure 39 - FPo3 and CKo3 Timing Diagram
- Figure 40 - Output Timing (ST-BUS Format)

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

· 1024 channel x 1024 channel non-blocking digital

Time Division Multiplex (TDM) switch at

4.096 Mbps, 8.192 Mbps and 16.384 Mbps or

using a combination of ports running at

2.048 Mbps, 4.096 Mbps, 8.192 Mbps and

16.384 Mbps

· 16 serial TDM input, 16 serial TDM output

streams

· Output streams can be configured as bi-

directional for connection to backplanes

· Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

· Per-stream input and output data rate conversion

selection at 2.048 Mbps, 4.096 Mbps,

8.192 Mbps or 16.384 Mbps. Input and output

data rates can differ

· Per-stream high impedance control outputs

(STOHZ) for 8 output streams

· Per-stream input bit delay with flexible sampling

point selection

· Per-stream output bit and fractional bit

advancement

· Per-channel ITU-T G.711 PCM A-Law/

µ-Law

Translation

· Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz

· Input frame pulses:61 ns, 122 ns, 244 ns

· Four frame pulse and four reference clock outputs

· Three programmable delayed frame pulse outputs

July 2005

Ordering Information

ZL50016GAC

256 Ball PBGA

Trays

ZL50016QCC

256 Lead LQFP

Trays

-40

°C to +85°C

ZL50016

Enhanced 1 K Digital Switch

Data Sheet

Figure 1 - ZL50016 Functional Block Diagram

Data Memory

Internal Registers &

Microprocessor Interface

Input Timing

Output HiZ

Test Port

Control

S/P Converter

STOHZ[7:0]

FPo[3:0]
CKo[3:0]

STio[15:0]

Connection Memory

T_I

TEL

_RD

D[15:

0
]

A[13:0]

TDi

TDo

TRST

Output Timing

STi[15:0]

FPo_OFF[2:0]

P/S Converter

_WR

FPi

CKi

MODE_4M0

MODE_4M1

ODE

RESET

DD_IO

DD_CORE

DD_IOA

DD_COREA

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

· Per-channel constant or variable throughput delay for frame integrity and low latency applications

· Per Stream (16) Bit Error Rate Test circuits complying to ITU-O.151

· Per-channel high impedance output control

· Per-channel message mode

· Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses

· Connection memory block programming

· Supports ST-BUS and GCI-Bus standards for input and output timing

· IEEE-1149.1 (JTAG) test port

· 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage

Applications

· PBX and IP-PBX

· Small and medium digital switching platforms

· Remote access servers and concentrators

· Wireless base stations and controllers

· Multi service access platforms

· Digital Loop Carriers

· Computer Telephony Integration

Description

The ZL50016 is a maximum 1024 x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has
sixteen input streams (STi0 - 15) and sixteen output streams (STio0 - 15). The device can switch 64 kbps and
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be
independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or
16.384 Mbps. The ZL50016 provides up to eight high impedance control outputs (STOHZ0 - 7) to support the use
of external tristate drivers for the first eight output streams (STio0 - 15). The output streams can be configured to
operate in bi-directional mode, in which case STi0 - 15 will be ignored.

The device contains two types of internal memory - data memory and connection memory. There are four modes of
operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the
contents of the connection memory define, for each output stream and channel, the source stream and channel
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with
a pseudorandom bit sequence (PRBS) from one of 16 PRBS generators that generates a 2

-1 pattern. On the

input side channels can be routed to one of 16 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.

The configurable non-multiplexed microprocessor port allows users to program various device operating modes
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection
memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or
Intel-type microprocessors.

The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

ZL50016

Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 External High Impedance Control, STOHZ0 - 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11.0 Device Operation in Divided Clock and Multiplied Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11.1 Divided Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2 Multiplied Clock Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.3 Output Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

12.0 Microprocessor Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

14.0 Pseudo Random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.0 PCM A-law/m-law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
16.0 Quadrant Frame Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

18.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
19.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
20.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

20.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
20.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
20.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ZL50016

Data Sheet

List of Figures

Zarlink Semiconductor Inc.

Figure 1 - ZL50016 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50016 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 8
Figure 3 - ZL50016 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0="11" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4 or 8 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4 or 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 33 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 34 - Output Drive Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 35 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 36 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 37 - FPo1/3 and CKo1/3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 38 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 39 - FPo3 and CKo3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 40 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ZL50016

Data Sheet

List of Tables

Zarlink Semiconductor Inc.

Table 1 - CKi and FPi Configurations for Divided Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2 - CKi and FPi Configurations for Multiplied Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7 - ZL50016 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11 - Quadrant Frame Bit Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23 - Stream Input Quadrant Frame Register 0 - 15 (SIQFR0 - 15) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 25 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 29 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 32 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

1.0 Pinout Diagrams

1.1 BGA Pinout

Figure 2 - ZL50016 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)

STi10

STi5

STi4

CKo2

STi0

CKo0

DD_

COREA

FPi

CKi

IC_Open IC_Open IC_GND

ODE

STi9

STi7

STi6

STi1

CKo1

IC_Open IC_Open IC_Open IC_GND

STio15

STi11

DD_IO

STi3

STi2

FPo_

OFF1

IC_GND

STio13

DD_IO

STio14

STi14

STi8

DD_IO

DD_

CORE

DD_

CORE

DD_IO

STio12

FPo2

STi15

STi12

STi13

DD_IO

DD_

CORE

DD_

CORE

DD_

CORE

DD_

CORE

DD_IO

IC_Open

FPo3

FPo_

OFF2

RESET

IC_GND IC_Open

TDo

DD_IO

A12

A13

FPo1

FPo0

DD_

COREA

A10

FPo_

OFF0

A11

DD_IOA

CKo3

TMS

DD_

COREA

DD_IO

IC_Open

DD_

COREA

TRST

TCK

DD_IO

DD_

CORE

DD_

CORE

DD_

CORE

DD_

CORE

DD_IO

STio10

STio11

STio9

TDi

DD_

CORE

DD_

CORE

D10

DD_

CORE

DD_

CORE

MOT

_INTEL

MODE_

4M0

STio8

DD_IO

STio0

STOHZ3

D11

D13

R/W

_WR

DTA_

RDY

STio4

DD_IO

STOHZ5

STio1

STio3

STOHZ1

D14

STio5

STOHZ4 STOHZ6

STOHZ7

STOHZ0

STio2

STOHZ2

D12

D15

DS_RD

MODE_

4M1

STio6

STio7

Note: A1 corner identified by metallized marking.

Note: Pinout is shown as viewed through top of package.

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

1.2 QFP Pinout

Figure 3 - ZL50016 256-Lead 28 mm x 28 mm LQFP (top view)

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

22 24 26 28 30

120

102

104

106

108

110

114

116

118

112

52 54 56

58 60

100

132

134

136

138

140

142

144

146

148

150

IC_

e
n

IC_

e
n

IC_

e
n

IC_

e
n

IC_

e
n

IC_

DD_

IC_

DD_

NC NC NC NC

62 64

122

124

126

128

182

184

186

188

190

NC NC VS

I
O

i_7

i_6

NC NC

I
O

VSS

DD_

VDD_IO

TRST

TCK

TMS

VSS

VDD_CORE

VSS

VDD_COREA

VSS

CKo3

VDD_IOA

VDD_COREA

VSS

VDD_IOA

VSS

VDD_COREA

VSS

VDD_CORE

TDo

RESET

IC_Open

IC_GND

VSS

VDD_IO

STi_15

STi_14

STi_11

STi_10

STi_9

STi_8

VSS

TDi

VDD_IO

202

220

218

216

214

212

208

206

204

210

222

240

238

236

234

232

228

226

224

230

242

256

254

252

248

246

244

250

200

198

196

194

VSS

STi_13

STi_12

NC NC NC NC

VDD_I

VSS

i
o_0

i
o_1

i
o_2

i
o_3

STOH

_
0

OHZ_1

STOH

_
2

STOH

_
3

VDD_I

D4 D5

D7 D8 D9

VDD_I

VSS

T_I

_RDY

_
4

VDD_I

VSS

i
o_4

i
o_5

i
o_6

i
o_7

STOH

_
4

_
5

STOH

_
6

Z_7

VDD_IO

VSS

STio_8

STio_9

STio_10

STio_11

VDD_IO

IC_Open

VSS

VDD_CORE

VSS

A11

A10
A9

VDD_CORE

VSS

A13

A12

IC_Open

VDD_IO

VSS

FPo_OFF0

FPo0

FPo_OFF1

FPo1

FPo2

FPo_OFF2

FPo3

VDD_CORE

VSS

IC_GND

VDD_IO

VSS

STio_12

STio_13

STio_14

STio_15

VDD_IO

VSS

DD_

VSS

192

130

NC NC

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

234

TMS

Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.

238

TCK

Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic.

239

TRST

Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.

240

TDi

Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.

212

TDo

Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.

B12, B13,
C10, C11,

F13, G4,

K12, C12,

80, 105,

150, 151,
152, 153,

210, 149

IC_Open

Internal Test Mode (5 V-Tolerant Input with Internal
Pull-down)
These pins may be left unconnected.

G3, D12,

B14, C13

144, 107,

148, 208

IC_GND

Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.

PBGA Pin

Number

LQFP Pin

Number

Pin Name

Description

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

G15, G14,

E15, F14

102, 106,

110, 112

FPo0 - 3

ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output
clock of CKo0.
FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output
clock of CKo1.
FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output
clock of CKo2.
FPo3: Programmable 8 kHz frame pulse corresponding to
4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock
of CKo3.

H14, D11,

F15

100, 104,

108

FPo_OFF0 - 2

Generated Offset Frame Pulse Outputs 0 to 2 (5 V-Tolerant
Three-state Outputs)
Individually programmable 8 kHz frame pulses, offset from the
output frame boundary by a programmable number of channels.

B7, C7, B5,

170, 172,

174, 227

CKo0 - 3

ST-BUS/GCI-Bus Clock Outputs 0 to 3 (5 V-Tolerant
Three-state Outputs)
CKo0: 4.096 MHz output clock.
CKo1: 8.192 MHz output clock.
CKo2: 16.384 MHz output clock.
CKo3: 4.096 MHz, 8.192 MHz or 16.384 MHz programmable
output clock. 32.768MHz if in multiplied clock mode.

B10

155

FPi

ST-BUS/GCI-Bus Frame Pulse Input (5 V-Tolerant
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the CKi must
be applied to this pin. If the data rate is 16.384 Mbps, a 61 ns wide
frame pulse must be used. By default, the device accepts a
negative frame pulse in ST-BUS format, but it can accept a
positive frame pulse instead if the FPINP bit is set high in the
Control Register (CR). It can accept a GCI-formatted frame pulse
by programming the FPINPOS bit in the Control Register (CR) to
high.

B11

154

CKi

ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
In divided clock mode the clock frequency applied to this pin must
be twice the highest input or output data rate. In multiplied
clock mode the clock frequency applied to this pin must be twice
the highest input data rate.
The exception is, when data is running at 16.384 Mbps, a 16.384
MHz clock must be used. By default, the clock falling edge defines
the input frame boundary, but the device allows the clock rising
edge to define the frame boundary by programming the CKINP bit
in the Control Register (CR).

PBGA Pin

Number

LQFP Pin

Number

Pin Name

Description

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

B6, C6, D5,
D4, B4, B3,
C5, C4, E3,
C2, B2, D2,

F3, F4, E2,

179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
205, 206,

STi0 - 15

Serial Input Streams 0 to 15 (5 V-Tolerant Inputs with Internal
Pull-downs)
The data rate of each input stream can be selected independently
using the Stream Input Control Registers (SICR[n]). In the
2.048 Mbps mode, these pins accept serial TDM data streams at
2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode,
these pins accept serial TDM data streams at 4.096 Mbps with 64
channels per frame. In the 8.192 Mbps mode, these pins accept
serial TDM data streams at 8.192 Mbps with 128 channels per
frame. In the 16.384 Mbps mode, these pins accept TDM data
streams at 16.384 Mbps with 256 channels per frame.

N4, P4, R4,

P5, N13,

P11, R14,

R15, M15,

L15, L13,

L14, E14,

D13, D15,

C15

6, 7, 9,
10, 51,
52, 53,
54, 70,
72, 73,

74, 115,

116, 117,

118

STio 0 - 15

Serial Output Streams 0 to 15 (5 V-Tolerant Slew-Rate-Limited
Three-state I/Os with Enabled Internal Pull-downs)
The data rate of each output stream can be selected
independently using the Stream Output Control Registers
(SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM
data streams at 2.048 Mbps with 32 channels per frame. In the
4.096 Mbps mode, these pins output serial TDM data streams at
4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode,
these pins output serial TDM data streams at 8.192 Mbps with
128 channels per frame. In the 16.384 Mbps mode, these pins
output serial TDM data streams at 16.384 Mbps with 256
channels per frame.These output streams can be used as
bi-directionals by programming BDL (bit 6) of Internal Mode
Selection (IMS) register.

R3, P6, R5,

N5, P12,

N15, P13,

P15

11, 12,

13, 14,
55, 56,

58, 59

STOHZ 0 - 7

Serial Output Streams High Impedance Control 0 to 7
(5 V-Tolerant Slew-Rate-Limited Three-state Outputs)
These pins are used to enable (or disable) external three-state
buffers. When an output channel is in the high impedance state,
the STOHZ drives high for the duration of the corresponding
output channel. When the STio channel is active, the STOHZ
drives low for the duration of the corresponding output channel.
STOHZ outputs are available for STio0 - 7 only.

B15

141

ODE

Output Drive Enable (5 V-Tolerant Input with Internal Pull-up)
This is the output enable control for STio0 - 15 and the
output-driven-high control for STOHZ0 - 7. When it is high, STio0 -
15 and STOHZ0 - 7 are enabled. When it is low, STio0 - 15 are
tristated and STOHZ0 - 7 are driven high.

M4, N6, R6,

P7, R7, N7,

M8, N8, P8,

R8, M9, N9,

R9, N10, P9,

R10

16, 18,
20, 22,
23, 24,
25, 26,
27, 28,
30, 32,
34, 36,

37, 38

D0 - 15

Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state
I/Os)
These pins form the 16-bit data bus of the microprocessor port.

PBGA Pin

Number

LQFP Pin

Number

Pin Name

Description

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

N12

DTA_RDY

Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.

R11

Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.

N11

R/W_WR

Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.

R12

DS_RD

Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.

K13, K15,

K14, J11,

J12, J13,

J15, H11,

J14, H12,

H13, H15,

G12, G13

82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,

98, 99

A0 - 13

Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.

M13

MOT_INTEL

Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin
is connected to ground, Intel interface should be used.

211

RESET

Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 15 drivers and drives the STOHZ0 - 7 outputs
to high. It also preloads registers with default values and clears all
internal counters. To ensure proper reset action, the reset pin
must be low for longer than 1

µs. Upon releasing the reset signal

to the device, the first microprocessor access cannot take place
for at least 600

µs due to the time required to stabilize the device

from the power-down state. Refer to Section Section 13.2 on
page 32 for details.

PBGA Pin

Number

LQFP Pin

Number

Pin Name

Description

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

3.0 Device Overview

The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15).
STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking
digital switch with 1024 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides eight high impedance control outputs (STOHZ0 - 7) to support the use
of external ST-BUS/GCI-Bus tristate drivers for the first eight sixteen ST-BUS/GCI-Bus outputs (STio0 -7).

By using Zarlink's message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.

The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Clock mode (CLKM
bit 11 Table 13, Control Register (CR) Bits. In Multiplied Clock mode, the output data streams will be driven by an
internally generated clock, which is multiplied from CKi internally. In Multiplied Clock mode, the output data streams
will be driven by an internally generated clock, which is multiplied from CKi internally. Refer to Application Note
ZLAN-120 for further explanation of the different modes of operation.

There are two clock modes for this device:

The first is the Divided Clock mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is
4.096 MHz, the output data rate cannot be higher than 2.048 Mbps.The second clock mode is called Multiplied
Clock mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by
this internal clock. In Multiplied Clock mode, the data rate of output streams can be any rate, but output jitter may
not be exactly the same as input jitter.

A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate
in various modes under different switching configurations. Users can use the microprocessor port to perform
internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit
address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).

The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

4.0 Data Rates and Timing

The ZL50016 has 16 serial data inputs and 16 serial data outputs. Each stream can be individually programmed to
operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32
channels, 64 channels, 128 channels or 256 channels, respectively, during a 125

µs frame.

The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal
Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0
- 15 (STio0 - 15) are set to operate in a bi-directional mode.The input data rate is set on a per-stream basis by
programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 15 (SICR0 - 15). The output data
rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register
0 - 15 (SOCR0 - 15). The output data rates do not have to match or follow the input data rates. The maximum
number of channels switched is limited to 1024 channels. If all 16 input streams were operating at 16.384 Mbps
(256 channels per stream), this would result in 4096 channels. Memory limitations prevent the device from
operating at this capacity. A maximum capacity of 1024 channels will occur if four of the streams are operating at
16.384 Mbps, eight of the streams are operating at 8.192 Mbps or all streams operating at 4.096 Mbps. With all
streams operating at 2.048 Mbps, the capacity will be reduced to 512 channels. However, as each stream can be
programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

count does not exceed 1024 channels. It should be noted that only full stream can be programmed for use. The
device does not allow fractional streams.

4.1 External High Impedance Control, STOHZ0 -

There are 16 external high impedance control signals, STOHZ0 - 7, that are used to control the external drivers for
per-channel high impedance operations. Only the first eight ST-BUS/GCI-Bus (STio0 - 7) outputs are provided with
corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot channels
based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin is high
and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 7 are enabled. When the ODE pin, OSB (bit
2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 7 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 16 on page 27 for a
diagrammatical explanation.

4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing

The frequency of the input clock (CKi) for the ZL50016 depends on the operation mode selected. In divided clock
mode, CKi must be at least twice the highest input or output data rate. For example, if the highest input data rate is
4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is
twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In multiplied clock
mode the frequency of CKi must be at least twice the highest input data rate regardless of the output data rate. An
APLL is used to multiple CKi to generate an internal clock that is used to output clocks and STio streams.
Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz,
regardless of the output data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi.

In either mode the user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width
of the input frame pulse and the frequency of the input clock supplied to the device.

Highest Input or Output

Data Rate

CKIN 1-0 Bits

Input Clock Rate (CKi)

Input Frame Pulse (FPi)

16.384 Mbps or 8.192 Mbps

16.384 MHz

8 kHz (61 ns wide pulse)

4.096 Mbps

8.192 MHz

8 kHz (122 ns wide pulse)

2.048 Mbps

4.096 MHz

8 kHz (244 ns wide pulse)

Table 1 - CKi and FPi Configurations for Divided Clock Modes

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

5.0 ST-BUS and GCI-Bus Timing

The ZL50016 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the
device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by
the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge
of CKo while FPo goes high. The data rates define the number of channels that are available in a 125

µs frame

pulse period.

By default, the ZL50016 is configured for ST-BUS input and output timing. To set the input timing to conform to the
GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing
to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse
Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the
polarity (positive-going or negative-going) of the output clocks.

6.0 Output Timing Generation

The ZL50016 generates frame pulse and clock timing. There are four output frame pulse pins (FPo0 - 3) and four
output clock pins (CKo0 - 3). All output frame pulses are 8 kHz output signals. By default, the output frame
boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1,
CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. The
duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 3 on
page 20. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode
Selection (IMS) register.

The output timing is dependent on the operation mode that is selected. When the device is in Divided Clock mode,
the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is
8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output
a 4.096 MHz or 8.192 MHz clock signal.

The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50016 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.

The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and
CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing.

Pin Name

Output Timing Rate

Output Timing Unit

FPo0 pulse width

244

CKo0

4.096

MHz

FPo1 pulse width

122

CKo1

8.192

MHz

FPo2 pulse width

CKo2

16.384

MHz

FPo3 pulse width

244, 122, 61 or 30

CKo3

4.096, 8.192, 16.384 or 32.768

MHz

Table 3 - Output Timing Generation

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

7.0 Data Input Delay and Data Output Advancement

Various registers are provided to adjust the input delay and output advancement for each input and output data
stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream.

If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The
sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating
at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set
to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate.

The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment, unless the output
stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2
bit. By default, there is 0 output bit advancement.

Although input delay or output advancement features are available on streams which are operating in bi-directional
mode it is not recommended, as it can easily cause bus contention. If users require this function special attention
must be given to the timing to ensure contention is minimized.

7.1 Input Bit Delay Programming

The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.

By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 15 (SICR0 - 15) as described in Table 22 on page 48. The input bit delay can range from
0 to 7 bits.

Figure 11 - Input Bit Delay Timing Diagram (ST-BUS)

FPi

STi[n]
Bit Delay = 0
(Default)

Channel 0

Channel 1

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2

Channel 2

2 1 0

4 3

Last Channel

STi[n]
Bit Delay = 1

Channel 0

Channel 1

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3

Channel 2

2 1 0

4 3

Last Channel

Bit Delay = 1

Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 15 (SICR0 - 15).

Figure 13 - Input Bit Delay and Factional Sampling Point

7.3 Output Advancement Programming

This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 15 (SOCR0 - 15).

By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 15 (SOCR0 - 15) as described in Table 24 on page 51. The output bit
advancement can vary from 0 to 7 bits.

Nominal Channel n+1 Boundary

000 01

000 10

000 00 (Default)

000 11

001 01

001 10

001 00

001 11

010 01

010 10

010 00

010 11

011 01

011 10

011 00

011 11

111 00

111 10

111 01

110 11

110 00

110 10

110 01

101 11

101 00

101 10

101 01

100 11

100 00

100 10

100 01

111 11

The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset

STi[n]

Nominal Channel n Boundary

Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point

Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS)

7.4 Fractional Output Bit Advancement Programming

In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers
better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the
serial data output pins.

By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the
output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the
Stream Output Control Register 0 - 15 (SOCR0 - 15). For all streams running at any data rate except 16.384 Mbps
the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the
fractional bit advancement can be set to either 0 or 1/2 bit.

Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)

FPi

STio[n]
Bit Adv = 0
(Default)

Channel 0

Channel 1

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2

Channel 2

2 1 0

4 3

Last Channel

STio[n]
Bit Adv = 1

Channel 0

Channel 1

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3

Channel 2

2 1 0

Last Channel

Bit Advancement = 1

Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.

2 1

FPi

STio[n]
STo[n]FA1-0 = 00
(Default 2, 4, 8 or
16Mb/s)

Channel 0

Last Channel

STio[n]
STo[n]FA1-0 = 01
(2, 4 or 8 Mbps)

Channel 0

Last Channel

Fractional Bit Advancement = 1/4 Bit

STio[n]
STo[n]FA1-0 = 10
(2, 4 or 8 Mbps)
STo[n]FA1-0 = 01
(16 Mbps)

Channel 0

Last Channel

Fractional Bit Advancement = 1/2 Bit

STio[n]
STo[n]FA1-0 = 11
(2, 4 or 8 Mbps)

Channel 0

Last Channel

Fractional Bit Advancement = 3/4 Bit

Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

7.5 External High Impedance Control Advancement

The external high impedance signals can be programmed to better match the timing required by the external
buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of
their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any
data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by
programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at
16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same
register.

Figure 16 - Channel Switching External High Impedance Control Timing

8.0 Data Delay Through the Switching Paths

The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.

8.1 Variable Delay Mode

Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.

In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.

CH0

CH1

CH2

CH3

Last-2

Last-1

Last

CH0

Last

HiZ

FPi

STio[n]

STOHZ[n]

STOHZ[n]
(with Advancement)

(Default = No Advancement)

STOHZ Advancement (Programmable in 4 steps of 1/4 bit

for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
Programmable in 2 steps of 1/2 bit for 16.384 Mbps)

Note: n = 0 to 15
Note: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.

Output Frame Boundary

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in
the same 125

µs frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will

appear in the following frame.

Figure 17 - Data Throughput Delay for Variable Delay

8.2 Constant Delay Mode

In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames -
Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a
stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when
the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all
output channels.

The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and
output channel number (n). The data throughput delay (T) is:

T = 2 frames + (n - m)

The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit
is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable
variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay
mode.

m = input channel number

n = output channel number

n-m <= 0

0 < n-m < 7

n-m = 7

n-m > 7

STio < STi

STio >= STi

T = Delay between input and output

1 frame - (m-n)

1 frame + (n-m)

n-m

Table 4 - Delay for Variable Delay Mode

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

CH4 CH5 CH6

CH7 CH8 CH9

STi4
CH2

STio5

CH9

STi6
CH1

STio9

CH3

Frame N

Frame N + 1

L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps respectively

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 18 - Data Throughput Delay for Constant Delay

9.0 Connection Memory Description

The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High
(CM_H). The CM_L is 16 bits wide and is used for channel switching and other special modes. The CM_H is 5 bits
wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low,

µ-law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory
location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor
access cycle. See Table 29 on page 54 for the address mapping of the connection memory. Any unused bits will be
reset to zero on the 16-bit data bus.

For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode
without the

µ-law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If

µ-law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information,
the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory
Low.

When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50016 will operate in one of
the special modes described in Table 31 on page 56. When the per-channel message mode is enabled, MSG7 - 0
(bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data.
When the per-channel message mode is enabled, the

µ-law/A-law conversion can also be enabled as required.

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

L-2

L-1 CH0 CH1 CH2 CH3

STi

STio

STi

STio

L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, or 16.384 Mbps respectively

Frame N

Frame N + 1

Frame N + 2

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

10.0 Connection Memory Block Programming

This feature allows for fast initialization of the connection memory after power up.

10.1 Memory Block Programming Procedure

1. Set MBPE (bit 3) in the Control Register (CR) from low to high.

2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded

into CM_L.

3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-

ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.

The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.

Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.

It takes at least two frame periods (250

µs) to complete a block program cycle.

MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.

MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.

Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.

11.0 Device Operation in Divided Clock and Multiplied Clock Modes

This device has two main operating modes - Divided Clock mode and Multiplied Clock mode.

In Multiplied Clock mode, output clocks and frame pulses are generated from an internal high-speed clock
synchronized to CKi and FPi. Therefore, all specified output clock rates and data rates are available on CKo0-3 and
STio0-31. In Divided Clock mode, output clocks and frame pulses are directly divided from CKi/FPi. Therefore, the
output clock rate cannot exceed the CKi rate (the output data rates are also limited as per Table 1). The input data
rate cannot exceed the CKi rate in either Multiplied or Divided Clock modes, because input data are always
sampled directly by CKi.

Bit

Value

BPD2

BPD1

BPD0

Table 5 - Connection Memory Low After Block Programming

Bit

Value

Table 6 - Connection Memory High After Block Programming

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Table 7, "ZL50016 Operating Modes" on page 31 summarizes the different modes of operation available within the
ZL50016. Each Major mode (explained below) has various associated Minor modes that are determined by setting
the MODE_4M Input Control pins and the OPM bit in the Control Register (Table 13, "Control Register (CR) Bits" on
page 38) indicated in the table.

Table 7 - ZL50016 Operating Modes

11.1 Divided Clock Mode Operation

When the device is in Divided Clock mode, STio0 - 15 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the input and output data rate cannot exceed the
input data rate defined by CKi. For example, if CKi is 4.096 MHz, the input and output data rate cannot be higher
than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz.

11.2 Multiplied Clock Mode Operation

When the device is in Multiplied Clock mode, device hardware is used to multiply CKi internally. STio0 - are driven
by this internally generated clock. In this mode, the output clocks and data can run at any of the specified rates, but
they may have different jitter characteristics from the input clock (CKi). The input data rates are still limited by the
CKi rate (as per Table 1), as input data are always sampled directly by CKi.

11.3 Output Clock Frequencies

The device can generate a limited number of clock and frame pulse output signals. All signals are synchronous to
each other and are locked to the input CKi and FPi. The device can provide outputs with the following frequencies,
with the exception that when in Divided Clock mode, the output clock rate cannot exceed the input CKi rate.

Device

Input Pins

CR Register

Output Clock Pins

Data Pins

Operating Mode

Control

Signal

Bit

Reference Lock

Enabled

Clock Source

Major

Minor

MODE_4M [1:0]

CKi

OPM

CKo0-3

STi

STo

Divided

Clock

4 M

CKi

Yes

CKi

CKo0-3

(CKi)

8/16 M

Multiplied

Clock

4 M

CKi MULT

CKo0-3

(CKi MULT)

8/16 M

Legend:

X - Don't care or not applicable.

Reference Lock - Refers to what signal the output pins are locked to:
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
Clock Source - Refers to which clock samples STi and which clock outputs STo; STi applies when STi or STio is input; STo applies when STio is output.

CKo0

4.096 MHz

CKo1

8.192 MHz

CKo2

16.384 MHz

CKo3

4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz

FPo0

8 kHz (244 ns wide pulse)

FPo1

8 kHz (122 ns wide pulse)

FPo2

8 kHz (61 ns wide pulse)

FPo3

8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)

Table 8 - Generated Output Frequencies

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

12.0 Microprocessor Port

The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY).

The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.

For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.

Refer to Figure 20 on page 60, Figure 21 on page 61, Figure 22 on page 62 and Figure 23 on page 63 for the
microprocessor timing.

13.0 Device Reset and Initialization

The RESET pin is used to reset the ZL50016. When this pin is low, the following functions are performed:

· synchronously puts the microprocessor port in a reset state

· tristates the STio0 - 15 outputs

· drives the STOHZ0 - 7 outputs to high

· preloads all internal registers with their default values (refer to the individual registers for default values)

· clears all internal counters

13.1 Power-up Sequence

The recommended power-up sequence is for the V

DD_IO

supply (normally +3.3 V) to be established before the

power-up of the V

DD_CORE

supply (normally +1.8 V). The V

DD_CORE

supply may be powered up at the same time

as V

DD_IO

, but should not "lead" the V

DD_IO

supply by more than 0.3 V.

13.2 Device Initialization on Reset

Upon power up, the ZL50016 should be initialized as follows:

· Set the ODE pin to low to disable the STio0 - 15 outputs and to drive STOHZ0 - 7 to high

· Set the TRST pin to low to disable the JTAG TAP controller

· Reset the device by pulsing the RESET pin to zero for longer than 1

µs

· After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the

device to stabilize from the power down state before the first microprocessor port access can occur

· Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs

· Wait at least 500

µs prior to the next microport access (see Note below)

· Use the block programming mode to initialize the connection memory

· Release the ODE pin from low to high after the connection memory is programmed

Note: If CKi is 16.384 MHz, the waiting time is 500

µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is

4.096 MHz, the waiting time is 2 ms.

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

13.3 Software Reset

In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset
SRSTSW (bit 1) in the Software Reset Register (SRR).

14.0 Pseudo Random Bit Generation and Error Detection

The ZL50016 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 16 transmitters connected to the output streams and 16 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 2

-1 pseudorandom code (ITU O.151).

Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125

µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and

TBEREN (bit 4) in the IMS register. In order to save power, the 16 transmitters and/or receivers can be disabled.
(This is the default state.)

Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.

For each input stream, there is a set of registers for the BER test. The registers are as follows:

· BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register

(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.

· BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the

BER sequence will start to be compared.

· BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence

will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64,or 128

channels at the data rates of 2.048, 4.096,or 8.192.Mbps, respectively. The minimum length of the BER test

is a single channel. The user must take care to program the correct channel length for the BER test so that

the channel length does not exceed the total number of channels available in the stream.

· BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When

the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER

(bit 1) in the BER Receiver Control Register is used to reset the BRER register.

For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L) PCC1 - 0 (bits 2 - 1) in
the Connection Memory Low must be programmed to "10" to enable the per-stream based BER transmitters. For
each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the
channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER
receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250

µs)

between completion of connection memory programming and starting the BER receiver before the BER receiver
can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

15.0 PCM A-law/

µ-law Translation

The ZL50016 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or
data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode
and Message Mode.

In order to use this feature the Connection Memory High (CM_H) entry for the output channel must be
programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the
input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 9.

The different code options are:

For voice coding options, the ITU-T G.711 A-law and ITU-T G.711

µ-law are the standard rules for encoding. A-law

without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0).

µ-law

without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3,
2, 1, 0).

When transferring data code, the option "no code" does not invert the bits. The Alternate Bit Inversion (ABI) option
inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When
the "All bits inverted" option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.

The input channel and output channel encoding law are configured independently. If the output channel coding is
set to be different from the input channel, the ZL50016 performs translation between the two standards. If the input
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection
Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data
encoding laws.

16.0 Quadrant Frame Programming

By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 15), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:

Input Coding

(ICL1- 0)

Output Coding

(OCL1 - 0)

Voice Coding

(V/D bit = 0)

Data Coding

(V/D bit = 1)

ITU-T G.711 A-law

No code

ITU-T G.711

µ-law

Alternate Bit Inversion (ABI)

A-law without Alternate Bit
Inversion (ABI)

Inverted Alternate Bit
Inversion (ABI)

µ-law without Magnitude
Inversion (MI)

All bits inverted

Table 9 - Input and Output Voice and Data Coding

Data Rate

Quadrant 0

Quadrant 1

Quadrant 2

Quadrant 3

2.048 Mbps

Channel 0 - 7

Channel 8 - 15

Channel 16 - 23

Channel 24 - 31

4.096 Mbps

Channel 0 - 15

Channel 16 - 31

Channel 32 - 47

Channel 48 - 63

8.192 Mbps

Channel 0 - 31

Channel 32 - 63

Channel 64 - 95

Channel 96 - 127

16.384 Mbps

Channel 0 - 63

Channel 64 - 127

Channel 128 - 191

Channel 192 - 255

Table 10 - Definition of the Four Quadrant Frames

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to "1"
or "0" as shown by the following table:

Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.

17.0 JTAG Port

The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.

17.1 Test Access Port (TAP)

The Test Access Port (TAP) accesses the ZL50016 test functions. It consists of three input pins and one output pin
as follows:

· Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip

clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of

the Boundary-Scan register cells concurrently with the operation of the device and without interfering with

the on-chip logic.

· Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to

control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is

internally pulled to high when it is not driven from an external source.

· Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a

test data register, depending on the sequence previously applied to the TMS input. The registers are

described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse.

This pin is internally pulled to high when it is not driven from an external source.

· Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of

either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is

clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the

TDo driver is set to a high impedance state.

· Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not

driven from an external source.

STIN[n]Q[y]C[2:0]

Action

0xx

Normal Operation

100

Replaces LSB of every channel in Quadrant y with `0'

101

Replaces LSB of every channel in Quadrant y with `1'

110

Replaces MSB of every channel in Quadrant y with `0'

111

Replaces MSB of every channel in Quadrant y with `1'

Note: y = 0, 1, 2, 3

Table 11 - Quadrant Frame Bit Replacement

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

18.0 Register Address Mapping

Address
A13 - A0

CPU

Access

Register

Name

Abbreviation

Reset By

0000

R/W

Control Register

Switch/Hardware

0001

R/W

Internal Mode Selection Register

IMS

Switch/Hardware

0002

R/W

Software Reset Register

SRR

Hardware Only

0003

R/W

Output Clock and Frame Pulse Control Register

OCFCR

Hardware

0004

R/W

Output Clock and Frame Pulse Selection
Register

OCFSR

Hardware

0005

R/W

FPo_OFF0 Register

FPOFF0

Hardware

0006

R/W

FPo_OFF1 Register

FPOFF1

Hardware

0007

R/W

FPo_OFF2 Register

FPOFF2

Hardware

0010

R Only

Internal Flag Register

IFR

Switch/Hardware

0011

R Only

BER Error Flag Register 0

BERFR0

Switch/Hardware

0013

R Only

BER Receiver Lock Register 0

BERLR0

Switch/Hardware

0100

010F

R/W

Stream Input Control Registers 0 - 15

SICR0 - 15

Switch/Hardware

0120

012F

R/W

Stream Input Quadrant Frame Registers 0 - 15

SIQFR0 - 15

Switch/Hardware

0200

020F

R/W

Stream Output Control Registers 0 - 15

SOCR0 - 15

Switch/Hardware

0300

030F

R/W

BER Receiver Start Registers 0 - 15

BRSR0 - 15

Switch/Hardware

0320

032F

R/W

BER Receiver Length Registers 0 - 15

BRLR0 - 15

Switch/Hardware

0340

034F

R/W

BER Receiver Control Registers 0 - 15

BRCR0 - 15

Switch/Hardware

0360

036F

R Only

BER Receiver Error Registers 0 - 15

BRER0 - 15

Switch/Hardware

Table 12 - Address Map for Registers (A13 = 0)

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

19.0 Detailed Register Description

Bit

Name

Description

15 - 12

Unused

Reserved. In normal functional mode, these bits MUST be set to zero.

OPM

Operation Mode.

This bit is used to set the device in Master/Slave operation. Refer to Table 7, "ZL50016

Operating Modes" on page 31 for more details.

Unused

Reserved. In normal functional mode, this bits MUST be set to zero.

FPINPOS

Input Frame Pulse (FPi) Position

When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).

When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)

CKINP

Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.

FPINP

Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.

6 - 5

CKIN1 - 0

Input Clock (CKi) and Frame Pulse (FPi) Selection

The MODE_4M0 and MODE_4M1 pins, as described in "Pin Description" on page 10,
should also be set to define the input clock mode.

VAREN

Variable Delay Mode Enable

When this bit is low, the variable delay mode is disabled on a device-wide basis.

When this bit is high, the variable delay mode is enabled on a device-wide basis.

MBPE

Memory Block Programming Enable

When this bit is high, the connection memory block programming mode is enabled to

program the connection memory. When it is low, the memory block programming mode is

disabled.

Table 13 - Control Register (CR) Bits

External Read/Write Address: 0000

Reset Value: 0000

OPM

FPIN

POS

CKINP

FPINP

CKIN

VAR

MBPE

OSB

MS1

MS0

CKIN1 - 0

FPi Active Period

CKi

61 ns

16.384 MHz

122 ns

8.192 MHz

244 ns

4.096 MHz

Reserved

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 9

Unused

Reserved. In normal functional mode, these bits MUST be set to zero.

STIO_PD_

STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.

Unused

Reserved. In normal functional mode, these bits MUST be set to zero.
Used in this bi-directional mode.

BDL

Bi-directional Control for Streams 0-15

RBEREN

PRBS Receiver Enable

When this bit is low, all the BER receivers are disabled. To enable any BER receivers,

this bit MUST be high.

TBEREN

PRBS Transmitter Enable

When this bit is low, all the BER transmitters are disabled. To enable any BER

transmitters, this bit MUST be high.

3 - 1

BPD2 - 0

Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.

Table 14 - Internal Mode Selection Register (IMS) Bits

External Read/Write Address: 0001

Reset Value: 0000

STIO_

PD_EN

BDL

RBER

TBER

BPD

MBPS

BDL

STio0 - 15 Operation

normal operation:

STi0-15 are inputs

STio0-15 are outputs

bi-directional operation:

STi0-15 tied low internally

STio0-15 are bi-directional

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

MBPS

Memory Block Programming Start:
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.

Bit

Name

Description

15 - 2

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

SRSTSW

Software Reset Bit for Switch

When this bit is low, switching blocks are in normal operation. When this bit is high,

switching blocks are in software reset state. Refer to Table 12, "Address Map for

Registers (A13 = 0)" on page 32 for details regarding which registers are affected.

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

Table 15 - Software Reset Register (SRR) Bits

Bit

Name

Description

Table 14 - Internal Mode Selection Register (IMS) Bits (continued)

External Read/Write Address: 0001

Reset Value: 0000

STIO_

PD_EN

BDL

RBER

TBER

BPD

MBPS

External Read/Write Address: 0002

Reset Value: 0000

SRST

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 9

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

FPOF2EN

FPo_OFF2 Enable

When this bit is high, output frame pulse FPo_OFF2

When this bit is low, output frame pulse FPo_OFF2.

FPOF1EN

FPo_OFF1 Enable

When this bit is high, output frame pulse FPo_OFF1 is enabled.

When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.

FPOF0EN

FPo_OFF0 Enable

When this bit is high, output frame pulse FPo_OFF0 is enabled.

When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

CKOFPO3

CKo3 and FPo3 Enable

When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.

When this bit is low, CKo3 and FPo3 are in high impedance state.

CKOFPO2

CKo2 and FPo2 Enable

When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.

When this bit is low, CKo2 and FPo2 are in high impedance state.

CKOFPO1

CKo1 and FPo1 Enable

When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.

When this bit is low, CKo1 and FPo1 are in high impedance state.

CKOFPO0

CKo0 and FPo0 Enable

When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.

When this bit is low, CKo0 and FPo0 are in high impedance state.

Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits

External Read/Write Address: 0003

Reset Value: 0000

FPOF2

FPOF1

FPOF0

CKO

FPO3

CKO

FPO2

CKO

FPO1

CKO

FPO0

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 14

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

13 - 12

CKOFPO3

SEL1 - 0

Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle
Selection

CKO3P

Output Clock (CKo3) Polarity Selection
When this bit is low, the output clock CKo3 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo3 rising edge aligns with the
frame boundary.

FPO3P

Output Frame Pulse (FPo3) Polarity Selection
When this bit is low, the output frame pulse FPo3 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo3 has the positive frame pulse format.

FPO3POS

Output Frame Pulse (FPo3) Position
When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus).

CKO2P

Output Clock (CKo2) Polarity Selection
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.

FPO2P

Output Frame Pulse (FPo2) Polarity Selection
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.

FPO2POS

Output Frame Pulse (FPo2) Position
When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus).

Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits

External Read/Write Address: 0004

Reset Value: 0000

CKO

FPO3

SEL1

CKO

FPO3

SEL0

CKO3

FPO3

POS

CKO2

FPO2

POS

CKO1

FPO1

POS

CKO0

FPO0

POS

CKOFPO3

SEL1 - 0

FPo3

CKo3

244 ns

4.096 MHz

122 ns

8.192 MHz

61 ns

16.384 MHz

30 ns

32.768 MHz

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

CKO1P

Output Clock (CKo1) Polarity Selection
When this bit is low, the output clock CKo1 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo1 rising edge aligns with the
frame boundary.

FPO1P

Output Frame Pulse (FPo1) Polarity Selection
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.

FPO1POS

Output Frame Pulse (FPo1) Position
When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus).

CKO0P

Output Clock (CKo0) Polarity Selection
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.

FPO0P

Output Frame Pulse (FPo0) Polarity Selection
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.

FPO0POS

Output Frame Pulse (FPo0) Position
When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).

Note: In Divided Clock modes, CKo3 - 1 cannot exceed frequency of CKi.

Bit

Name

Description

Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)

External Read/Write Address: 0004

Reset Value: 0000

CKO

FPO3

SEL1

CKO

FPO3

SEL0

CKO3

FPO3

POS

CKO2

FPO2

POS

CKO1

FPO1

POS

CKO0

FPO0

POS

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 2

Unused

Reserved
In normal functional mode, these bits are zero.

OUTERR

Output Error (Read Only)
This bit is set high when the total number of output channels is programmed to be
more than the maximum capacity of 1024, in which case the output channels beyond
the maximum capacity should be disabled.
This bit will be cleared automatically after programming is corrected.

INERR

Input Error (Read Only)
This bit is set high when the total number of input channels is programmed to be more
than the maximum capacity of 1024, in which case the input channels beyond the
maximum capacity should be disabled.This bit will be cleared automatically after pro-
gramming is corrected.

Table 19 - Internal Flag Register (IFR) Bits - Read Only

Bit

Name

Description

15 - 0

BERF[n]

BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.

Note: [n] denotes input stream from 0 - 15.

Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only

External Read Address: 0010

Reset Value: 0000

OUT
ERR

ERR

External Read Address: 00011

Reset Value: 0000

BER

F15

BER

F14

BER

F13

BER

F12

BER

F11

BER

F10

BER

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 12

Unused

Reserved

In normal functional mode, these bits MUST be set to zero.

11 - 9

STIN[n]Q3C2 - 0

Quadrant Frame 3 Control Bits
These three bits are used to control STi[n]'s quadrant frame 3, which is defined
as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.

8 - 6

STIN[n]Q2C2 - 0

Quadrant Frame 2 Control Bits
These three bits are used to control STi[n]'s quadrant frame 2, which is defined
as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps,
4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively.

Table 23 - Stream Input Quadrant Frame Register 0 - 15 (SIQFR0 - 15) Bits

External Read/Write Address: 0120

- 012F

Reset Value: 0000

STIN[n]

Q3C2

STIN[n]

Q3C1

STIN[n]

Q3C0

STIN[n]

Q2C2

STIN[n]

Q2C1

STIN[n]

Q2C0

STIN[n]

Q1C2

STIN[n]

Q1C1

STIN[n]

Q1C0

STIN[n]

Q0C2

STIN[n]

Q0C1

STIN[n]

Q0C0

STIN[n]Q3C

2-0

Operation

0xx

normal operation

100

LSB of each channel is replaced by "0"

101

LSB of each channel is replaced by "1"

110

MSB of each channel is replaced by "0"

111

MSB of each channel is replaced by "1"

STIN[n]Q2C

2-0

Operation

0xx

normal operation

100

LSB of each channel is replaced by "0"

101

LSB of each channel is replaced by "1"

110

MSB of each channel is replaced by "0"

111

MSB of each channel is replaced by "1"

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

5 - 3

STIN[n]Q1C2 - 0

Quadrant Frame 1 Control Bits
these three bits are used to control STi[n]'s quadrant frame 1, which is defined
as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.

2 - 0

STIN[n]Q0C2 - 0

Quadrant Frame 0 Control Bits
These three bits are used to control STi[n]'s quadrant frame 0, which is defined
as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.

Note: [n] denotes input stream from 0 - 15.

Bit

Name

Description

Table 23 - Stream Input Quadrant Frame Register 0 - 15 (SIQFR0 - 15) Bits (continued)

External Read/Write Address: 0120

- 012F

Reset Value: 0000

STIN[n]

Q3C2

STIN[n]

Q3C1

STIN[n]

Q3C0

STIN[n]

Q2C2

STIN[n]

Q2C1

STIN[n]

Q2C0

STIN[n]

Q1C2

STIN[n]

Q1C1

STIN[n]

Q1C0

STIN[n]

Q0C2

STIN[n]

Q0C1

STIN[n]

Q0C0

STIN[n]Q1C

2-0

Operation

0xx

normal operation

100

LSB of each channel is replaced by "0"

101

LSB of each channel is replaced by "1"

110

MSB of each channel is replaced by "0"

111

MSB of each channel is replaced by "1"

STIN[n]Q0C2-0

Operation

0xx

normal operation

100

LSB of each channel is replaced by "0"

101

LSB of each channel is replaced by "1"

110

MSB of each channel is replaced by "0"

111

MSB of each channel is replaced by "1"

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 12

Unused

Reserved

In normal functional mode, these bits MUST be set to zero.

11 - 9

STOHZ[n]A2 - 0

(Valid only for STio0-7)

STOHZ Additional Advancement Bits

8 - 7

STO[n]FA1 - 0

Output Stream[n] Fractional Advancement Bits)

6 - 4

STO[n]AD2 - 0

Output Stream[n] Bit Advancement Selection Bits
The binary value of these bits refers to the number of bits that the output stream
is to be advanced relative to FPo. The maximum value is 7. Zero means no
advancement.

3 - 0

STO[n]DR3 - 0

Output Data Rate Selection Bits

Note: [n] denotes output stream from 0 - 15.

Table 24 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits

External Read/Write Address: 0200

- 020F

Reset Value: 0000

STOHZ

[n]A2

STOHZ

[n]A1

STOHZ

[n]A0

STO[n]

FA1

STO[n]

FA0

STO[n]

AD2

STO[n]

AD1

STO[n]

AD0

STO[n]

DR3

STO[n]

DR2

STO[n]

DR1

STO[n]

DR0

STOHZ[n]A2-0

Additional Advancement

(2.048 Mbps, 4.096 Mbps,

8.192 Mbps)

Additional Advancement

(16.384 Mbps streams)

000

0 bit

001

1/4 bit

2/4 bit

010

2/4 bit

4/4 bit

011

3/4 bit

Reserved

100

4/4 bit

101-111

Reserved

STO[n]FA1-0

Advancement

(2.048 Mbps, 4.096 Mbps,

8.192 Mbps streams)

Advancement

(16.384 Mbps streams)

1/4 bit

2/4

2/4 bit

Reserved

3/4 bit

STIN[n]DR3 - 0

Data Rate

0000

disabled: STio HiZ

(STOHZ driven high)

0001

2.048 Mbps

0010

4.096 Mbps

0011

8.192 Mbps

0100

16.384 Mbps

0101 - 1111

Reserved

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 8

Unused

Reserved

In normal functional mode, these bits MUST be set to zero.

7 - 0

ST[n]

BRS7 - 0

Stream[n] BER Receive Start Bits
The binary value of these bits refers to the input channel in which the BER data starts
to be compared.

Note: [n] denotes input stream from 0 - 15.

Table 25 - BER Receiver Start Register [n] (BRSR[n]) Bits

Bit

Name

Description

15 - 9

Unused

Reserved

In normal functional mode, these bits MUST be set to zero.

8 - 0

ST[n]

BL8 - 0

Stream[n] BER Length Bits
The binary value of these bits refers to the number of consecutive channels expected
to receive the BER pattern. The maximum number of BER channels is 32, 64,128 and
256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps
respectively. The minimum number of BER channels is 1. If these bits are set to zero,
no BER test will be performed.

Note: [n] denotes input stream from 0 - 15.

Table 26 - BER Receiver Length Register [n] (BRLR[n]) Bits

External Read/Write Address: 0300

- 030F

Reset Value: 0000

ST[n]

BRS7

ST[n]

BRS6

ST[n]

BRS5

ST[n]

BRS4

ST[n]

BRS3

ST[n]

BRS2

ST[n]

BRS1

ST[n]

BRS0

External Read/Write Address: 0320

- 03F

Reset Value: 0000

ST[n]

BL8

ST[n]

BL7

ST[n]

BL6

ST[n]

BL5

ST[n]

BL4

ST[n]

BL3

ST[n]

BL2

ST[n]

BL1

ST[n]

BL0

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Bit

Name

Description

15 - 2

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

ST[n]

CBER

Stream[n] Bit Error Rate Counter Clear

When this bit is high, it resets the internal bit error counter and the stream BER

Receiver Error Register to zero.

ST[n]

SBER

Stream[n] Bit Error Rate Test Start

When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit

error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the

completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set

in the IMS Register first.

Note: [n] denotes input stream from 0 - 15.

Table 27 - BER Receiver Control Register [n] (BRCR[n]) Bits

Bit

Name

Description

15 - 0

ST[n]

BC15 - 0

Stream[n] BER Count Bits (Read Only)
The binary value of these bits refers to the bit error counts. When it reaches its maxi-
mum value of 0xFFFF, the value will be held and will not rollover.

Note: [n] denotes input stream from 0 - 15.

Table 28 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only

External

Read/Write Address: 0340

- 034F

Reset Value: 0000

ST[n]

CBER

ST[n]

SBER

External

Read Address: 0360

- 036F

Reset Value: 0000

ST[n]

BC15

ST[n]

BC14

ST[n]

BC13

ST[n]

BC12

ST[n]

BC11

ST[n]

BC10

ST[n]

BC9

ST[n]

BC8

ST[n]

BC7

ST[n]

BC6

ST[n]

BC5

ST[n]

BC4

ST[n]

BC3

ST[n]

BC2

ST[n]

BC1

ST[n]

BC0

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

20.0 Memory

20.1 Memory Address Mappings

When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).

MSB

(Note 1)

Stream Address

(St0 - 15)

Channel Address

(Ch0 - 255)

A13

A12

A11

A10

Stream [n]

Channel [n]

1
1
1
1
1
1
1
1
1

.
.
.
.
.

1
1

0
0
0
0
0
0
0
0
0

.
.
.
.
.

0
0

0
0
0
0
0
0
0
0
1

.
.
.
.
.

1
1

0
0
0
0
1
1
1
1
0

.
.
.
.
.

1
1

0
0
1
1
0
0
1
1
0

.
.
.
.
.

1
1

0
1
0
1
0
1
0
1
0

.
.
.
.
.

0
1

Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8

.
.
.
.
.

Stream 14
Stream 15

0
0

.
.

0
0
0
0

.
.

0
0

.
.
.
.

0
0

.
.
.
.

1
1

0
0

.
.

0
0
0
0

.
.

0
0

.
.
.
.

1
1

.
.
.

1
1

0
0

.
.

0
0
1
1

.
.

1
1

.
.
.
.

1
1

.
.
.

1
1

0
0

.
.

1
1
0
0

1
1

.
.
.
.

1
1

.
.
.
.

1
1

0
0

.
.

1
1
0
0

.
.

1
1

.
.
.
.

1
1

.
.
.
.

1
1

0
0

.
.

1
1
0
0

1
1

.
.
.
.

1
1

.
.
.
.

1
1

0
0

.
.

1
1
0
0

1
1

.
.
.
.

1
1

.
.
.
.

1
1

0
1

.
.

0
1
0
1

.
.

0
1

.
.
.
.

0
1

.
.
.
.

0
1

Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
.
.
.
.
Ch126
Ch 127 (Note 4)
.
.
.
.
Ch 254
Ch 255 (Note 5)

Note 1: Notes:A13 must be high for access to data and connection memory positions. A13 must be low to access

internal registers.

Note 2: Channels 0 to 31 are used when serial stream is at 2.048 Mbps.
Note 3: Channels 0 to 63 are used when serial stream is at 4.096 Mbps.
Note 4: Channels 0 to 127 are used when serial stream is at 8.192 Mbps.
Note 5: Channels 0 to 255 are used when serial stream is at 16.384 Mbps.

Table 29 - Address Map for Memory Locations (A13 = 1)

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

20.2 Connection Memory Low (CM_L) Bit Assignment

When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 30 on page 55.

Bit

Name

Description

UAEN

Conversion between

µ-law and A-law Enable

When this bit is low, normal switch without

µ-law/A-law conversion. Connec-

tion memory high will be ignored.
When this bit is high, switch with

µ-law/A-law conversion, and connection

memory high controls the conversion method.

V/C

Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from con-
stant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.

Unused

Reserved. In normal functional mode, these bits MUST be set to zero.

12 - 9

SSA3 - 0

Source Stream Address
The binary value of these 4 bits represents the input stream number.

8 - 1

SCA7 - 0

Source Channel Address
The binary value of these 8 bits represents the input channel number.

CMM = 0

Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit13 -
1 are the source stream number and channel number.

Note: For proper

law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.

Table 30 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0

UA
EN

V/C

SSA

SCA

CMM

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits
PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode
as shown in Table 31 on page 56.

20.3 Connection Memory High (CM_H) Bit Assignment

Connection memory high provides the detailed information required for

µ-law and A-law conversion. ICL and OCL

bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected
PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the
class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between
A-law and

µ-law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the

ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following
table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are
translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed.

Bit

Name

Description

UAEN

Conversion between

µ-law and A-law Enable (Message mode only)

When this bit is low, message mode has no

µ-law/A-law conversion. Connec-

tion memory high will be ignored.
When this bit is high, message mode has

µ-law/A-law conversion, and con-

nection memory high controls the conversion method.

14 - 11

Unused

Reserved
In normal functional mode, these bits MUST be set to zero.

10 - 3

MSG7 - 0

Message Data Bits
8-bit data for the message mode. Not used in the per-channel tristate and
BER test modes.

2 - 1

PCC1 - 0

Per-Channel Control Bits
These two bits control the corresponding entry's value on the STio stream.

CMM = 1

Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate, per-channel message mode or per-channel BER
mode.

Note: For proper

law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.

Table 31 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1

UA
EN

MSG

PCC

CMM

Channel Output Mode

Per Channel Tristate

Message Mode

BER Test Mode

Reserved

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

21.0 DC Parameters

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25

°C and are for design aid only: not guaranteed and not subject to production testing.

Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-

tion testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (

Absolute Maximum Ratings*

Parameter

Symbol

Min.

Max.

Units

I/O Supply Voltage

DD_IO

-0.5

5.0

Core Supply Voltage

DD_CORE

-0.5

2.5

Input Voltage

I_3V

-0.5

+ 0.5

Input Voltage (5 V-tolerant inputs)

I_5V

-0.5

7.0

Continuous Current at Digital Outputs

Package Power Dissipation

1.5

Storage Temperature

- 55

+125

°C

Recommended Operating Conditions -

Voltages are with respect to ground (V

) unless otherwise stated

Characteristics

Sym.

Min.

Typ.

Max.

Units

Operating Temperature

-40

+85

°C

Positive Supply

DD_IO

3.0

3.3

3.6

Positive Supply

DD_CORE

1.71

1.8

1.89

Input Voltage

3.3

DD_IO

Input Voltage on 5 V-Tolerant Inputs

I_5V

5.0

5.5

DC Electrical Characteristics

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Supply Current - V

DD_CORE

115

Supply Current - V

DD_IO

=30pF

Input High Voltage

2.0

Input Low Voltage

0.8

Input Leakage (input pins)
Input Leakage (bi-directional pins)

5
5

µA

DD_IO

See Note 1

Weak Pullup Current

-33

µA

Input at 0 V

Weak Pulldown Current

µA

Input at V

DD_IO

Input Pin Capacitance

Output High Voltage

2.4

= 8 mA

10 Output Low Voltage

0.4

= 8 mA

11 Output High Impedance Leakage

µA

0 < V < V

12 Output Pin Capacitance

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access

AC Electrical Characteristics

- Motorola Non-Multiplexed Bus Mode - Read Access

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

1 CS de-asserted time

CSD

2 DS de-asserted time

DSD

3 CS setup to DS falling

CSS

4 R/W setup to DS falling

RWS

5 Address setup to DS falling

6 CS hold after DS rising

CSH

7 R/W hold after DS rising

RWH

8 Address hold after DS rising

9 Data setup to DTA Low

= 50 pF

10 Data Active to High Impedance

DHZ

= 50 pF, R

= 1 K

(Note 1)

11 Acknowledgement delay time.

From DS low to DTA low:

Registers
Memory

AKD

185

ns
ns

= 50 pF

12 Acknowledgement hold time.

From DS high to DTA high

AKH

= 50 pF, R

= 1 K

(Note 1)

13 DTA drive high to HiZ

AKZ

Note 1: High impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to

discharge C

Note 2: A delay of 500

µs to 2 ms (see Section 13.2 on page 32) must be applied before the first microprocessor access is

performed after the RESET pin is set high.

A0-A13

D0-D15

CSH

RWS

R/W

RWH

AKD

AKH

DTA

VALID ADDRESS

VALID READ DATA

CSS

DSD

AKZ

CSD

DHZ

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access

AC Electrical Characteristics

- Motorola Non-Multiplexed Bus Mode - Write Access

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

1 CS de-asserted time

CSD

2 DS de-asserted time

DSD

3 CS setup to DS falling

CSS

4 R/W setup to DS falling

RWS

5 Address setup to DS falling

6 Data setup to DS falling

= 50 pF

7 CS hold after DS rising

CSH

8 R/W hold after DS rising

RWH

9 Address hold after DS rising

10 Data hold from DS rising

= 50 pF, R

= 1 K

(Note 1)

11 Acknowledgement delay time.

From DS low to DTA low:

Registers
Memory

AKD

150

ns
ns

= 50 pF

12 Acknowledgement hold time.

From DS high to DTA high

AKH

= 50 pF, R

= 1 K

(Note 1)

13 DTA drive high to HiZ

AKZ

Note 1: High impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to

discharge C

Note 2: A delay of 500

µs to 2 ms (see Section 13.2 on page 32) must be applied before the first microprocessor access is

performed after the RESET pin is set high.

A0-A13

CSH

RWS

R/W

RWH

AKD

AKH

DTA

CSS

DSD

AKZ

D0-D15

VALID WRITE DATA

CSD

VALID ADDRESS

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access

AC Electrical Characteristics

- Intel Non-Multiplexed Bus Mode - Read Access

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

1 CS de-asserted time

CSD

2 RD setup to CS falling

3 WR setup to CS falling

4 Address setup to CS falling

5 RD hold after CS rising

6 WR hold after CS rising

7 Address hold after CS rising

8 Data setup to RDY high

= 50 pF

9 Data Active to High Impedance

CSZ

= 50 pF, R

= 1 K

(Note 1)

10 Acknowledgement delay time.

From CS low to RDY high:

Registers
Memory

AKD

175
185

ns
ns

= 50 pF

11 Acknowledgement hold time.

From CS high to RDY low

AKH

= 50 pF, R

= 1 K

(Note 1)

12 RDY drive low to HiZ

AKZ

Note 1: High impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to

discharge C

Note 2: A delay of 500

µs to 2 ms (see Section 13.2 on page 32) must be applied before the first microprocessor access is

performed after the RESET pin is set high.

A0-A13

D0-D15

AKD

AKH

RDY

VALID ADDRESS

VALID READ DATA

CSD

AKZ

CSZ

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access

AC Electrical Characteristics

- Intel Non-Multiplexed Bus Mode - Write Access

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

1 CS de-asserted time

CSD

2 WR setup to CS falling

3 RD setup to CS falling

4 Address setup to CS falling

5 Data setup to CS falling

= 50 pF

6 WR hold after CS rising

7 RD hold after CS rising

8 Address hold after CS rising

9 Data hold after CS rising

= 50 pF, R

= 1 K

(Note 1)

10 Acknowledgement delay time.

From CS low to RDY high:

Registers
Memory

AKD

150

ns
ns

= 50 pF

11 Acknowledgement hold time.

From CS high to RDY low

AKH

= 50 pF, R

= 1 K

(Note 1)

12 RDY drive low to HiZ

AKZ

Note 1: High impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to

discharge C

Note 2: A delay of 500

µs to 2 ms (Section 13.2 on page 32) must be applied before the first microprocessor access is performed

after the RESET pin is set high.

A0-A13

D0-D15

AKD

AKH

RDY

VALID ADDRESS

CSD

AKZ

VALID WRITE DATA

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

AC Electrical Characteristics

- FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz)

Characteristic

Sym.

Min.

Typ.

Max. Units Notes

FPi Input Frame Pulse Width

FPIW

115

FPi Input Frame Pulse Setup Time

FPIS

FPi Input Frame Pulse Hold Time

FPIH

CKi Input Clock Period

CKIP

CKi Input Clock High Time

CKIH

CKi Input Clock Low Time

CKIL

CKi Input Clock Rise/Fall Time

CKi, t

CKi

CKi Input Clock Cycle to Cycle Variation

CVC

AC Electrical Characteristics

- FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz)

Characteristic

Sym.

Min.

Typ.

Max. Units Notes

FPi Input Frame Pulse Width

FPIW

122

220

FPi Input Frame Pulse Setup Time

FPIS

FPi Input Frame Pulse Hold Time

FPIH

CKi Input Clock Period

CKIP

110

122

135

CKi Input Clock High Time

CKIH

CKi Input Clock Low Time

CKIL

CKi Input Clock Rise/Fall Time

CKi, t

CKi

CKi Input Clock Cycle to Cycle Variation

CVC

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

tion testing.

Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps

AC Electrical Characteristics

- ST-BUS/GCI-Bus Output Timing

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

1 STio Delay - Active to Active

@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps

SOD2

SOD4

SOD8

SOD16

SOD2

SOD4

SOD8

SOD16

0
0
0
0

-6
-6
-6
-6

6
6
6
6

0
0
0
0

ns
ns
ns
ns

= 30 pF

Multiplied Clock Mode

Divided Clock Mode

Bit0

Ch255

CKo0

FPo0

(4.096 MHz)

8.192 Mbps

4.096 Mbps

2.048 Mbps

Output Frame Boundary

STio0 - 15

Bit7

Ch0

Bit6

Ch0

Bit5

Ch0

Bit4

Ch0

Bit0

Ch63

Bit7

Ch0

Bit6

Ch0

Bit0

Ch31

SOD2

SOD4

SOD8

Bit0

Ch127

Bit7

Ch0

Bit6

Ch0

Bit5

Ch0

Bit4

Ch0

Bit3

Ch0

Bit2

Ch0

Bit1

Ch0

Bit0

Ch0

Bit7

Ch0

Bit6

Ch0

Bit5

Ch0

Bit4

Ch0

Bit3

Ch0

Bit2

Ch255

Bit1

Ch255

Bit2

Ch0

Bit1

Ch0

Bit0

Ch0

Bit7

Ch1

Bit6

Ch1

Bit5

Ch1

Bit4

Ch1

Bit3

Ch1

Bit2

Ch1

Bit1

Ch1

SOD16

16.384 Mbps

STio0 - 15

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 36 - FPo0 and CKo0 Timing Diagram

tion testing.

AC Electrical Characteristics

FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Multiplied Clock Mode with More than 10 ns

of Input Cycle to Cycle Variation

tion testing.

AC Electrical Characteristics

FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Divided Clock Mode and Multiplied Clock

Mode with Less than 10ns of Input Cycle to Cycle Variation

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo0 Output Pulse Width

FPW03

239

244

249

= 30 pF

FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary

FODF03

117

127

FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge

FODR03

117

127

CKo0 Output Clock Period

CKP03

239

244

249

= 30 pF

CKo0 Output High Time

CKH03

117

127

CKo0 Output Low Time

CKL03

117

127

CKo0 Output Rise/Fall Time

rCK03

, t

fCK03

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo0 Output Pulse Width

FPW03

218

244

270

= 30 pF

FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary

FODF03

117

127

FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge

FODR03

146

CKo0 Output Clock Period

CKP03

218

244

270

= 30 pF

CKo0 Output High Time

CKH03

117

127

CKo0 Output Low Time

CKL03

146

CKo0 Output Rise/Fall Time

rCK03

, t

fCK03

FPW03

FODR03

FODF03

FPo0/3

CKo0/3

CKL03

CKH03

CKP03

rCK03

fCK03

Output Frame Boundary

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 37 - FPo1/3 and CKo1/3 Timing Diagram

tion testing.

AC Electrical Characteristics

FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Multiplied Clock Mode with More than 10ns

of Input Cycle to Cycle Variation

tion testing.

AC Electrical Characteristics

FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Divided Clock Mode and Multiplied Clock

Mode with Less than 10 ns of Input Cycle to Cycle Variation

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo1 Output Pulse Width

FPW13

117

122

127

= 30 pF

FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary

FODF13

FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge

FODR13

CKo1 Output Clock Period

CKP13

117

122

127

= 30 pF

CKo1 Output High Time

CKH13

CKo1 Output Low Time

CKL13

CKo1 Output Rise/Fall Time

rCK13

, t

fCK13

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo1 Output Pulse Width

FPW13

106

122

127

= 30 pF

FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary

FODF13

FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge

FODR13

CKo1 Output Clock Period

CKP13

106

122

148

= 30 pF

CKo1 Output High Time

CKH13

CKo1 Output Low Time

CKL13

CKo1 Output Rise/Fall Time

rCK13

, t

fCK13

FPW13

FODR13

FODF13

FPo1/3

CKo1/3

CKL13

CKH13

CKP13

rCK13

fCK13

Output Frame Boundary

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 38 - FPo2 and CKo2 Timing Diagram

AC Electrical Characteristics

FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Divided Clock Mode and Multiplied Clock

Mode with Less than 10 ns of Input Cycle to Cycle Variation

tion testing.

AC Electrical Characteristics

FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Multiplied Clock Mode with More than

10 ns of Input Cycle to Cycle Variation

tion testing.

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo2 Output Pulse Width

FPW23

= 30 pF

FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary

FODF23

FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge

FODR23

CKo2 Output Clock Period

CKP23

= 30 pF

CKo2 Output High Time

CKH23

CKo2 Output Low Time

CKL23

CKo2 Output Rise/Fall Time

rCK23

, t

fCK23

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo2 Output Pulse Width

FPW23

= 30 pF

FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary

FODF23

FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge

FODR23

CKo2 Output Clock Period

CKP2

= 30 pF

CKo2 Output High Time

CKH23

CKo2 Output Low Time

CKL23

CKo2Output Rise/Fall Time

rCK23

, t

fCK23

FPW23

FODR23

FODF23

FPo2/3

CKo2/3

CKL23

CKH23

CKP23

rCK23

fCK23

Output Frame Boundary

ZL50016

Data Sheet

Zarlink Semiconductor Inc.

Figure 39 - FPo3 and CKo3 Timing Diagram

AC Electrical Characteristics

FPo3/CKo3 (32.768 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less

than 10 ns of Input Cycle to Cycle Variation

tion testing.

AC Electrical Characteristics

FPo3/CKo3 (32.768 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Input Cycle

to Cycle Variation

tion testing.

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo3 Output Pulse Width

FPW3

30.5

= 30 pF

FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary

FODF3

FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge

FODR3

CKo3 Output Clock Period

CKP3

30.5

= 30 pF

CKo3 Output High Time

CKH3

CKo3 Output Low Time

CKL3

CKo3 Output Rise/Fall Time

rCK3

, t

fCK3

Characteristic

Sym.

Min. Typ.

Max.

Units

Notes

FPo3 Output Pulse Width

FPW3

30.5

= 30 pF

FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary

FODF3

FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge

FODR3

CKo3 Output Clock Period

CKP3

30.5

= 30 pF

CKo3 Output High Time

CKH3

CKo3 Output Low Time

CKL3

CKo3 Output Rise/Fall Time

rCK3

, t

fCK3

FPW3

FODR3

FODF3

FPo3

CKo3

CKL3

CKH3

CKP3

rCK3

fCK3

Output Frame Boundary

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