Document Outline
- Features
- Figure 1 - ZL50051/3 Functional Block Diagram
- Applications
- Device Overview
- Figure 2 - ZL50053 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram (as viewed through top ...
- Figure 3 - ZL50051 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram (as viewed through top ...
- Pin Description
- 1.0 Unidirectional and Bi-directional Switching Applications
- Figure 4 - 8,192 x 8,192 Channels (8Mbps), Unidirectional Switching
- Figure 5 - 4,096 x 4,096 Channels (8Mbps), Bi-directional Switching
- 1.1 Flexible Configuration
- 1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration)
- 1.1.2 Non-Blocking Bi-directional Configuration
- 1.1.3 Blocking Bi-directional Configuration
- Figure 6 - 6,144 x 2,048 Channels (8Mbps) Blocking Bi-directional Configuration
- 2.0 Functional Description
- 2.1 Switching Configuration
- 2.1.1 Unidirectional Switch
- 2.1.2 Backplane-to-Local Path
- 2.1.3 Local-to-Backplane Path
- 2.1.4 Backplane-to-Backplane Path
- 2.1.5 Local-to-Local Path
- 2.1.6 Port Data Rate Modes and Selection
- 2.1.6.1 Local Output Port
- 2.1.6.2 Backplane Output Port
- 2.2 Frame Pulse Input and Master Input Clock Timing
- Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates
- 2.3 Input Frame Pulse and Generated Frame Pulse Alignment
- Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates
- 2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
- 2.5 Input Clock Jitter Tolerance
- 3.0 Input and Output Offset Programming
- 3.1 Input Offsets
- 3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams)
- Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16Mbps
- Figure 10 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Da...
- 3.2 Output Advancement Programming (Backplane and Local Output Streams)
- Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps
- 4.0 Port High Impedance Control
- Table 1 - Local and Backplane Output Enable Control Priority
- 5.0 Data Delay Through the Switching Paths
- Table 2 - Variable Range for Input Streams
- Table 3 - Variable Range for Output Streams
- Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch0
- Figure 13 - Data Throughput Delay with Input Ch0 Switched to Output Ch13
- Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
- 6.0 Microprocessor Port
- 7.0 Device Power-Up, Initialization and Reset
- 7.1 Power-Up Sequence
- 7.2 Initialization
- 7.3 Reset
- Figure 15 - Hardware RESET De-assertion
- 8.0 Connection Memory
- 8.1 Local Connection Memory
- 8.2 Backplane Connection Memory
- Table 4 - Local and Backplane Connection Memory Configuration
- 8.3 Connection Memory Block Programming
- 8.3.1 Memory Block Programming Procedure:
- Table 5 - Local Connection Memory in Block Programming Mode
- Table 6 - Backplane Connection Memory in Block Programming Mode
- 9.0 Memory Built-In-Self-Test (BIST) Mode
- 10.0 JTAG Port
- 10.1 Test Access Port (TAP)
- 10.2 TAP Registers
- 10.2.1 Test Instruction Register
- 10.2.2 Test Data Registers
- 10.2.2.3 The Device Identification Register
- 10.3 Boundary Scan Description Language (BSDL) File
- 11.0 Memory Address Mappings
- Table 7 - Address Map for Data and Connection Memory Locations (A14 = 1)
- 11.1 Local Data Memory Bit Definition
- Table 8 - Local Data Memory (LDM) Bits
- 11.2 Backplane Data Memory Bit Definition
- Table 9 - Backplane Data Memory (BDM) Bits
- 11.3 Local Connection Memory Bit Definition
- Table 10 - LCM Bits for Source-to-Local Switching
- 11.4 Backplane Connection Memory Bit Definition
- Table 11 - BCM Bits for Source-to-Backplane Switching
- 12.0 Internal Register Mappings
- Table 12 - Address Map for Registers (A14 = 0)
- 13.0 Detailed Register Descriptions
- 13.1 Control Register (CR)
- Table 13 - Control Register Bits
- Figure 16 - Frame Boundary Conditions, ST-BUS Operation
- Figure 17 - Frame Boundary Conditions, GCI-Bus Operation
- 13.2 Block Programming Register (BPR)
- Table 14 - Block Programming Register Bits
- 13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31)
- Table 15 - Local Input Bit Delay Register (LIDRn) Bits
- 13.3.1 Local Input Delay Bits 4-0 (LID[4:0])
- Table 16 - Local Input Bit Delay and Sampling Point Programming Table
- 13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
- Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits
- 13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0])
- Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table
- 13.5 Local Output Advancement Registers (LOAR0 to LOAR31)
- Table 19 - Local Output Advancement Register (LOAR) Bits
- 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)
- Table 20 - Local Output Advancement (LOAR) Programming Table
- 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31)
- Table 21 - Backplane Output Advancement Register (BOAR) Bits
- 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
- Table 22 - Backplane Output Advancement (BOAR) Programming Table
- 13.7 Memory BIST Register
- Table 23 - Memory BIST Register (MBISTR) Bits
- 13.8 Bit Rate Register
- Table 24 - Bit Rate Register (BRR) Bits
- 13.9 Device Identification Register
- Table 25 - Device Identification Register (DIR) Bits
- 14.0 DC Electrical Characteristics
- Absolute Maximum Ratings*
- Recommended Operating Conditions
- DC Electrical Parameters
- 15.0 AC Electrical Characteristics
- AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
- Input and Output Clock Timing
- Figure 18 - Input and Output Clock Timing Diagram for ST-BUS
- Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus
- Local and Backplane Data Timing
- Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8Mbps)
- Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16Mbps)
- Figure 22 - GCI-Bus Local/Backplane Data Timing Diagram (8Mbps)
- Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16Mbps)
- Local and Backplane Output High Impedance Timing
- Figure 24 - Serial Output and External Control
- Figure 25 - Output Driver Enable (ODE)
- Input Clock Jitter Tolerance
- Non-Multiplexed Microprocessor Port Timing
- Figure 26 - Motorola Non-Multiplexed Bus Timing
- AC Electrical Characteristics - JTAG Test Port Timing
- Figure 27 - JTAG Test Port Timing Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 64 input
streams and 64 output streams
4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
Backplane port accepts 32 input and 32 output
ST-BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
Local port accepts 32 input and 32 output ST-
BUS streams with a fixed data rate of
8.192 Mbps, or 16 input and 16 output ST-BUS
streams with a fixed data rate of 16.384 Mbps
Exceptional input clock jitter tolerance (17 ns)
Per-stream bit delay for Local and Backplane
input streams
Per-stream advancement for Local and Backplane
output streams
Constant 2-frame throughput delay for frame
integrity
Per-channel high impedance output control for
Local and Backplane streams
Per-channel driven-high output control for Local
and Backplane streams
Per-channel message mode for Local and
Backplane output streams
Connection memory block programming for fast
device initialization
December 2003
Ordering Information
ZL50051GAC
256 ball PBGA
ZL50053QCC
256 pin LQFP
-40
C to +85
C
ZL50051/3
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (8 or 16 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Figure 1 - ZL50051/3 Functional Block Diagram
Backplane Data Memories
(4,096 channels)
DS CS R/W
A14-0
DTA
D15-0
Test Port
Microprocessor Interface
and Internal Registers
V
SS (GND)
V
DD_CORE
TDi TDo TCK TRST
TMS
LSTo0-31
(4,096 locations)
RESET
Local
Interface
Connection Memory
BSTi0-31
Input
Timing Unit
FP8i
PLL
LSTi0-31
Interface
Backplane
BSTo0-31
Local
C8i
V
DD_IO
ODE
C8o
C16o
FP8o
FP16o
V
DD_PLL
Output
Timing
Unit
(4,096 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(4,096 channels)
BORS
LORS
ZL50051/3
Data Sheet
2
Zarlink Semiconductor Inc.
Automatic selection between ST-BUS and GCI-Bus operation
Non-multiplexed Motorola microprocessor interface
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
Memory Built-In-Self-Test (BIST), controlled via microprocessor register
1.8 V core supply voltage
3.3 V I/O supply voltage
5 V tolerant inputs, outputs and I/Os
Applications
Central Office Switches (Class 5)
Media Gateways
Class-Independent Switches
Access Concentrators
Scalable TDM-Based Architectures
Digital Loop Carriers
ZL50051/3
Data Sheet
3
Zarlink Semiconductor Inc.
Device Overview
The ZL50051 and ZL50053 are two different packages of the same device. They have the same functionality
except that ZL50053 does not have 16.384 MHz output clock and frame pulse (C16o and FP16o) due to package
differences. The ZL50051/3 has two data ports, the Backplane and the Local port. The device can operate at two
different data rates, 8.192 Mbps or 16.384 Mbps. All 64 input and 64 output streams must operate at the same data
rate.
The ZL50051/3 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
Input-to-Output Unidirectional, supporting 8 K x 8 K switching
Backplane-to-Local Bi-directional, supporting 4 K x 4 K data switching
Local-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
Backplane-to-Backplane Bi-directional, supporting 4 K x 4 K data switching
Local-to-Local Bi-directional, supporting 4 K x 4 K data switching
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel, (stored in data memory), to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-
Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and four
control signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50051 and ZL50053 are each available in one package:
ZL50051: a 17 mm x 17 mm body, 1 mm ball-pitch, 256-PBGA
ZL50053: a 28 mm x 28 mm body, 0.40 mm pin-pitch, 256-LQFP
ZL50051/3
Data Sheet
Table of Contents
4
Zarlink Semiconductor Inc.
1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 18
1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.6.1 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.6.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.1 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 24
4.0 Port High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.0 Device Power-Up, Initialization and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.0 Internal Register Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.0 Detailed Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ZL50051/3
Data Sheet
Table of Contents
5
Zarlink Semiconductor Inc.
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.5 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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