Document Outline

• Features
• Applications
• Description
  • Figure 1 - ZL50070 Functional Block Diagram
• Change Summary
  • Pin Diagram - 23 mm x 23 mm 484 Ball PBGA (as viewed through top of package)
  • Pin Description
• 1.0 Functional Description
  • 1.1 Overview
  • 1.2 Switch Operation
    • Figure 2 - 24 K x 24 K Channel Basic Switch Configuration
    • Table 1 - Data Rate and Maximum Switch Size
  • 1.3 Stream Provisioning
  • 1.4 Input and Output Rate Selection
    • Table 2 - TDM Stream Bit Rates
    • 1.4.1 Per Group Rate Selection
      • Figure 3 - ZL50070 24 K x 24 K Channel and Stream Provisioning Example at Multiple Rates
  • 1.5 Rate Conversion
    • Figure 4 - Input and Output Data Rate Conversion Example
• 2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
  • Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0
• 3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing
• 4.0 Output Channel Control
• 5.0 Data Input Delay and Data Output Advancement
  • 5.1 Input Sampling Point Delay Programming
    • Figure 5 - Input Sampling Point Delay Programming
  • 5.2 Fractional Bit Advancement on Output
    • Figure 6 - Output Bit Advancement Timing
• 6.0 Message Mode
  • 6.1 Data Memory Read
  • 6.2 Connection Memory Block Programming
• 7.0 Data Delay Through the Switching Paths
  • 7.1 Constant Delay Mode
    • Figure 7 - Data Throughput Delay for Constant Delay
  • 7.2 Variable Delay Mode
    • Figure 8 - Data Throughput Delay for Variable Delay
• 8.0 Per-Channel A-Law/u-Law Translation
  • Table 4 - Input and Output Voice and Data Coding
• 9.0 Bit Error Rate Tester
  • Figure 9 - Example PRBS Timeslot Insertion
• 10.0 Microprocessor Port
  • 10.1 Addressing
    • Table 5 - Example of Address and Byte Significance
  • 10.2 32 Bit Bus Operation
    • Table 6 - 32 Bit Motorola Mode Byte Addressing
    • Table 7 - 32 Bit Motorola Mode Access Transfer Size
    • Table 8 - 32 Bit Intel Mode Bus Enable Signals
  • 10.3 16 Bit Bus Operation
    • Table 9 - Byte Enable Signals
    • Table 10 - 16 Bit Mode Word Alignment
    • Table 11 - 16 Bit Mode Example Byte Address
  • 10.4 Bus Operation
    • 10.4.1 Read Cycle
      • Figure 10 - Read Cycle Operation
    • 10.4.2 Write Cycle
      • Figure 11 - Write Cycle Operation
• 11.0 Power-up and Initialization of the ZL50070
  • 11.1 Device Reset and Initialization
  • 11.2 Power Supply Sequencing
  • 11.3 Initialization
• 12.0 IEEE 1149.1 Test Access Port
  • 12.1 Test Access Port (TAP)
  • 12.2 Instruction Register
  • 12.3 Test Data Register
  • 12.4 Boundary Scan Description Language (BSDL)
• 13.0 Memory Map of ZL50070
  • Table 12 - Memory Map
• 14.0 Detailed Memory and Register Descriptions
  • 14.1 Connection Memory
    • Table 13 - Connection Memory Group Address Mapping
    • Table 14 - Connection Memory Stream Address Offset at Various Output Rates
    • Table 15 - Connection Memory Timeslot Address Offset Range
    • 14.1.1 Connection Memory Bit Functions
      • Table 16 - Connection Memory Bits (CMB)
    • 14.1.2 Connection Memory LSB
      • Table 17 - Connection Memory LSB Group Address Mapping
      • Table 18 - Connection Memory LSB Stream Address Offset at Various Output Rates
  • 14.2 Data Memory
    • Table 19 - Data Memory Group Address Mapping
    • Table 20 - Data Memory Stream Address Offset at Various Output Rates
  • 14.3 BER Control Memory and Error Counters
    • 14.3.1 Input BER Enable Control Memory
      • Table 21 - BER Enable Control Memory Group Address Mapping
      • Table 22 - BER Enable Control Memory Stream Address Offset at Various Output Rates
    • 14.3.2 BER Counters
      • Table 23 - BER Counter Group and Stream Address Mapping
  • 14.4 Group Control Registers
    • Table 24 - Group Control Register Addressing
    • Table 25 - Group Control Register
  • 14.5 Input Clock Control Register
    • Table 26 - Input Clock Control Register
  • 14.6 Output Clock Control Register
    • Table 27 - Output Clock Control Register
  • 14.7 Block Init Register
  • 14.8 Block Init Enable Register
    • Table 28 - Block and Power-up Initialization Status Bits
• 15.0 DC/AC Electrical Characteristics
  • Absolute Maximum Ratings1 - Voltages are with respect to ground (VSS) unless otherwise stated.
  • Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
  • DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
  • AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground (VSS) unless otherwise stated.
  • AC Electrical Characteristics1 - FPi0-2 and CKi0-2 Timing
  • Figure 12 - Frame Pulse Input and Clock Input
  • AC Electrical Characteristics1 - FPi and CKi Skew
  • Figure 13 - Frame Skew Timing Diagram
  • AC Electrical Characteristics1 - FPO0-3 and CKO0-3 (65.536 MHz) Timing
  • AC Electrical Characteristics1 - FPO0-3 and CKO0-3 (32.768 MHz) Timing
  • AC Electrical Characteristics1 - FPO0-3 and CKO0-3 (16.384 MHz) Timing
  • AC Electrical Characteristics1 - FPO0-3 and CKO0-3 (8.192 MHz) Timing
  • Figure 14 - ST-Bus Frame Pulse and Clock Output Timing
  • Figure 15 - GCI Frame Pulse and Clock Output Timing
  • AC Electrical Characteristics - Output Clock Jitter Generation
  • AC Electrical Characteristics1 - Serial Data Timing2 to CKi
  • Figure 16 - Serial Data Timing to CKi
  • AC Electrical Characteristics - Serial Data Timing1 to CKo2
  • Figure 17 - Serial Data Timing to CKo
  • AC Electrical Characteristics - CKo to Other CKo1 Skew
  • Figure 18 - CKo to other CKo Skew
  • AC Electrical Characteristics - Microprocessor Bus Interface
  • Figure 19 - Microprocessor Bus Interface Timing
  • Figure 20 - Intel Mode Timing
  • AC Electrical Characteristics1 - IEEE 1149.1 Test Port and PWR Pin Timing
  • Figure 21 - IEEE 1149.1 Test Port & PWR Reset Timing