Document Outline

• Features
  • General
  • Circuit Emulation Services
  • TDM Interfaces
  • Network Interfaces
  • System Interfaces
  • Packet Processing Functions
• Applications
• Description
• Device Line Up
  • Table 1 - Capacity of Devices in the ZL50110/11/14 Family
  • Figure 1 - ZL50110/11/14 High Level Overview
• 1.0 Changes Summary
• 2.0 Physical Specification
  • Figure 2 - ZL50111 Package View and Ball Positions
  • Figure 3 - ZL50110 Package View and Ball Positions
  • Figure 4 - ZL50114 Package View and Ball Positions
• 3.0 External Interface Description
  • 3.1 TDM Interface
    • 3.1.1 ZL50111 Variant TDM Stream Connection
      • Table 2 - TDM Interface ZL50111 Stream Pin Definition
    • 3.1.2 ZL50110 Variant TDM stream connection
      • Table 3 - TDM Interface ZL50110 Stream Pin Definition
    • 3.1.3 ZL50114 Variant TDM Stream Connection
      • Table 4 - TDM Interface ZL50114 Stream Pin Definition
    • 3.1.4 TDM Signals Common to ZL50111, ZL50110 and ZL50114
      • Table 5 - TDM Interface Common Pin Definition
  • 3.2 PAC Interface
    • Table 6 - PAC Interface Package Ball Definition
  • 3.3 Packet Interfaces
    • Table 7 - Packet Interface Signal Mapping - MII to GMII/TBI
    • Table 8 - MII Management Interface Package Ball Definition
    • Table 9 - MII Port 0 Interface Package Ball Definition
    • Table 10 - MII Port 1 Interface Package Ball Definition
    • Table 11 - MII Port 2 Interface Package Ball Definition
    • Table 12 - MII Port 3 Interface Package Ball Definition
  • 3.4 External Memory Interface
    • Table 13 - External Memory Interface Package Ball Definition
  • 3.5 CPU Interface
    • Table 14 - CPU Interface Package Ball Definition
  • 3.6 System Function Interface
    • Table 15 - System Function Interface Package Ball Definition
  • 3.7 Test Facilities
    • 3.7.1 Administration, Control and Test Interface
      • Table 16 - Administration/Control Interface Package Ball Definition
    • 3.7.2 JTAG Interface
      • Table 17 - JTAG Interface Package Ball Definition
  • 3.8 Miscellaneous Inputs
    • Table 18 - Miscellaneous Inputs Package Ball Definitions
  • 3.9 Power and Ground Connections
    • Table 19 - Power and Ground Package Ball Definition
  • 3.10 Internal Connections
    • Table 20 - No Connection Ball Definition
• 4.0 Typical Applications
  • 4.1 Leased Line Provision
    • Figure 5 - Leased Line Services Over a Circuit Emulation Link
  • 4.2 Metropolitan Area Network Aggregation
    • Figure 6 - Metropolitan Area Network Aggregation using CESoP
  • 4.3 Digital Loop Carrier
    • Figure 7 - Digital Loop Carrier using CESoP
  • 4.4 Remote Concentrator
    • Figure 8 - Remote Concentrator using CESoP
  • 4.5 Cell Site Backhaul
    • Figure 9 - Cell Site Backhaul using CESoP
  • 4.6 Metro Ethernet Equipment
    • Figure 10 - Metro Ethernet Equipment using CESoP
• 5.0 Functional Description
  • Figure 11 - ZL50110/11/14 Family Operation
  • 5.1 Block Diagram
    • Figure 12 - ZL50110/11/14 Data and Control Flows
  • 5.2 Data and Control Flows
    • Table 21 - Standard Device Flows
  • 5.3 TDM Interface
    • Table 22 - TDM Services Offered by the ZL50110/11/14 Family
    • 5.3.1 TDM Interface Block
    • 5.3.2 Structured TDM Port Data Formats
      • Table 23 - Some of the TDM Port Formats Accepted by the ZL50110/11/14 Family
    • 5.3.3 TDM Clock Structure
      • 5.3.3.1 Synchronous TDM Clock Generation
        • Figure 13 - Synchronous TDM Clock Generation
      • 5.3.3.2 Asynchronous TDM Clock Generation
  • 5.4 Payload Assembly
    • 5.4.1 Structured Payload Operation
      • Figure 14 - ZL50110/11/14 Packet Format - Structured Mode
      • 5.4.1.1 Structured Payload Order
        • Figure 15 - Channel Order for Packet Formation
    • 5.4.2 Unstructured Payload Operation
      • Figure 16 - ZL50110/11/14 Packet Format - Unstructured Mode
  • 5.5 Protocol Engine
  • 5.6 Packet Transmission
  • 5.7 TDM Formatter
• 6.0 Clock Recovery
  • 6.1 Differential Clock Recovery
    • Figure 17 - Differential Clock Recovery
  • 6.2 Adaptive Clock Recovery
    • Figure 18 - Adaptive Clock Recovery
  • 6.3 SYSTEM_CLK Considerations
• 7.0 System Features
  • 7.1 Latency
  • 7.2 Loopback Modes
  • 7.3 Host Packet Generation
    • Table 24 - DMA Maximum Bandwidths
  • 7.4 Loss of Service (LOS)
  • 7.5 External Memory Requirement
    • Figure 19 - External Memory Requirement for ZL50111
    • Figure 20 - External Memory Requirement for ZL50110
  • 7.6 GIGABIT Ethernet - Recommended Configurations
    • 7.6.1 Central Ethernet Switch
      • Figure 21 - Gigabit Ethernet Connection - Central Ethernet Switch
    • 7.6.2 Redundant Ethernet Switch
      • Figure 22 - Gigabit Ethernet Connection - Redundant Ethernet Switch
  • 7.7 Power Up sequence
    • Figure 23 - Powering Up the ZL50110/11/14
  • 7.8 JTAG Interface and Board Level Test Features
  • 7.9 External Component Requirements
  • 7.10 Miscellaneous Features
  • 7.11 Test Modes Operation
    • 7.11.1 Overview
      • 7.11.1.1 System Normal Mode
      • 7.11.1.2 System Tri-State Mode
    • 7.11.2 Test Mode Control
      • Table 25 - Test Mode Control
    • 7.11.3 System Normal Mode
    • 7.11.4 System Tri-state Mode
• 8.0 DPLL Specification
  • 8.1 Modes of Operation
    • 8.1.1 Locking Mode (normal operation)
      • Table 26 - DPLL Input Reference Frequencies
    • 8.1.2 Holdover Mode
    • 8.1.3 Freerun Mode
    • 8.1.4 Powerdown Mode
  • 8.2 Reference Monitor Circuit
  • 8.3 Locking Mode Reference Switching
  • 8.4 Locking Range
  • 8.5 Locking Time
  • 8.6 Lock Status
  • 8.7 Jitter
    • 8.7.1 Acceptance of Input Wander
    • 8.7.2 Intrinsic Jitter
    • 8.7.3 Jitter Tolerance
    • 8.7.4 Jitter Transfer
  • 8.8 Maximum Time Interval Error (MTIE)
    • Figure 24 - Jitter Transfer Function
    • Figure 25 - Jitter Transfer Function - Detail
• 9.0 Memory Map and Register Definitions
• 10.0 DC Characteristics
  • Absolute Maximum Ratings*
  • Recommended Operating Conditions
  • DC Electrical Characteristics - Typical characteristics are at 1.8V core, 3.3V I/O, 25�C and ty...
  • Input Levels
  • Output Levels
• 11.0 AC Characteristics
  • 11.1 TDM Interface Timing - ST-BUS
    • 11.1.1 ST-BUS Slave Clock Mode
      • TDM ST-BUS Slave Timing Specification
      • Figure 26 - TDM ST-BUS Slave Mode Timing at 8.192Mbps
      • Figure 27 - TDM ST-BUS Slave Mode Timing at 2.048Mbps
    • 11.1.2 ST-BUS Master Clock Mode
      • Table 27 - TDM ST-BUS Master Timing Specification
      • Figure 28 - TDM Bus Master Mode Timing at 8.192Mbps
      • Figure 29 - TDM Bus Master Mode Timing at 2.048Mbps
  • 11.2 TDM Interface Timing - H.110 Mode
    • Table 28 - TDM H.110 Timing Specification
    • Figure 30 - H.110 Timing Diagram
  • 11.3 TDM Interface Timing - H-MVIP
    • Table 29 - TDM H-MVIP Timing Specification
    • Figure 31 - TDM - H-MVIP Timing Diagram for 16MHz Clock (8.192Mbps)
  • 11.4 TDM LIU Interface Timing
    • Table 30 - TDM - LIU Structured Transmission/Reception
    • Figure 32 - TDM-LIU Structured Transmission/Reception
  • 11.5 PAC Interface Timing
    • Table 31 - PAC Timing Specification
  • 11.6 Packet Interface Timing
    • 11.6.1 MII Transmit Timing
      • Table 32 - MII Transmit Timing - 100Mbps
      • Figure 33 - MII Transmit Timing Diagram
    • 11.6.2 MII Receive Timing
      • Table 33 - MII Receive Timing - 100Mbps
      • Figure 34 - MII Receive Timing Diagram
    • 11.6.3 GMII Transmit Timing
      • Table 34 - GMII Transmit Timing - 1000Mbps
      • Figure 35 - GMII Transmit Timing Diagram
    • 11.6.4 GMII Receive Timing
      • Table 35 - GMII Receive Timing - 1000Mbps
      • Figure 36 - GMII Receive Timing Diagram
    • 11.6.5 TBI Interface Timing
      • Table 36 - TBI Timing - 1000Mbps
      • Figure 37 - TBI Transmit Timing Diagram
      • Figure 38 - TBI Receive Timing Diagram
    • 11.6.6 Management Interface Timing
      • Table 37 - MAC Management Timing Specification
      • Figure 39 - Management Interface Timing for Ethernet Port - Read
      • Figure 40 - Management Interface Timing for Ethernet Port - Write
  • 11.7 External Memory Interface Timing
    • Table 38 - External Memory Timing
    • Figure 41 - External RAM Read and Write Timing
  • 11.8 CPU Interface Timing
    • Table 39 - CPU Timing Specification
    • Figure 42 - CPU Read - MPC8260
    • Figure 43 - CPU Write - MPC8260
    • Figure 44 - CPU DMA Read - MPC8260
    • Figure 45 - CPU DMA Write - MPC8260
  • 11.9 System Function Port
    • Table 40 - System Clock Timing
  • 11.10 JTAG Interface Timing
    • Table 41 - JTAG Interface Timing
    • Figure 46 - JTAG Signal Timing
    • Figure 47 - JTAG Clock and Reset Timing
• 12.0 Power Characteristics
  • Figure 48 - ZL50110/11/14 Power Consumption Plot
• 13.0 Design and Layout Guidelines
  • 13.1 High Speed Clock & Data Interfaces
    • 13.1.1 External Memory Interface - special considerations during layout
    • 13.1.2 GMAC Interface - special considerations during layout
    • 13.1.3 TDM Interface - special considerations during layout
    • 13.1.4 Summary
  • 13.2 CPU TA Output
    • Figure 49 - CPU_TA Board Circuit
  • 13.3 Mx_LINKUP_LED Outputs
    • Table 42 - Mx_LINKUP_LED Pin Assignments
    • Figure 50 - Mx_LINKUP_LED Stuffing Option
    • Table 43 - Mx_LINKUP_LED Stuffing Option
• 14.0 Reference Documents
  • 14.1 External Standards/Specifications
  • 14.2 Zarlink Standards
• 15.0 Glossary