Document Outline

• Features
  • General
  • Circuit Emulation Services
  • Customer Side TDM Interfaces
  • Customer Side Packet Interfaces
  • Provider Side Packet Interfaces
  • System Interfaces
  • Packet Processing Functions
• Applications
• 1.0 Changes Summary
• 2.0 Device Line Up
  • Table 1 - Capacity of Devices in the ZL50115/16/17/18/19/20 Family
• 2.0 Description
  • Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
• 3.0 Physical Specification
  • Figure 2 - ZL50115 Package View and Ball Positions
  • Figure 3 - ZL50116 Package View and Ball Positions
  • Figure 4 - ZL50117 Package View and Ball Positions
  • Figure 5 - ZL50118 Package View and Ball Positions
  • Figure 6 - ZL50119 Package View and Ball Positions
  • Figure 7 - ZL50120 Package View and Ball Positions
  • Table 2 - ZL50115/16/17/18/19/20 Ball Signal Assignment (continued)
• 4.0 External Interface Description
  • 4.1 TDM Interface
    • 4.1.1 TDM stream connections
      • Table 3 - TDM Interface Stream Pin Definition
    • 4.1.2 TDM Signals common to ZL50115/16/17/18/19/20
      • Table 4 - TDM Interface Common Pin Definition
  • 4.2 PAC Interface
    • Table 5 - PAC Interface Package Ball Definition
  • 4.3 Packet Interfaces
    • Table 6 - Packet Interface Signal Mapping - MII to GMII/TBI
    • Table 7 - MII Management Interface Package Ball Definition
    • Table 8 - MII Port 0 Interface Package Ball Definition (continued)
    • Table 9 - MII Port 1 Interface Package Ball Definition (continued)
  • 4.4 CPU Interface
    • Table 10 - CPU Interface Package Ball Definition (continued)
  • 4.5 System Function Interface
    • Table 11 - System Function Interface Package Ball Definition
  • 4.6 Test Facilities
    • 4.6.1 Administration, Control and Test Interface
      • Table 12 - Administration/Control Interface Package Ball Definition
    • 4.6.2 JTAG Interface
      • Table 13 - JTAG Interface Package Ball Definition
  • 4.7 Miscellaneous Inputs
    • Table 14 - Miscellaneous Inputs Package Ball Definitions
  • 4.8 Power and Ground Connections
    • Table 15 - Power and Ground Package Ball Definition
  • 4.9 Internal Connections
    • Table 16 - Internal Connections Package Ball Definitions
  • 4.10 No Connections
    • Table 17 - Miscellaneous Inputs Package Ball Definitions
  • 4.11 Device ID
    • Table 18 - Device ID Ball Definition
• 5.0 Typical Applications
  • 5.1 Leased Line Provision
    • Figure 8 - Leased Line Services Over a Circuit Emulation Link
  • 5.2 Remote Concentrator Unit
    • Figure 9 - Remote Concentrator Unit using CESoP
  • 5.3 FTTP
    • Figure 10 - EPON using CESoP
  • 5.4 Wireless - WiFi or WiMAX
    • Figure 11 - Wi-Fi and WiMAX using CESoP
  • 5.5 Digital Loop Carrier
    • Figure 12 - Digital Loop Carrier using CESoP
  • 5.6 Integrated Access Device
    • Figure 13 - Integrated Access Device Using CESoP
• 6.0 Functional Description
  • Figure 14 - ZL50115/16/17/18/19/20 Family Operation
  • 6.1 Block Diagram
    • Figure 15 - ZL50115/16/17/18/19/20 Data and Control Flows
  • 6.2 Data and Control Flows
    • Table 19 - Standard Device Flows
  • 6.3 TDM Interface
    • Table 20 - TDM Services Offered by the ZL50115/16/17/18/19/20 Family
    • 6.3.1 TDM Interface Block
    • 6.3.2 Structured TDM Port Data Formats
      • Table 21 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 Family
    • 6.3.3 TDM Clock Structure
      • 6.3.3.1 Synchronous TDM Clock Generation
        • Figure 16 - Synchronous TDM Clock Generation
      • 6.3.3.2 Asynchronous TDM Clock Generation
  • 6.4 Payload Assembly
    • 6.4.1 Structured Payload Operation
      • Figure 17 - ZL50115/16/17/18/19/20 Packet Format - Structured Mode
      • 6.4.1.1 Payload Order
        • Figure 18 - Channel Order for Packet Formation
    • 6.4.2 Unstructured Payload Operation
      • Figure 19 - ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode
  • 6.5 Protocol Engine
  • 6.6 Packet Transmission
  • 6.7 Packet Reception
  • 6.8 TDM Formatter
  • 6.9 Ethernet Traffic Aggregation (ZL50118/19/20 only)
• 7.0 Clock Recovery
  • 7.1 Differential Clock Recovery
    • Figure 20 - Differential Clock Recovery
  • 7.2 Adaptive Clock Recovery
    • Figure 21 - Adaptive Clock Recovery
• 8.0 System Features
  • 8.1 Latency
  • 8.2 Loopback Modes
  • 8.3 Host Packet Generation
    • Table 22 - DMA Maximum Bandwidths
  • 8.4 Loss of Service (LOS)
  • 8.5 Power Up sequence
    • Figure 22 - Powering Up the ZL5011x
  • 8.6 JTAG Interface and Board Level Test Features.
  • 8.7 External Component Requirements
  • 8.8 Miscellaneous Features
  • 8.9 Test Modes Operation
    • 8.9.1 Overview
      • 8.9.1.1 System Normal Mode
      • 8.9.1.2 System Tri-State Mode
    • 8.9.2 Test Mode Control
      • Table 23 - Test Mode Control
    • 8.9.3 System Normal Mode
    • 8.9.4 System Tri-state Mode
• 9.0 DPLL Specification
  • 9.1 Modes of Operation
    • 9.1.1 Locking Mode (normal operation)
      • Table 24 - DPLL Input Reference Frequencies
    • 9.1.2 Holdover Mode
    • 9.1.3 Freerun Mode
    • 9.1.4 Powerdown Mode
  • 9.2 Reference Monitor Circuit
  • 9.3 Locking Mode Reference Switching
  • 9.4 Locking Range
  • 9.5 Locking Time
  • 9.6 Lock Status
  • 9.7 Jitter
    • 9.7.1 Acceptance of Input Wander
    • 9.7.2 Intrinsic Jitter
    • 9.7.3 Jitter Tolerance
    • 9.7.4 Jitter Transfer
  • 9.8 Maximum Time Interval Error (MTIE)
    • Figure 23 - Jitter Transfer Function
    • Figure 24 - Jitter Transfer Function - Detail
• 10.0 Memory Map and Register Definitions
• 11.0 DC Characteristics
  • Absolute Maximum Ratings*
  • Recommended Operating Conditions
  • DC Electrical Characteristics - Typical characteristics are at 1.8V core, 3.3V I/O, 25�C and ty...
  • Input Levels
  • Output Levels
• 12.0 AC Characteristics
  • 12.1 TDM Interface Timing - ST-BUS
    • 12.1.1 ST-BUS Slave Clock Mode
      • TDM ST-BUS Slave Timing Specification
      • Figure 25 - TDM ST-BUS Slave Mode Timing at 8.192Mbps
      • Figure 26 - TDM ST-BUS Slave Mode Timing at 2.048Mbps
    • 12.1.2 ST-BUS Master Clock Mode
      • Table 25 - TDM ST-BUS Master Timing Specification
      • Figure 27 - TDM Bus Master Mode Timing at 8.192Mbps
      • Figure 28 - TDM Bus Master Mode Timing at 2.048Mbps
  • 12.2 TDM Interface Timing - H.110 Mode
    • Table 26 - TDM H.110 Timing Specification
    • Figure 29 - H.110 Timing Diagram
  • 12.3 TDM Interface Timing - H-MVIP
    • Table 27 - TDM H-MVIP Timing Specification (continued)
    • Figure 30 - TDM - H-MVIP Timing Diagram for 16MHz Clock (8.192Mbps)
  • 12.4 TDM LIU Interface Timing
    • Table 28 - TDM - LIU Structured Transmission/Reception
    • Figure 31 - TDM-LIU Structured Transmission/Reception
  • 12.5 PAC Interface Timing
    • Table 29 - PAC Timing Specification
  • 12.6 Packet Interface Timing
    • 12.6.1 MII Transmit Timing
      • Table 30 - MII Transmit Timing - 100Mbps
      • Figure 32 - MII Transmit Timing Diagram
    • 12.6.2 MII Receive Timing
      • Table 31 - MII Receive Timing - 100Mbps
      • Figure 33 - MII Receive Timing Diagram
    • 12.6.3 GMII Transmit Timing
      • Table 32 - GMII Transmit Timing - 1000Mbps
      • Figure 34 - GMII Transmit Timing Diagram
    • 12.6.4 GMII Receive Timing
      • Table 33 - GMII Receive Timing - 1000Mbps
      • Figure 35 - GMII Receive Timing Diagram
    • 12.6.5 TBI Interface Timing
      • Table 34 - TBI Timing - 1000Mbps
      • Figure 36 - TBI Transmit Timing Diagram
      • Figure 37 - TBI Receive Timing Diagram
    • 12.6.6 Management Interface Timing
      • Table 35 - MAC Management Timing Specification
      • Figure 38 - Management Interface Timing for Ethernet Port - Read
      • Figure 39 - Management Interface Timing for Ethernet Port - Write
  • 12.7 CPU Interface Timing
    • Table 36 - CPU Timing Specification
    • Figure 40 - CPU Read - MPC8260
    • Figure 41 - CPU Write - MPC8260
    • Figure 42 - CPU DMA Read - MPC8260
    • Figure 43 - CPU DMA Write - MPC8260
  • 12.8 System Function Port
    • Table 37 - System Clock Timing
  • 12.9 JTAG Interface Timing
    • Table 38 - JTAG Interface Timing
    • Figure 44 - JTAG Signal Timing
    • Figure 45 - JTAG Clock and Reset Timing
• 13.0 Power Characteristics
  • Figure 46 - ZL50115/16/17/18/19/20 Power Consumption Plot
• 14.0 Design and Layout Guidelines
  • 14.1 High Speed Clock & Data Interfaces
    • 14.1.1 GMAC Interface - Special Considerations During Layout
    • 14.1.2 TDM Interface - Special Considerations During Layout
    • 14.1.3 Summary
  • 14.2 CPU TA Output
    • Figure 47 - CPU_TA Board Circuit
• 15.0 Reference Documents
  • 15.1 External Standards/Specifications
  • 15.2 Zarlink Standards
• 16.0 Glossary