1
Features
Independent multiple channels of echo
cancellation; from 8 channels of 64ms to 4
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
Independent Power Down mode for each group of
2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed AT&T voice quality testing for carrier
grade echo cancellers.
Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
PCM coding,
/A-Law ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
Protection against narrow band signal divergence
and instability in high echo environments
0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
Voice over IP network gateways
Voice over ATM, Frame Relay
T1/E1/J1 multichannel echo cancellation
Wireless base stations
Echo Canceller pools
DCME, satellite and multiplexer system
March 2003
Ordering Information
ZL50234/QCC 100-Pin LQFP
ZL50234/GDC 208-Ball LBGA
-40
C to +85
C
ZL50234
8 Channel Voice Echo Canceller
Data Sheet
Figure 1 - ZL50234 Device Overview
RESET
Rout
Sout
DS CS R/W A10-A0 DTA
D7-D0
V
SS
V
DD1 (3.3V)
TDI TDO TCK TRST
TMS
Rin
IRQ
C4i
F0i
MCLK
ODE
Sin
Fsel
Test Port
Microprocessor Interface
Timing
Unit
Serial
to
Parallel
Parallel
to
Serial
PLL
Note:
Refer to Figure 4
for Echo Canceller
block diagram
V
DD2 (1.8V)
Echo Canceller Pool
Group 0
ECA/ECB
Group 1
ECA/ECB
Group 2
ECA/ECB
Group 3
ECA/ECB
ZL50234
Data Sheet
2
Zarlink Semiconductor Inc.
Description
The ZL50234 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation
conforming to ITU-T G.168 requirements. The ZL50234 architecture contains 4 groups of two echo cancellers (ECA
and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds
echo cancellation. This provides 8 channels of 64 milliseconds to 4 channels of 128 milliseconds echo cancellation
or any combination of the two configurations. The ZL50234 supports ITU-T G.165 and G.164 tone disable
requirements.
Figure 2 - 100 Pin LQFP
31
30
50
17
11
9
72
5
23
21
19
35
1
3
1
5
1
D7
D6
D5
D4
D3
D2
D1
D0
CS
DS
VSS
NC
R/W
DTA
2
4
6
8
10
12
14
1
6
18
20
22
2
4
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
29
28
27
26
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
100
77
99
76
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
A1
A2
A3
A4
A5
A0
V
DD1
VDD2
NC
VSS
A6
A7
A8
A9
A1
0
VSS
V
DD2
V
DD1
VSS
VSS
PL
L
VSS2
NC
ODE
Sout
Rout
Sin
NC
NC
VSS
C4ib
Foib
Rin
VDD2
V
DD2
Mcl
k
fs
e
l
PL
L
VSS1
PL
L
V
D
D
V
DD1
TMS
TDI
TDO
TCK
VSS
TRSTB
RESETB
IRQB
ZL50234QC
NC
(100 pin LQFP)
V
DD1
= 3.3V
V
DD2
= 1.8V
NC
V
DD1
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IC0
IC0
IC0
IC0
IC
0
IC0
IC0
IC0
IC0
IC
0
IC
0
IC
0
IC
0
IC
0
IC
0
NC
Data Sheet
ZL50234
3
Zarlink Semiconductor Inc.
Figure 3 - 208 Ball LBGA
B
C
D
E
F
G
H
J
K
L
M
N
1
2
3
4
5
6
7
8
9
10
11
12
13
1
- A1 corner is identified by metallized markings.
A
14
15
16
P
R
T
1
V
DD2
c4i
F0i
Rin
Sin
Rout
ODE
A1
Sout
MCLK
Fsel
TMS
TDI
TCK
RESET
IRQ
DS
CS
R/W
DTA
D0
D1
D2
D4
D5
D6
D7
A10
A9
A8
A7
A6
A5
A4
A3
A2
ZL50234GD
V
DD1
IC0
PLLVSS PLLVDD
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
IC0
VDD1
V
SS
NC
NC
TDO
TRST
A0
D3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD1
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
DD2
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD1
ZL50234
Data Sheet
4
Zarlink Semiconductor Inc.
Pin Description
PIN
Name
PIN #
Description
208-Ball LBGA
100 PIN
LQFP
V
SS
A1, A3,A7,A11, A13,
A15, A16, B2, B6, B8,
B12, B14, B15, B16, C3,
C5, C7, C9, C11, C12,
C13, C14, C16, D4, D8,
D10, D12, D13, E3, E4,
E14, F13, G3, G4, G7,
G8, G9, G10, H7, H8,
H9, H10, H13, H14, J7,
J8, J9, J10, K7, K8, K9,
K10, K13, K14, L3, L4,
M13, M14, M15, N3, N4,
N5, N7, N9, N11, N13,
P2, P3, P5, P7, P9,P11,
P13, P14, R2, R14,
R15, R16, T1, T3, T7,
T10, T14, T16
5, 18, 32,
42, 56, 69,
81, 98
Ground.
V
DD1
A5, A9, B10, C4, C8,
B4, C10, D3, D5, D7,
D9, D11, D14, E13, F3,
F4, F14, H3, H4, J13,
J14, L13, L14, M3, M4,
N6, N8, N10, N14, N15,
P4, P6, P8, P10, P15,
R4, R6, R8, R10, R12,
T5, T12
27, 48, 77,
100
Positive Power Supply V
DD1.
Nominally 3.3 Volt.
V
DD2
C6, D6, J3, J4, N12,
P12, G13, G14
14, 37, 64,
91
Positive Power Supply V
DD2
. Nominally 1.8 Volts.
IC0
E15, F15, A12, A10, A6,
A2, B1, B3, C1, C2, D2,
E2, J2, K2, R1
7, 41, 43,
65, 66, 67,
68, 70, 71,
72, 86, 87,
88, 93, 94
Internal Connection. These pins must be connected to V
SS
for
normal operation.
NC
A14, C15, D1, D15, E1,
F1, G1, G15, H1, H15,
J1, J15, K1,
K15,L1,L15,F2,L2
24, 25, 26,
44, 45, 46,
47, 49, 51,
52, 53, 54,
55, 73, 74,
75, 76, 78,
79, 80, 82,
83, 84, 85,
89, 99, 50
No connection. These pins must be left open for normal
operation.
IRQ
R9
9
Interrupt Request (Open Drain Output).
This output goes low
when an interrupt occurs in any channel. IRQ returns high when
all the interrupts have been read from the Interrupt FIFO
Register. A pull-up resistor (1K typical) is required at this output.
Data Sheet
ZL50234
5
Zarlink Semiconductor Inc.
DS
R11
10
Data Strobe (Input). This active low input works in conjunction
with CS to enable the read and write operations.
CS
R13
11
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R/W
R5
12
Read/Write (Input). This input controls the direction of the data
bus lines (D7-D0) during a microprocessor access.
DTA
R7
13
Data Transfer Acknowledgment (Open Drain Output). This
active low output indicates that a data bus transfer is completed.
A pull-up resistor (1K typical) is required at this output.
D0..D7
T2,T4,T6,T8,T9,T11,
T13,T15
15, 16, 17,
19, 20, 21,
22, 23
Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
bidirectional data bus of the microprocessor port.
A0..A10
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16,
D16
28, 29, 30,
31, 33, 34,
35, 36, 38,
39, 40
Address A0 to A10 (Input). These inputs provide the A10 - A0
address lines to the internal registers.
ODE
B13
57
Output Drive Enable (Input). This input pin is logically AND'd
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Sout
A8
58
Send PCM Signal Output (Output). Port 1 TDM data output
streams. Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Rout
B9
59
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
Sin
B11
60
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 8
channels per stream.
Rin
B7
61
Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at 2.048 Mb/s
with 8 channels per stream.
F0i
B5
62
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
C4i
A4
63
Serial Clock (Input). 4.096 MHz serial clock for shifting data
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
G2
90
Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Pin Description (continued)
PIN
Name
PIN #
Description
208-Ball LBGA
100 PIN
LQFP
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