Document Outline
- Features
- Description
- 1.0 BGA and Ball Signal Descriptions
- 1.1 BGA Views (Top-View)
- 1.2 Power and Ground Distribution
- 1.3 Ball Signal Descriptions
- 1.4 Signal Mapping and Internal pull-up/Down Configuration
- 1.5 Bootstrap Options
- 1.5.1 Recommended Default Bootstrap Settings
- 1.6 Default Switch Configuration and Initialization Sequence
- 2.0 Block Functionality
- 2.1 Internal Memory
- 2.2 MAC Modules
- 2.2.1 RMII MAC Module (RMAC)
- 2.2.1.1 GPSI (7WS) Interface
- 2.2.2 CPU MAC Module (CMAC)
- 2.2.3 MII MAC Module (MMAC)
- 2.2.4 PHY Addresses
- 2.3 Management Module
- 2.4 Frame Engine
- 2.5 Search Engine
- 2.6 Heartbeat Packet Generation and Response
- 2.7 Timeout Reset Monitor
- 2.8 JTAG
- 3.0 Management and Configuration
- 3.1 Register Configuration, Frame Transmission, and Frame Reception
- 3.1.1 Register Configuration
- 3.1.2 Rx/Tx of Standard Ethernet Frames
- 3.1.3 Control Frames
- 3.2 I2C Interface
- 3.2.1 Start Condition
- 3.2.2 Address
- 3.2.3 Data Direction
- 3.2.4 Acknowledgment
- 3.2.5 Data
- 3.2.6 Stop Condition
- 3.3 Synchronous Serial Interface
- 3.3.1 Write Command
- 3.3.2 Read Command
- 4.0 Data Forwarding Protocol
- 4.1 Unicast Data Frame Forwarding
- 4.2 Multicast Data Frame Forwarding
- 4.3 Frame Forwarding To and From CPU
- 5.0 Search Engine
- 5.1 Search Engine Overview
- 5.2 Basic Flow
- 5.3 Search, Learning, and Aging
- 5.3.1 MAC Search
- 5.3.2 Learning
- 5.3.3 Aging
- 5.4 MAC Address Filtering
- 5.5 Protocol Filtering
- 5.6 Logical Port Filtering
- 5.7 Quality of Service
- 5.8 Priority Classification Rule
- 5.9 Port Based VLAN
- 6.0 Frame Engine
- 6.1 Data Forwarding Summary
- 6.2 Frame Engine Details
- 6.2.1 FCB Manager
- 6.2.2 Rx Interface
- 6.2.3 RxDMA
- 6.2.4 TxQ Manager
- 6.2.5 Port Control
- 6.2.6 TxDMA
- 7.0 Quality of Service and Flow Control
- 7.1 Model
- 7.2 Two QoS Configurations
- 7.2.1 Strict Priority
- 7.2.2 Weighted Fair Queuing
- 7.3 WRED Drop Threshold Management Support
- 7.4 Shaper
- 7.5 Rate Control
- 7.6 Buffer Management
- 7.6.1 Dropping When Buffers Are Scarce
- 7.7 Flow Control Basics
- 7.7.1 Unicast Flow Control
- 7.7.2 Multicast Flow Control
- 7.8 Mapping to IETF Diffserv Classes
- 7.9 Failover Backplane Feature
- 8.0 Port Trunking
- 8.1 Features and Restrictions
- 8.2 Unicast Packet Forwarding
- 8.3 Multicast Packet Forwarding
- 9.0 Traffic Mirroring
- 9.1 Mirroring Features
- 9.2 Using port mirroring for loop back
- 10.0 Clocks
- 10.1 Clock Requirements
- 10.1.1 System Clock (SCLK) speed requirement
- 10.1.2 RMAC Reference Clock (M_CLK) speed requirement
- 10.1.3 MMAC Reference Clock (REF_CLK) speed requirement
- 10.1.4 JTAG Test Clock (TCK) speed requirements
- 10.2 Clock Generation
- 10.2.1 MDC
- 10.2.2 SCL
- 10.2.3 Ethernet Interface Clocks
- 11.0 Hardware Statistics Counters
- 11.1 Hardware Statistics Counters List
- 11.2 IEEE 802.3 HUB Management (RFC 1516)
- 11.2.1 Event Counters
- 11.2.1.1 ReadableOctet
- 11.2.1.2 ReadableFrame
- 11.2.1.3 FCSErrors
- 11.2.1.4 AlignmentErrors
- 11.2.1.5 FrameTooLongs
- 11.2.1.6 ShortEvents
- 11.2.1.7 Runts
- 11.2.1.8 Collisions
- 11.2.1.9 LateEvents
- 11.2.1.10 VeryLongEvents
- 11.2.1.11 DataRateMisatches
- 11.2.1.12 AutoPartitions
- 11.2.1.13 TotalErrors
- 11.3 IEEE 802.1 Bridge Management (RFC 1286)
- 11.3.1 Event Counters
- 11.3.1.1 InFrames
- 11.3.1.2 OutFrames
- 11.3.1.3 InDiscards
- 11.3.1.4 DelayExceededDiscards
- 11.3.1.5 MtuExceededDiscards
- 11.4 RMON Ethernet Statistic Group (RFC 1757)
- 11.4.1 Event Counters
- 11.4.1.1 Drop Events
- 11.4.1.2 Octets
- 11.4.1.3 BroadcastPkts
- 11.4.1.4 MulticastPkts
- 11.4.1.5 CRCAlignErrors
- 11.4.1.6 UndersizePkts
- 11.4.1.7 OversizePkts
- 11.4.1.8 Fragments
- 11.4.1.9 Jabbers
- 11.4.1.10 Collisions
- 11.4.1.11 Packet Count for Different Size Groups
- 11.5 Miscellaneous Counters
- 12.0 Register Definition
- 12.1 ZL50400 Register Description
- 12.2 Directly Accessed Registers
- 12.2.1 INDEX_REG0
- 12.2.2 DATA_FRAME_REG
- 12.2.3 CONTROL_FRAME_REG
- 12.2.4 COMMAND&STATUS Register
- 12.2.5 Interrupt Register
- 12.2.6 Control Command Frame Buffer1 Access Register
- 12.2.7 Control Command Frame Buffer2 Access Register
- 12.3 Indirectly Accessed Registers
- 12.3.1 (Group 0 Address) MAC Ports Group
- 12.3.1.1 ECR1Pn: Port n Control Register
- 12.3.1.2 ECR2Pn: Port n Control Register
- 12.3.1.3 ECR3Pn: Port n Control Register
- 12.3.1.4 ECR4Pn: Port n Control Register
- 12.3.1.5 BUF_LIMIT Frame Buffer Limit
- 12.3.1.6 FCC Flow Control Grant Period
- 12.3.2 (Group 1 Address) VLAN Group
- 12.3.2.1 AVTCL VLAN Type Code Register Low
- 12.3.2.2 AVTCH VLAN Type Code Register High
- 12.3.2.3 PVMAP00_0 Port 0 Configuration Register 0
- 12.3.2.4 PVMAP00_1 Port 0 Configuration Register 1
- 12.3.2.5 PVMAP00_3 Port 0 Configuration Register 3
- 12.3.2.6 PVMAPnn_0,1,3 Ports 1~9 Configuration Registers
- 12.3.2.7 PVMODE
- 12.3.3 (Group 2 Address) Port Trunking Groups
- 12.3.3.1 TRUNKn Trunk Group 0~7
- 12.3.3.2 TRUNKn_HASH10 Trunk group n hash result 1/0 destination port number
- 12.3.3.3 TRUNKn_HASH32 Trunk group n hash result 3/2 destination port number
- 12.3.3.4 TRUNKn_HASH54 Trunk group n hash result 5/4 destination port number
- 12.3.3.5 TRUNKn_HASH76 Trunk group n hash result 7/6 destination port number
- 12.3.3.6 MULTICAST_HASHn-0 Multicast hash result 0~7 mask byte 0
- 12.3.3.7 MULTICAST_HASHn-1 Multicast hash result 0~7 mask byte 1
- 12.3.4 (Group 3 Address) CPU Port Configuration Group
- 12.3.4.1 MAC0 CPU MAC address byte 0
- 12.3.4.2 MAC1 CPU MAC address byte 1
- 12.3.4.3 MAC2 CPU MAC address byte 2
- 12.3.4.4 MAC3 CPU MAC address byte 3
- 12.3.4.5 MAC4 CPU MAC address byte 4
- 12.3.4.6 MAC5 CPU MAC address byte 5
- 12.3.4.7 INT_MASK0 Interrupt Mask
- 12.3.4.8 INTP_MASK0 Interrupt Mask for MAC Port 0,1
- 12.3.4.9 INTP_MASKn Interrupt Mask for MAC Ports 2~9 Registers
- 12.3.4.10 RQS Receive Queue Select
- 12.3.4.11 RQSS Receive Queue Status
- 12.3.4.12 MAC01 Increment MAC port 0,1 address
- 12.3.4.13 MAC23 Increment MAC port 2,3 address
- 12.3.4.14 MAC45 Increment MAC port 4,5 address
- 12.3.4.15 MAC67 Increment MAC port 6,7 address
- 12.3.4.16 MAC9 Increment MAC port 9 address
- 12.3.4.17 CPUQINS0 - CPUQINS6 CPU Queue Insertion Command
- 12.3.4.18 CPUQINSRPT CPU Queue Insertion Report
- 12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 CPU Allocated Granule Pointer
- 12.3.4.20 CPURLSINFO0 - CPURLSINFO4 Receive Queue Status
- 12.3.4.21 CPUGRNCTR CPU Granule Control
- 12.3.5 (Group 4 Address) Search Engine Group
- 12.3.5.1 AGETIME_LOW MAC address aging time Low
- 12.3.5.2 AGETIME_HIGH MAC address aging time High
- 12.3.5.3 SE_OPMODE Search Engine Operation Mode
- 12.3.6 (Group 5 Address) Buffer Control/QOS Group
- 12.3.6.1 QOSC QOS Control
- 12.3.6.2 UCC Unicast Congestion Control
- 12.3.6.3 MCC Multicast Congestion Control
- 12.3.6.4 MCCTH Multicast Threshold Control
- 12.3.6.5 RDRC0 WRED Rate Control 0
- 12.3.6.6 RDRC1 WRED Rate Control 1
- 12.3.6.7 RDRC2 WRED Rate Control 2
- 12.3.6.8 SFCB Share FCB Size
- 12.3.6.9 C1RS Class 1 Reserve Size
- 12.3.6.10 C2RS Class 2 Reserve Size
- 12.3.6.11 C3RS Class 3 Reserve Size
- 12.3.6.12 AVPML VLAN Tag Priority Map
- 12.3.6.13 AVPMM VLAN Priority Map
- 12.3.6.14 AVPMH VLAN Priority Map
- 12.3.6.15 AVDM VLAN Discard Map
- 12.3.6.16 TOSPML TOS Priority Map
- 12.3.6.17 TOSPMM TOS Priority Map
- 12.3.6.18 TOSPMH TOS Priority Map
- 12.3.6.19 TOSDML TOS Discard Map
- 12.3.6.20 USER_PROTOCOL_n User Define Protocol 0~7
- 12.3.6.21 USER_PROTOCOL_FORCE_DISCARD User Define Protocol 0~7 Force Discard
- 12.3.6.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority
- 12.3.6.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority
- 12.3.6.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority
- 12.3.6.25 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority
- 12.3.6.26 WELL_KNOWN_PORT_ENABLE Well Known Logic Port 0 to 7 Enables
- 12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD Well Known Logic Port 0~7 Force Discard
- 12.3.6.28 USER_PORT[7:0]_[LOwithHIGH] User Define Logical Port 0~7
- 12.3.6.29 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
- 12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
- 12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
- 12.3.6.32 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
- 12.3.6.33 USER_PORT_ENABLE[7:0] User Define Logic Port 0 to 7 Enables
- 12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] User Define Logic Port 0~7 Force Discard
- 12.3.6.35 RLOWL User Define Range Low Bit 7:0
- 12.3.6.36 RLOWH User Define Range Low Bit 15:8
- 12.3.6.37 RHIGHL User Define Range High Bit 7:0
- 12.3.6.38 RHIGHH User Define Range High Bit 15:8
- 12.3.6.39 RPRIORITY User Define Range Priority
- 12.3.7 (Group 6 Address) MISC Group
- 12.3.7.1 MII_OP0 MII Register Option 0
- 12.3.7.2 MII_OP1 MII Register Option 1
- 12.3.7.3 FEN Feature Register
- 12.3.7.4 MIIC0 MII Command Register 0
- 12.3.7.5 MIIC1 MII Command Register 1
- 12.3.7.6 MIIC2 MII Command Register 2
- 12.3.7.7 MIIC3 MII Command Register 3
- 12.3.7.8 MIID0 MII Data Register 0
- 12.3.7.9 MIID1 MII Data Register 1
- 12.3.7.10 USD One Micro Second Divider
- 12.3.7.11 DEVICE Mode
- 12.3.7.12 CHECKSUM - EEPROM Checksum
- 12.3.7.13 LHBTimer Link Heart Beat Timeout Timer
- 12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode
- 12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
- 12.3.7.16 FCB Base Address Register 0
- 12.3.7.17 FCB Base Address Register 1
- 12.3.7.18 FCB Base Address Register 2
- 12.3.8 (Group 7 Address) Port Mirroring Group
- 12.3.8.1 MIRROR CONTROL Port Mirror Control Register
- 12.3.8.2 MIRROR_DEST_MAC[5:0] Mirror Destination MAC Address 0~5
- 12.3.8.3 MIRROR_SRC _MAC[5:0] Mirror Source MAC Address 0~5
- 12.3.8.4 RMAC_MIRROR0 RMAC Mirror 0
- 12.3.8.5 RMAC_MIRROR1 RMAC Mirror 1
- 12.3.9 (Group 8 Address) Per Port QOS Control
- 12.3.9.1 FCRn Port 0~9 Flooding Control Register
- 12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control
- 12.3.9.3 PR100_n Port 0~7 Reservation
- 12.3.9.4 PR100_CPU Port CPU Reservation
- 12.3.9.5 PRM Port MMAC Reservation
- 12.3.9.6 PTH100_n Port 0~7 Threshold
- 12.3.9.7 PTH100_CPU Port CPU Threshold
- 12.3.9.8 PTHG Port MMAC Threshold
- 12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0
- 12.3.9.10 QOSC02, QOSC15 - Classes Byte Limit port 1-7
- 12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port
- 12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit MMAC port
- 12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For MMAC
- 12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port MMAC
- 12.3.10 (Group E Address) System Diagnostic
- 12.3.10.1 DTSRL Test Output Selection
- 12.3.10.2 DTSRM Test Output Selection
- 12.3.10.3 TESTOUT0, TESTOUT1 Testmux Output [7:0], [15:8]
- 12.3.10.4 MASK0-MASK4 Timeout Reset Mask
- 12.3.10.5 BOOTSTRAP0 BOOTSTRAP3
- 12.3.10.6 PRTFSMST0~9
- 12.3.10.7 PRTQOSST0-PRTQOSST7
- 12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port)
- 12.3.10.9 PRTQOSST9A, PRTQOSST9B (MMAC port)
- 12.3.10.10 CLASSQOSST
- 12.3.10.11 PRTINTCTR
- 12.3.10.12 QMCTRL0~9
- 12.3.10.13 QCTRL
- 12.3.10.14 BMBISTR0, BMBISTR1
- 12.3.10.15 BMControl
- 12.3.10.16 BUFF_RST
- 12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1
- 12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1
- 12.3.10.19 FCB_NUM0, FCB_NUM1
- 12.3.10.20 BM_RLSFF_CTRL
- 12.3.10.21 BM_RSLFF_INFO[5:0]
- 12.3.11 (Group F Address) CPU Access Group
- 12.3.11.1 GCR - Global Control Register
- 12.3.11.2 DCR - Device Status and Signature Register
- 12.3.11.3 DCR1 - Device Status Register 1
- 12.3.11.4 DPST Device Port Status Register
- 12.3.11.5 DTST Data read back register
- 12.3.11.6 DA Dead or Alive Register
- 13.0 Characteristics and Timing
- 13.1 Absolute Maximum Ratings
- 13.2 DC Electrical Characteristics
- 13.3 Recommended Operating Conditions
- 13.4 AC Characteristics and Timing
- 13.4.1 Typical Reset & Bootstrap Timing Diagram
- 13.4.2 Reduced Media Independent Interface
- 13.4.3 Media Independent Interface
- 13.4.4 General Purpose Serial Interface (7-wire)
- 13.4.5 MDIO Input Setup and Hold Timing
- 13.4.6 IC Input Setup Timing
- 13.4.7 Serial Interface Setup Timing
- 13.4.8 JTAG (IEEE 1149.1-2001)
- 14.0 Document History
- 14.1 July 2003
- 14.2 November 2003
- 14.3 February 2004
- 14.4 August 2004
- 14.5 November 2004
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Integrated Single-Chip 10/100 Ethernet Switch
Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
Embedded 2 Mbits (256 KBytes) internal memory
supports up to 4 K byte frames
L2 switching
MAC address self learning, up to 4 K MAC
addresses using internal table
Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
Supports Ethernet multicasting and
broadcasting and flooding control
VLAN Support
Supports port-based VLAN
CPU access supports the following interface
options:
Serial interface in lightly managed mode, or in
unmanaged mode with optional I
2
C EEPROM
interface
Failover Features
Rapid link failure detection using
hardware-generated heartbeat packets
link failover in less than 50 ms
Rate Control (both ingress and egress)
Bandwidth rationing, Bandwidth on demand,
SLA (Service Level Agreement)
Smooth out traffic to uplink port
Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
Egress Rate Control
Down to 16 kbps Rate Control granularity
Per queue traffic shaper on uplink port
January 2005
Ordering Information
ZL50400GDC
208 Pin LBGA
-40
C to +85C
ZL50400
Lightly Managed/Unmanaged
9-Port 10/100 M Ethernet Switch
Data Sheet
Figure 1 - System Block Diagram
9-Port 10/100M
Ethernet Switch
Quad
10/100
PHY
Quad
10/100
PHY
10/100
PHY
C
P
U
EEPROM
I
2
C
RMII / MII / GPSI
MII
Serial
ZL50400
ZL50400
Data Sheet
2
Zarlink Semiconductor Inc.
Packet Filtering and Port Security
Static address filtering for source and/or destination MAC
Static MAC address not subject to aging
Secure mode freezes MAC address learning (each port may independently use this mode)
Supports port authentication (IEEE 802.1x)
QoS Support
Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with
strict priority and/or WFQ service disciplines
Provides 2 levels of dropping precedence with WRED mechanism
User controls the WRED thresholds.
Buffer management: per class and per port buffer reservations
Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
Classification based on:
Port based priority
VLAN Priority field in VLAN tagged frame
DS/TOS field in IP packet
UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
The precedence of the above classifications is programmable
Supports IEEE 802.3ad link aggregation
Up to 8 trunk groups, with up to 8 ports per group
Supports load sharing among trunk ports based on:
- Source port
- Source and/or destination MAC address
Supports module hot swap on all ports
MIB Statistics counters for all ports
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
Built-in reset logic triggered by system malfunction
Built-In Self Test for internal SRAM
IEEE-1149.1 (JTAG) test port
ZL50400
Data Sheet
3
Zarlink Semiconductor Inc.
Description
The ZL50400 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for lightly managed and
unmanaged switch applications. The chip supports up to 4 K MAC addresses and port-based Virtual LANs
(VLANs).
With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50400 provides
powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission
priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission
priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or
the UDP/TCP logical port fields in IP packets. The ZL50400 recognizes a total of 16 UDP/TCP logical ports, 8
hard-wired and 8 programmable (including one programmable range).
The ZL50400 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure
to the CPU. The CPU can then failover that link to an alternate link.
The ZL50400 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50400 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network
management solution.
The ZL50400 is fabricated using 0.18 micron technology. The ZL50400 is packaged in a 208-pin Ball Grid Array
package.
ZL50400
Data Sheet
Table of Contents
4
Zarlink Semiconductor Inc.
1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Ball Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Signal Mapping and Internal pull-up/Down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 Recommended Default Boostrap Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Default Switch Configuration and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 MAC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1.1 GPSI (7WS) Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 CPU MAC Module (CMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.3 MII MAC Module (MMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 PHY Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Heartbeat Packet Generation and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.0 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ZL50400
Data Sheet
Table of Contents
5
Zarlink Semiconductor Inc.
5.8 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.6 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Two QoS Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.1 Strict Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.2 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.5 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.7 Flow Control Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.7.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.8 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.9 Failover Backplane Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.0 Traffic Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.0 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.1 System Clock (SCLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.2 RMAC Reference Clock (M_CLK) speed requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.3 MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1.4 JTAG Test Clock (TCK) speed requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2.3 Ethernet Interface Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1.3 FCSErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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