Document Outline
- Features
- Applications
- Description
- Figure 1 - ZL70100 Block Diagram
- 1.0 Functional Description
- 1.1 General
- 1.2 Basic Operation and Modes
- 2.0 Example Configurations
- Figure 2 - MICS Transceiver Configured for an Implant
- Figure 3 - MICS Transceiver Configured for a Basestation
- 3.0 Electrical Characteristics
- Absolute Maximum ratings - Voltages are with respect to ground (VSS) unless otherwise stated.
- Recommended Operating Conditions - Note1
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
402-405 MHz (10 MICS channels) and
433-434 MHz (2 ISM channels)
High data rate (800/400/200 kbps raw data rate)
High performance MAC with automatic error
handling and flow control, typ < 1.5x10
-10
BER.
Very few external components
(2 pcs + antenna matching)
Extremely low power consumption (5 mA,
continuous TX/RX, <1 mA low power mode)
Ultra low power wakeup circuit (200 nA)
Standards compatible (MICS, FCC, IEC)
Applications
Implantable Devices e.g., Pacemakers, ICD's,
Cochlea implants, Neurostimulators, Implantable
Insulin Pumps, Bladder Control Devices,
implantable physiological monitors
Body area network, short range device
applications using the 433 MHz ISM band.
Description
The ZL70100 is a high performance half duplex RF
communications link for medical implantable
applications. The system is very flexible and supports
several low power wakeup options. Extremely low
power is achievable using the 2.45 GHz ISM Band
Wakeup-receiver option. The high level of integration
includes a Media Access Controller, providing
complete control of the device along with coding and
decoding of RF messages. A standard SPI interface
provides for easy access by the application
For further information please contact sales.
May 2005
Ordering Information
ZL70100LDF1 - 48 pin QFN* (tape & reel,
bake
and
drypack)
ZL70100LDG1 -48 pin QFN* (tray, bake and
drypack)
*Pb Free Matte Tin
0
C to +55
C
ZL70100
Medical Implantable RF Transceiver
Data Sheet
Figure 1 - ZL70100 Block Diagram
Zarlink MICS Transceiver - ZL70100
R X
T X
24 MHz
+
Correlator
Clock
Recovery
RX Control
Message
Storage
CRC
Decode
RS Decode
Control
Message
Storage
TX Control
CRC
Generation
RS
Encoder
Wake-Up
Control
Whitening
Interface
SPI
TX IF Modulator
R X
Regulator
1.85-2.0V
RF 2.45 GHz
RF 400 MHz
RF 400 MHz
Media Access Controller
2.45 GHz Wake-Up Receiver
400 MHz Transceiver
VD
D
A
VSU
P
RX
2.45 GHz
RX
400 MHz
TX
400 MHz
XT
A
L
2
XT
A
L
1
Peak Detector
Mixer
Mixer
Power Amplifier
Low Noise
Amplifier
5bit
ADC
Ultra Low
Power
Oscillator
VD
D
D
VD
D
I
O
VSSD
VS
SA
ADC analog Inputs
(TESTIO[4:1] pins)
Analog Inputs
RX IF Filter and FM Detector
RX
ADC
PLL
DataBus
RSSI
tx_clk
tx_data
rx_data
4
4
To ADC Mux
Antenna
Matching
Antenna
Matching
Enable
Battery or
Other Supply
WU_EN
PDCTRL
MODE[1:0]
XO_BY PASS
Test Mode Control
Input Pin Pull-down Control
Bypass of on-chip Crystal Oscillator Control
Select IMD or Base Transceiver
Wakeup IMD
SPI_SDO
SPI_SDI
SPI_CLK
SPI_CS_B
PO[3:0]
IRQ
PI[2:0]
4
3
2
SPI
Interf ace
Programmable
IO
68 nF Decoupling
Capacitor
Ana
l
og T
e
s
t
TE
S
T
IO
[6
:5
]
2
IBS
ZL70100
Data Sheet
2
Zarlink Semiconductor Inc.
1.0 Functional Description
1.1 General
The ZL70100 is an ultra low power, high bandwidth RF link for medical implantable applications. It operates in the
MICS (Medical Implantable Service Band) at 402-405 MHz. It uses a Reed-Solomon coding scheme together with
CRC error detection to achieve an extremely reliable link. For data-blocks, a maximum BER (Bit Error Rate) of less
than 1.5x10
-10
is provided assuming a raw radio channel quality of 10
-3
BER. An even higher quality of 2x10
-14
BER is available using Housekeeping messages, a facility fully described in the ZL70100 Design Manual.
1.2 Basic Operation and Modes
The MICS transceiver is intended for operation in both an Implant and Basestation. These systems have different
requirements especially with regard to power consumption. Therefore, the MICS transceiver has defined two
fundamental startup modes of operation:
Implantable Medical Device (IMD) Mode
Basestation Mode
When configured as an IMD, the transceiver is usually asleep and in a very low current state. The IMD transceiver
may be woken up by either receipt of a specially coded 2.45 GHz wakeup message or directly by the IMD
processor via the WU_EN pin. This flexibility leads to the following options for waking up an IMD transceiver for
communication.
IMD transceiver woken up by specially coded 2.45 GHz wakeup message using an ultra low power sniffing
method.
IMD transceiver woken up to sniff 400 MHz link. The ZL70100 supports such a mode of operation although
the 2.45 GHz wakeup system has lower power consumption.
IMD transceiver woken to send an emergency message in which case no clear channel assessment by the
Basestation is required.
IMD transceiver woken up by a low frequency inductive link (as typically used in pacemakers/ICDs) or some
alternative mechanism.
ZL70100
Data Sheet
3
Zarlink Semiconductor Inc.
2.0 Example Configurations
The MICS Transceiver device is configurable as an Implant transceiver or as a Basestation transceiver. Typical
configurations are shown in the following diagrams.
Figure 2 - MICS Transceiver Configured for an Implant
Ex am ple of m atc hing
network f or a patc h
antenna.
N ote 1: * Inputs c onnec ted v ia internal pull-down to ground. U pper s ide pins do not need to be bonded out
Implantable
RF Transceiver
(Bare D ie)
V DDA 2
VSUP
RX _245A
RX _245B
V S S A _W A K E _LNA
V S S A _GE N1
RF_T X
V S S A _RF_P A
RF_RX
V S S A _RF_LNA
V S S A _GE N2
RB IA S
V S S D1
S P I_S DI
S P I_S DO
S P I_CLK
V S S D7
V DDD
P DCT RL*
V S S D2
S P I_CS _B
W U_E N
IRQ
VS
SA
_
R
F
_
VC
O
TE
S
T
I
O
[
5
]
TE
S
T
I
O
[
6
]
CL
F
1
CL
F
2
CL
F
_
RE
F
VS
SA
_
G
E
N
3
VS
SA
_
G
E
N
4
VS
SA
_
R
F
_
XO
XT
A
L
1
XT
A
L
2
TE
S
T
I
O
1
TE
S
T
I
O
2
TE
S
T
I
O
3
TE
S
T
I
O
4
VD
D
A
1
IB
S
*
X
O
_
B
YP
AS
S
PO
0
PO
1
PO
2
PO
3
VS
SD
4
PI
0
*
PI
1
*
PI
2
*
MO
D
E
0
*
MO
D
E
1
*
Applic ation
Interf ac e
N ote 2: Two s upply v oltages are required VSU P (the m ain s upply ,2.1-3.6V) and VD D IO (the digital IO v oltage
whic h m ay be 1.5V to VSU P) VD D is an on-c hip deriv ed regulated s upply whic h requires a 68 nF
dec oupling c apac itor and c onnec tion of VD D A to VD D D
68 nF
V DD (internal
regulator)
T o V S UP
T o V DD
VSSA
VSSD
VSSD
VS
SD
VSSD
V S S D8
V S S D3
VSSD
VSSD
VS
SD
6
VS
SD
1
0
VS
SD
5
VS
SD
9
VSSD
24 MHz
C1, note
3
N ote 3: C 1 is an optional D C bloc k ing c apac itor.
V DDIO
(m ain s upply)
ZL70100
Data Sheet
4
Zarlink Semiconductor Inc.
Figure 3 - MICS Transceiver Configured for a Basestation
Matching
network
dependent on
antenna
ZL70100
QFN48
VDDA
VSSA
RX_245A
RX_245B
VSSA_W AKE_LNA
RF_T X
VSSA_RF_PA
RF_RX
VSSA_RF_LNA
RBIAS
VSSD
VDDIO
SPI_SDI
SPI_SDO
SPI_CLK
VSSD
VDDD
PDCT RL*
VSSD
SPI_CS_B
W U_EN
IRQ
VSSA_
R
F
_
V
C
O
T
E
S
T
IO
[5
]
T
E
S
T
IO
[6
]
CL
F
1
CL
F
_
RE
F
VSSA_
R
F
_
X
O
XT
AL
1
XT
AL
2
T
EST
I
O
1
T
EST
I
O
2
T
EST
I
O
3
T
EST
I
O
4
I
BS*
X
O
_
BYPASS
PO
0
PO
1
PO
2
PO
3
VSSD
PI
0
*
PI
1
*
PI
2
*
MO
D
E
0
*
MO
D
E
1
*
Application
Interf ace
Note 1: For Basestation, a TCXO is recom m ended (in which case XO_BY PASS is tied high)
External RSSI / Note 2
Note 2: External RSSI Detector Sy stem is recom mended. Connection to be done either to MICS chip af ter
RSSI or direct to application
2.45 GHz Transmitter
TX245
LPF
LNA
SAW
Switc h
T o VDDIO
T CXO
(Note1)
BPF
RSSI
ADC
T o Processor
VDD (internal
regulator)
T o VSUP
(main supply)
T o VDD
T o Application Interfac e
(optional)
Note 3: Two supply v oltages are required VSUP (the m ain supply ,2.1-3.6V) and VDDIO (the digital IO v oltage
which m ay be 1.5V to VSUP) VDD is an on-chip deriv ed regulated supply which requires a 68 nF
decoupling capacitor and connection of VDDA to VDDD
T X_MODE
VSSA
VSUP
68nF
ZL70100
Data Sheet
5
Zarlink Semiconductor Inc.
3.0 Electrical Characteristics
.
Note 1: The table above lists the external conditions under which the chip shall operate according to the specifications detailed within
this document.
Note 2: Note that VDDIO must always be less than VSUP even during system startup.
Absolute Maximum ratings -
Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min.
Max.
Unit
Notes
1
Supply voltage
VSUP
0
3.6
V
2
Input voltage (Digital IO)
VDDIO
0
3.6
V
peak
rel. to VSS
3
Storage temperature
T
stg
-40
+70
C
Recommended Operating Conditions -
Note1
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
4
Supply voltage
VSUP
2.1
3.5
V
5
Input voltage (Digital IO)
VDDIO
1.5
VSUP
V
Note 2
6
Operating temperature
T
op
0
55
C
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