ZN427E8 / ZN427J8

MICROPROCESSOR COMPATIBLE

8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER

DS3006 - 2.1

Fig.2 System diagram

The ZN427 is an 8-bit successive approximation converter

with three-state outputs to permit easy interfacing to a
common data bus. The IC contains a voltage switching DAC,
a fast comparator, successive approximation logic and a
2.56V precision bandgap reference, the use of which is pin
optional to retain flexibility. An external fixed or varying
reference may therefore be substituted, thus allowing
ratiometic operation

Only passive external components are required for

operation of the converter.

FEATURES

Easy Interfacing to Microprocessor, or Operates as a
'Stand-Alone' Converter

Fast: 10 microseconds Conversion time Guaranteed

No Missing Codes over Operating Temperature Range

Data Outputs Three-State TTL Compatible, other
Logic Inputs and Output TTL and CMOS Compatible

Choice of On-Chip or External Reference Voltage

Ratiometric Operation

Unipolar or Bipolar Input Ranges

Complementary to ZN428 DAC

Commercial or Military Temperature Range

Fig.1 Pin connection - top view

ORDERING INFORMATION

ZN427J8 (DC18)
ZN427E8 (DP18)

ZN427E8

ZN427J8

DP18

DC18

C to +70

-55

C to +125

Device type

Package

Operating temperature

WR (START CONVERSION)

BUSY (END OF CONVERSION)

BIT 8

(LSB)

RD (OUTPUT ENABLE)

BIT 7

CLOCK

BIT 6

BIT 5

EXT

BIT 4

BIT 3

REF

BIT 2

REF

OUT

BIT 1

(MSB)

GROUND

(+5V)

3-STATE BUFFERS

ANALOGUE VOLTAGE SWITCHES

R-2R LADDER

LSB

MSB

SUCCESSIVE

APPROXIMATION REGISTER

COMPARATOR

D TO A OUTPUT

VCC

(+5V)

CLOCK

INPUT

REXT

VIN

WR (START CONVERSION)

VREF IN

GROUND

VREF OUT

RD (OUTPUT ENABLE)

BUSY (END CONVERSION)

+2.5V

REFERENCE

ZN427

ABSOLUTE MAXIMUM RATINGS

Supply voltage V

+7.0V

Max. voltage, logic and V

REF

input

Operating temperature range

C to +70

C (ZN427E8)

-55

C to +125

C (ZN427J8)

Storage temperature range

-55

C to +125

External Ref. 2.5V

DC Package
DP Package
V

REF IN

= 2.560V

See note 1

= +3V, R

EXT

= 82k

V - = -5V

See comparator (page x-xx)

REF

= 390

, C

REF

= 4

See reference (page x-xx)

= 5.5V, V

= max.

= 2.4V, V

= max.

= 5.5V, V

= max.

= 2.4V, V

= max.

= 0.4V, V

= max.

= max., V

= min.

= max., V

= min.

= 2.4V

See Fig.9

See note 1

-
-
-
-
-
-

12
10

2.545

1.5
4.5

-
-

-3.0
-0.5

2.475

-
-

2.0

-
-
-
-
-
-
-
-

2.4

-
-
-
-
-

250

500
900

-
-

0.5

2.5

15
13

2.550

-
-
-

125

100

-
-
-

2.560

0.5

-
-
-
-
-
-
-
-
-
-
-
-
-
-

180
160

-
-

1000

0.5

-
-
-
-
-

18
16

2.555

3.0
5.5

-
-

-30.0

3.5

2.625

0.8

50
15

100

-5

-100

1.6

0.4

-1.5
250
250

250

-
-

Min.

Typ.

Max.

Bits

LSB
LSB

ppm/

mV
mV

V
V

ppm/

V
V

ns
ns
ns
ns
ns

kHz

Parameter

Units

Conditions

Converter
Resolution
Linearity error
Differential non-linearity
Linearity error T.C.
Differential non-linearity T.C.
Full-scale (gain) T.C.
Zero T.C.
Zero transition

00000000
to 00000001

F.S. transition

11111110
to 11111111

Conversion time
External reference voltage
Supply voltage (V

)

Supply current
Power consumption

Comparator
Input current
Input resistance
Tail current, I

EXT

Negative supply, V
Input voltage

Internal voltagee reference
Output voltage
Slope resistance
V

REF

temperature coefficient

Reference current

Logic (over operating temperature range)
High level input voltage V

Low level input voltage V

High level input current,

and RD inputs I

High level input current,
Clock input I

Low level input current I

High level output current I

Low level output current I

High level output voltage V

Low level output voltage V

Disable output leakage
Input clamp diode voltage
Read input to data output
Enable/disable delay time t

Start pulse width tWR

BUSY

propagation delay t

Clock pulse width
Maximum clock frequency

ELECTRICAL CHARACTERISTICS

(at V

= 5V, T

amb

= 25

C unless otherwise specified).

Note 1: A 900kHz clock gives a conversion time of 10

s (9 clock periods).

ZN427

GENERAL CIRCUIT OPERATION

The ZN427 utilises the successive approximation technique.
Upon receipt of a negative-going pulse at the

input the

BUSY

output goes low, the MSB is set to 1 and all other bits

are set to 0, which produces an output voltage of V

REF/2

from the

DAC. This is compared to the input voltage V

; a decision is

made on the next negative clock edge to reset the

MSB to 0 if > V

or leave it set to 1 if < V

Bit 2 is set to 1 on the same clock edge, producing an output

from the DAC of or + depending on the state

of the MSB. This voltage is compared to V

and on the next

clock edge a decision is made regarding bit 2, whilst bit 3 is set

REF

to 1. This procedure is repeated for all eight bits. On the ninth
negative clock edge

BUSY

goes high indicating that the

conversion is complete.

During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking

high, thus enabling the

three-state output. Readout is non-destructive. The

BUSY

output may be tied to the RD input to automatically enable the
outputs when the data is valid.

For reliable operation of the converter the start pulse applied
to the

input must meet certain timing criteria with respect

to the converter clock. These are detailed in the timing
diagram of Fig.3.

Fig.3 Timing diagram

NOTES ON TIMING DIAGRAM

1. A conversion sequence is shown for the digital word
01100110. For clarity the three-state outputs are shown as
being enabled during the conversion, but normal practice
would be to disable them until the conversion was complete.

2. The

BUSY

output goes low during a conversion. When

BUSY

goes high at the end of a conversion the output data is

valid. In a microprocessor system the

BUSY

output can be

used to generate an interrupt request when the conversion is
complete.

ZN427

PRACTICAL CLOCK AND SYNCHRONISING
CIRCUITS

The actual method of generating the clock signal and
synchronising it to the start conversion system in which the
ZN427 is incorporated.

When used with a microprocessor the ZN427 can be treated
as RAM and can be assigned a memory address using an
address decoder. If the

P clock is used to drive the ZN427

and the

P write pulse meets the ZN427 timing criteria with

respect to the

P clock then generating the start pulse is

simply a matter of gating the decoded address with the
microprocessor write pulse. Whilst the conversion is being
performed the microprocesor can perform other instructions
or No operation (NOP). when the conversion is complete the
outputs can be enabled onto the bus by gating the decoded
address with the read pulse. A timing diagram for this
sequence of operation is given in Fig.4.

An advantage of using the microprocessor clock is that the
conversion time is known precisely in terms of machine
cycles. the data outputs may therefore be read after a fixed
delay of at least nine clock cycles after the end of the

pulse, when the conversion will be complete.

Alternatively the read operation may be initiated by using the

BUSY

output to generate interrupt request.

3. In the timing diagram cross hatching indicates a 'don't
care' condition.

4. The start pulse operates as an asynchronous
(independent of clock) reset that sets the MSB output to 1 and
sets all other outputs and the end of conversion flag to 0. This
resetting occurs on the low-going edge of the start pulse and
as long as

is low the converter is inhibited. Conversion

commences on the first active (negative going) clock edge
after the

input has gone high again, when the MSB

decision is made. A number of timing constraints thus supply
to the start pulse.

(a) The minimum duration of the start pulse is 250ns, to allow
reliable resetting of the converter logic circuits.

(b) There is no limit to the maximum duration of the start pulse.

s must elapse

between the negative going edge of the start pulse and the first
active clock edge that indicates the MSB desicion.

(d) To ensure relaible clocking the positive-going edge of the
start pulse should not occur within 200ns of an active
(negative-going) clock edge. The ideal place for the positive-
going edge of the start pulse is coincident with a positive-going
clock edge. As a special case of the above conditions that
start pulse may be synchronous with a negative-going clock
pulse.

Fig.4 Typical timing diagram using

P clock and write pulse

In some systems, for example single-chip microcomputers
such as the 8048, this simple method may not be feasible for
one or more of the following reasons:

(a) The MPU clock is not available externally.

(b) The clock frequency is too high.

ZN427

N1 is connected as an astable multivibrator which, when the

BUSY

output is high, is inhibited by the output of N2 holding

one of its inputs low. The start conversion pulse resets the

BUSY

flag and N1 begins to oscillate. When the conversion

is complete

BUSY

goes high and the clock is inhibited.

Since the start pulse starts the clock it may occur at any time.
The only constraints on the start pulse are that it must be
longer than 250ns but at least 200ns shorter than the first clock
pulse. The first clock pulse is in fact longer than the rest since

C1 starts from a fully charged condition whereas on
subsequent cycles it changes between the upper and lower
threshold (V

T+

and V

) of the Schmitt trigger.

LOGIC INPUTS AND OUTPUTS

The logic inputs of the ZN427 utilise the emitter-follower
configuration shown in Fig.6. This gives extremely low input
currents for CMOS as well as TTL compatibility.

Fig.6 Equivalent circuit of all inputs

Fig.7

The data outputs have three-state buffers, an equivalent
circuit of which is shown in Fig.8. Whilst the RD input is low
both output transistors are turned off and the output is in a high

The

BUSY

output, shown in Fig.7, utilises a passive pullup for CMOS/TTL compatibility.

impedance state. When RD is high the data output will
assume the appropriate logic state (0 or 1).

ZN427

ANALOG CIRCUITS

D-A converter
IThe converter is of the voltage switching type and uses an R-
2R ladder network as shown in Fig.10. Each element is
connected to either 0V or V

REF

IN by transistor voltage switches

specially designed for low offset voltage (<1mV).

A binary weighted voltage is produced at the output of the R-
2R ladder.

D to A output = n (V

REF

IN -V

) + V

256
where n is the digital input to the D-A from successive
approximation register.

is a small offset voltage that is produced by the device

supply current flowing in the package lead resistance. The
value of V

is typically 2mV for the ZN427E8 and 4mV for the

ZN427J8.

This offset will normally be removed by the setting up
procedure and since the offset temperature coefficient is low
(8

C), the effect on accuaracy will be negligible.

The D-A output range can be considered to be 0 - V

REF IN

through an output resistance R (4k).

REFERENCE
(a) Internal reference
The internal reference is an active bandgap circuit which is
equivalent to a 2.5V Zener diode with a very low slope
impedance (Fig.11). A Resistor (R

REF

) should be connected

between pins 8 and 10. The recommended value of 390

will

supply a nominal reference current of (5.0 - 2.5)/0.39=6.4mA.
A stabilising/decoupling capacitor, C

REF

7), is required

between pins 8 and 9. For internal reference operation V

REF

OUT (pin 8) is connected to V

REF

IN (pin 7).

UP to five ZN427's may be driven from one internal reference,
there being no need to reduce R

REF

. This useful feature saves

power and gives excellent gain tracking between the
converters.

Alternatively the internal reference can be used as the
reference voltage for other external circuits and can source or
sink up to 3mA.

Fig.10 R-2R ladder network

R(4k)

D TO A OUTPUT

BIT 2

BIT 8

VOS

BIT 7

BIT 1
MSB

0 VOLTS
(PIN 9)

VREF IN
(PIN 7)

VOLTAGE

SWITCHES

ZN427

GROUND

(PIN 9)

CREF

(4.7µ)

RREF

(390)

VREF OUT

(PIN 8)

VCC +5V

(PIN 10)

Fig.11 Internal voltage reference

(b) External reference
If required an external reference in the range +1.5 to +3.0V
may be connected to V

REF

IN. The slope resistance of such a

reference source should be less than 2.5

, where n is the

number of converters supplied.

RATIOMETRIC OPERATION

If the output from a transducer varies with its supply then an
external reference for the ZN427 should be derived from the

same supply. The external reference can vary from +1.5 to
+3.0V. The ZN448/9 will operate if V

REF

IN is less than +1.5V

but reduced overdrive to the comparator will increase its delay
and so the conversion time will need to be increased.

COMPARATOR

The ZN427 contains a fast comparator, the equivalent input
circuit of which is shown in Fig.12.

Fig.12 Comparator equivalent circuit

PIN 5

V -

TO LOGIC
HIGH = 'RETAIN BIT'

D TO A OUTPUT
(O - VREF IN)

AIN

RIN

VIN

PIN 6

+5V PIN 10

REXT

IEXT

ZN427

The comparator derives the tail current, I

EXT

, for its first stage

from an external resistor, R

EXT

, which is taken to a negative

supply V.

This arrangement allows the ZN427 to work with any negative
supply in the range -3 to -30 volts. the ZN427 is designed to
be insensitive to changes in I

EXT

from 25

A to 150

A. The

suggested nominal value of I

EXT

is 65

A and a suitable value

for R

EXT

is given by R

EXT

= |V_|15k

(volts)

-3
-5
-10
-12
-15
-20
-25
-30

EXT

(

10%)

47k

82k

150k

180k

220k

330k

390k

470k

The output from the D-A converter is connected through the
4k

ladder resistance to one side of the comparator. The

analog input to be converted could be connected directly to the
other comparator input (V

, pin 6) but for optimum stability

with temperature the analog input should be applied through
a source resistance (R

= 4k

) to match the ladder

resistance).

ANALOG INPUT RANGES

The basic connection of the ZN427 shown in Fig.13 has an
analog input range 0 to V

REF

IN which, in some applications,

may be made available from previous signal conditioning/
scaling circuits. Input voltage ranges greater than this are
accommodated by providing an attenuator on the comparator
input, whilst for smaller input ranges the signal must be
amplified to a suitable level.

Bipolar input ranges are accommodated by off-setting the
analog input input range so that the comparator always sees
a positive input voltage.

Fig.13 External components for basic operation

LSB

BIT 8

MSB

BIT 1

VCC

(+5V)

BUSY

V-

(-5V)

AIN

VREFIN

VREFOUT

GND

(0V)

RREF

(390

)

REXT

(82k)

RIN
(4k)

VIN

CREF

(4µ7)

DIGITAL OUTPUTS

NOMINAL AIN RANGE = 0 TO VREFIN

ZN427

UNIPOLAR OPERATION

The general connection for unipolar operation is shown in
Fig.14.

The values of R

and R

are chosen so that V

= V

REF

IN when

the analogue input (A

) is at full-scale.

The resulting full-scale range is given by:

FS = 1 + , V

REF

IN = G.V

REF

IN.

To match the ladder resistance R

) = 4k

The required nominal values of R

and R

are given by

= 4Gk, R

= 4G k

G-1

Fig.14 Unipolar operation - general connection

680k

ZERO

ADJUST

GROUND

ZN427

VIN

AIN

VREF IN

Using these relationships a table of nominal values of R

and

can be constructed for V

REF

IN = 2.5V.

Gain adjustment
Due to tolerance in R

and R

, tolerance in V

REF

and the gain

(full-scale) error of the DAC, some adjustment should be
incorporated into R

to calibrate the full-scale of the converter.

When used with the internal reference and 2% resistors a
preset capable of adjusting R

by at least

5% of its nominal

value is suggested.

5.33k

16k

2
4

Input range

+5V

+10V

Zero adjustment
Due to offsets in the DAC and comparator the zero (0 to 1)
code transition would occur with typically 15mV applied to the
comparator input, which correpsonds to 1.5LSB with a 2.56V
reference.

Zero adjustment must therefore be provided to set the zero
transition to its correct value of +0.5LSB or 5mV with a 2.56V
reference. This is achieved by applying an adjustable positive
offset to the comparator input via P2 and R3. The values
shown are suitable for all input ranges greater than 1.5 times
V

REF

IN.

Practical circuit values for +5 and +10V input ranges are given
in Fig.15, which incorporates both zero and gain adjustments.

ZN427

Fig.15 Unipolar operation - component values

AIN

VREF IN

TO PIN 6

R1 11k

R2 5k6

680k

P1 10k

GAIN

ADJUST

ZERO

ADJUST

± 2% RESISTORS

±20% POTENTIOMETERS

AIN

VREF IN

TO PIN 6

R1 5k6

R2 8k2

680k

P1 5k

GAIN

ADJUST

ZERO

ADJUST

+5V FULL-SCALE

+10V FULL-SCALE

Unipolar adjustment prodedure

(i) Apply continuous convert pulses at intervals long enough

to allow a complete conversion and monitor the digital
outputs.

(ii) Apply full-scale minus 1.5LSB to A

and adjust off-set until

the 8 bit (LSB) output just flickers between 0 and 1 with all
other bits at 0.

(iii) Apply 0.5LSB) to A

and adjust zero until 8 bit just flickers

between 0 and 1 with all other bits at 1.

Unipolar logic coding

Analogue input (A

)

(Nominal code centre value)

FS - 1LSB
FS - 2LSB
0.75FS
0.5FS + 1LSB
0.5FS
0.5FS - 1LSB
0.25FS
1LSB
0

Output code

(offset binary)

11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000

1LSB = FS
256

Unipolar setting up points

FS - 1.5LSB

4.9707V
9.9414V

Input range, +FS

+5V

+10V

0.5LSB

9.8mV

19.5mV

ZN427

BIPOLAR OPERATION

For bipolar operation the input to the ZN427 is offset by half
full-scale by connecting a resistor R

between V

REF

IN and V

(Fig.16).

Fig.16 Bipolar operation - general connection

GROUND

ZN427

VIN

AIN

VREF IN

When A

= -FS, V

needs to be equal to zero.

When A

= +FS, V

needs to be equal to V

REF

IN.

If the full-scale range is

G. V

REF

IN then R

= (G - 1). R

and

= G. R

fulfil the required conditions.

To match the ladder resistance, R

(=R

) = 4k.

Thus the nominal values of R

, R

are given by R

= 8 Gk

= 8G/(G - 1)k, R

= 8k

A bipolar range of

REF

IN (which corresponds to the basic

unipolar range 0 to +V

REF

IN) results if R

= R

= 8k

and R

Assuming the V

REF IN

= 2.5V the nominal values of resistors for

5 and

10V input ranges are given in the following table.

16k

10.66k

16k

32k

2
4

Input range

+5V

+10V

Minus full-scale (offset) is set by adjusting R

about its nominal

value relative to R

. Plus full-scale (gain) is set by adjusting R

relative to R

Practical circuit realisations are given in Fig.17.

Note that in the

5V case R

has been chosen as 7.5k (instead

of 8.2k) to obtain a more symmetrical range of adjustment
using standard potentiometers.

ZN427

Fig.17 Bipolar operation - component values

AIN

VREF

TO PIN 6

13k

7k5

OFFSET
ADJUST

GAIN

ADJUST

± 2% RESISTORS

±20% POTENTIOMETERS

±5VOLTS FULL SCALE

AIN

VREF

TO PIN 6

27k

8k2

10k

OFFSET
ADJUST

8k2

GAIN

ADJUST

±10VOLTS FULL SCALE

Bipolar adjustment prodedure

(i) Apply continuous SC pulses at intervals long enough to

allow a complete conversion and monitor the digital
outputs.

(ii) Apply -(FS -0.5LSB) to A

and adjust off-set until the 8 bit

(LSB) output just flickers between 0 and 1 with all other bits
at 0.

(iii) Apply +(FS -1.5LSB) to A

and adjust gain until the 8 bit

just flickers between 0 and 1 with all other bits at 1.

(iv) Repeat step (ii).

Bipolar setting up points

+(FS -1.5LSB)

+4.9414V
+9.8828V

Input range,

+5V

+10V

-(FS -0.5LSB)

-4.9805V
-9.9609V

Bipolar logic coding

Analogue input (A

)

(Nominal code centre value)

+(FS - 1LSB)
+(FS - 2LSB)
+0.5FS
+1LSB
0
-1LSB
-0.5FS
-(FS - 1LSB)
-FS

Output code

(offset binary)

11111111
11111110
11000000
10000001
10000000
01111111
01000000
00000001
00000000

1LSB =2FS
265

ZN427

HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
Fax: (0793) 518411

GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576

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